SOC for car navigation system with a 55.3GOPS image recognition engine

In the SoC, the system bus makes a bottleneck for data communication in high speed on a chip. In addition, the system allows multiple bus layers for efficient management of the bus resources on a SoC. In this paper, we present a latency model of the ...

With the rapid development of semiconductor technology, more complicated systems have been integrated into single chips. However, system performance is not increased in proportion to the gate-count of the system. This is mainly because the optimized ...

The performance of a multiprocessor system heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor system-on-a-chip (SoC). Our bus-synthesis tool, which we call ...