article

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)

Authors:

Hyun-min Kyung,

Jong Wook Kwak,

Sung-Bae ParkAuthors Info & Claims

Microprocessors & Microsystems, Volume 34, Issue 2-4

Pages 102 - 116

https://doi.org/10.1016/j.micpro.2010.03.001

Published: 01 March 2010 Publication History

Abstract

With the rapid development of semiconductor technology, more complicated systems have been integrated into single chips. However, system performance is not increased in proportion to the gate-count of the system. This is mainly because the optimized design of the system becomes more difficult as the systems become more complicated. Therefore, it is essential to understand the internal behavior of the system and utilize the system resources effectively in the System on Chip (SOC) design. In this paper, we design a Performance Analysis Unit (PAU) for monitoring the AMBA Advanced eXtensible Interface (AXI) bus as a mechanism to investigate the internal and dynamic behavior of an SOC, especially for internal bus activities. A case study with the PAU for an H.264 decoder application is also presented to show how the PAU is utilized in SOC platform. The PAU has the capability to measure major system performance metrics, such as bus latency, amount of bus traffic, contention between master/slave devices, and bus utilization for specific durations. This paper also presents a distributor and synchronization method to connect multiple PAUs to monitor multiple internal buses of large SOC.

References

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AMBA specification (Rev 2.0), ARM, 1999.

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AMBA AXI Protocol Specification v1.0, ARM, 2003.

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PrimeCell AXI Configurable Interconnect (PL300) Technical Reference Manual, ARM, 2004.

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AMBA 3 High Performance Matrix (PL301) Technical Reference Manual r0p0, 2006.

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G.H. Park, H.M. Kyung, J.B Im, et al., Architecture Exploration and Performance Verification Environments for Multi-core SOC for Mobile Multimedia Embedded Systems, WARFP, February, 2006.

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H.M. Kyung, G.H. Park, J.W. Kwak, et al., Performance Monitor Unit Design for an AXI-based Multi-core SOC Platform, SAC ACM, March, 2007.

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Burkhart, H. and Millen, R., Performance-measurement tools in a multiprocessor environment. IEEE Transactions on Computer. v38 iMay.

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Lahiri, K., Raghunathan, A., Lakshminarayana, G. and Dey, S., Design of high performance system-on-chips using communication architecture tuners. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems. v23 i5. 620-636.

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Lahiri, K., Raghunathan, A. and Dey, S., System-level performance analysis for designing on-chip communication architectures. IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems. v20 iJune. 768-783.

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Cited By

Restuccia FKastner R(2022)Cut and Forward: Safe and Secure Communication for FPGA System on ChipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319734341:11(4052-4063)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1109/TCAD.2022.3197343
Valente GFanni TSau CMascio TPomante LPalumbo F(2021)A Composable Monitoring System for Heterogeneous Embedded PlatformsACM Transactions on Embedded Computing Systems10.1145/346164720:5(1-34)Online publication date: 9-Jul-2021
https://dl.acm.org/doi/10.1145/3461647

Index Terms

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC)
1. General and reference
  1. Cross-computing tools and techniques
    1. Performance
2. Social and professional topics
  1. Professional topics
    1. Computing profession
      1. Testing, certification and licensing

Index terms have been assigned to the content through auto-classification.

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Published In

cover image Microprocessors & Microsystems

Microprocessors & Microsystems Volume 34, Issue 2-4

March, 2010

55 pages

ISSN:0141-9331

Issue’s Table of Contents

Copyright © Elsevier B.V. © 2010.

Publisher

Elsevier Science Publishers B. V.

Netherlands

Publication History

Published: 01 March 2010

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Cited By

Restuccia FKastner R(2022)Cut and Forward: Safe and Secure Communication for FPGA System on ChipsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319734341:11(4052-4063)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1109/TCAD.2022.3197343
Valente GFanni TSau CMascio TPomante LPalumbo F(2021)A Composable Monitoring System for Heterogeneous Embedded PlatformsACM Transactions on Embedded Computing Systems10.1145/346164720:5(1-34)Online publication date: 9-Jul-2021
https://dl.acm.org/doi/10.1145/3461647

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