Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.5555/3201607.3201662acmconferencesArticle/Chapter ViewAbstractPublication PagesaspdacConference Proceedingsconference-collections
research-article

A practical split manufacturing framework for trojan prevention via simultaneous wire lifting and cell insertion

Published: 22 January 2018 Publication History

Abstract

Trojans and backdoors inserted by untrusted foundries have become serious threats to hardware security. Split manufacturing is proposed to prevent Trojan insertion proactively. Existing methods depend on wire lifting to hide partial circuit interconnections, which usually suffer from large overhead and lack of security guarantee. In this paper, we propose a novel split manufacturing framework that not only guarantees to achieve the required security level but also allows for a drastic reduction of the introduced overhead. In our framework, insertion of dummy circuit cells and wires is considered simultaneously with wire lifting. To support cell and wire insertion, we propose a new security criterion, and further derive its sufficient condition to avoid computation intensive operations in traditional methods. Then, for the first time, a novel mixed integer linear programming formulation is proposed to simultaneously consider cell and wire insertion together with wire lifting, which significantly enlarges the design space to guarantee the realization of the sufficient condition under the security requirements and overhead constraints. With extensive experimental results, our framework demonstrates much better efficiency, overhead reduction, and security guarantee compared with existing methods.

References

[1]
M. Tehranipoor and F. Koushanfar, "A survey of hardware trojan taxonomy and detection," IEEE MDTC, vol. 27, no. 1, pp. 10--25, 2010.
[2]
S. Bhasin and F. Regazzoni, "A survey on hardware trojan detection techniques," in Proc. ISCAS, 2015.
[3]
K. Yang, M. Hicks, Q. Dong, T. Austin, and D. Sylvester, "A2: Analog malicious hardware," in Proc. SP, 2016.
[4]
C. Krieg, C. Wolf, and A. Jantsch, "Malicious LUT: a stealthy FPGA trojan injected and triggered by the design flow," in Proc. ICCAD, 2016.
[5]
R. Torrance and D. James, "The state-of-the-art in semiconductor reverse engineering," in Proc. DAC, 2011, pp. 333--338.
[6]
K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin, "AppSAT: Approximately deobfuscating integrated circuits," in Proc. HOST, 2017.
[7]
J. Rajendran, M. Sam, O. Sinanoglu, and R. Karri, "Security analysis of integrated circuit camouflaging," in Proc. CCS, 2013.
[8]
M. Li, K. Shamsi, T. Meade, Z. Zhao, B. Yu, Y. Jin, and D. Z. Pan, "Provably secure camouflaging strategy for IC protection," in Proc. ICCAD, 2016.
[9]
K. Shamsi, M. Li, T. Meade, Z. Zhao, D. Z. Pan, and Y. Jin, "Cyclic obfuscation for creating sat-unresolvable circuits," in Proc. GLSVLSI, 2017.
[10]
Y. Xie, C. Bao, and A. Srivastava, "Security-aware design flow for 2.5D IC technology," in Proc. TrustED, 2015.
[11]
K. Vaidyanathan, R. Liu, E. Sumbul, Q. Zhu, F. Franchetti, and L. Pileggi, "Efficient and secure intellectual property (IP) design with split fabrication," in Proc. HOST, 2014.
[12]
B. Hill, R. Karmazin, C. T. O. Otero, J. Tse, and R. Manohar, "A split-foundry asynchronous FPGA," in Proc. CICC, 2013.
[13]
J. Valamehr, T. Sherwood, R. Kastner, D. Marangoni-Simonsen, T. Huffmire, C. Irvine, and T. Levin, "A 3-D split manufacturing approach to trustworthy system development," IEEE TCAD, vol. 32, no. 4, pp. 611--615, 2013.
[14]
K. Vaidyanathan, B. P. Das, and L. Pileggi, "Detecting reliability attacks during split fabrication using test-only BEOL stack," in Proc. DAC, 2014.
[15]
K. Xiao, D. Forte, and M. M. Tehranipoor, "Efficient and secure split manufacturing via obfuscated built-in self-authentication," in Proc. HOST, 2015.
[16]
F. Imeson, A. Emtenan, S. Garg, and M. V. Tripunitara, "Securing computer hardware using 3D integrated circuit (IC) technology and split manufacturing for obfuscation," in Proc. USENIX Security Symposium, 2013.
[17]
J. Rajendran, O. Sinanoglu, and R. Karri, "Is split manufacturing secure?" in Proc. DATE, 2013.
[18]
Y. Wang, P. Chen, J. Hu, and J. Rajendran, "The cat and mouse in split manufacturing," in Proc. DAC, 2016.
[19]
J. Magaña, D. Shi, and A. Davoodi, "Are proximity attacks a threat to the security of split manufacturing of integrated circuits?" in Proc. ICCAD, 2016.
[20]
J. Cheng, A. W.-C. Fu, and J. Liu, "K-isomorphism: privacy preserving network publication against structural attacks," in Proc. SIGMOD, 2010.
[21]
S. Skorobogatov and C. Woods, "Breakthrough silicon scanning discovers backdoor in military chip," in Proc. CHES, 2012.
[22]
D. B. West, Introduction to Graph Theory. Prentice Hall, 2000.
[23]
H. Salmani, M. Tehranipoor, and R. Karri, "On design vulnerability analysis and trust benchmarks development," in Proc. ICCD, 2013.
[24]
F. Brglez, D. Bryan, and K. Koámiński, "Combinational profiles of sequential benchmark circuits," in Proc. ISCAS, 1989.
[25]
"Cadence SOC Encounter," http://www.cadence.com.
[26]
G. Karypis and V. Kumar, "Analysis of multilevel graph partitioning," in Proc. Supercomputing. ACM, 1995.

Cited By

View all
  • (2019)Protect Your Chip Design Intellectual PropertyProceedings of the International Conference on Omni-Layer Intelligent Systems10.1145/3312614.3312657(211-216)Online publication date: 5-May-2019
  • (2019)Layout recognition attacks on split manufacturingProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287698(45-50)Online publication date: 21-Jan-2019
  • (2018)Concerted wire liftingProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201660(251-258)Online publication date: 22-Jan-2018

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ASPDAC '18: Proceedings of the 23rd Asia and South Pacific Design Automation Conference
January 2018
774 pages

Sponsors

Publisher

IEEE Press

Publication History

Published: 22 January 2018

Check for updates

Qualifiers

  • Research-article

Conference

ASPDAC '18
Sponsor:

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • Downloads (Last 12 months)2
  • Downloads (Last 6 weeks)0
Reflects downloads up to 16 Oct 2024

Other Metrics

Citations

Cited By

View all
  • (2019)Protect Your Chip Design Intellectual PropertyProceedings of the International Conference on Omni-Layer Intelligent Systems10.1145/3312614.3312657(211-216)Online publication date: 5-May-2019
  • (2019)Layout recognition attacks on split manufacturingProceedings of the 24th Asia and South Pacific Design Automation Conference10.1145/3287624.3287698(45-50)Online publication date: 21-Jan-2019
  • (2018)Concerted wire liftingProceedings of the 23rd Asia and South Pacific Design Automation Conference10.5555/3201607.3201660(251-258)Online publication date: 22-Jan-2018

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media