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Layout recognition attacks on split manufacturing

Published: 21 January 2019 Publication History

Abstract

One technique to prevent attacks from an untrusted foundry is split manufacturing, where only a part of the layout is sent to the untrusted high-end foundry, and the rest is manufactured at a trusted low-end foundry. The untrusted foundry has front-end-of-line (FEOL) layout and the original circuit netlist and attempts to identify critical components on the layout for Trojan insertion. Although defense methods for this scenario have been developed, the corresponding attack technique is not well explored. For instance, Boolean satisfiability (SAT) based bijective mapping attack is mentioned without detailed research. Hence, the defense methods are mostly evaluated with the k-security metric without actual attacks. We provide the first systematic study, to the best of our knowledge, on attack techniques in this scenario. Besides of implementing SAT-based bijective mapping attack, we develop a new attack technique based on structural pattern matching. Experimental comparison with bijective mapping attack shows that the new attack technique achieves about the same success rate with much faster speed for cases without the k-security defense, and has a much better success rate at the same runtime for cases with k-security defense. The results offer an alternative and practical interpretation for k-security in split manufacturing.

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cover image ACM Conferences
ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference
January 2019
794 pages
ISBN:9781450360074
DOI:10.1145/3287624
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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  • IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
  • IEEE CAS
  • IEEE CEDA
  • IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2019

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Author Tags

  1. hardware security
  2. layout recognition attack
  3. split manufacturing

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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  • (2021)TAALACM Transactions on Design Automation of Electronic Systems10.1145/344237926:4(1-22)Online publication date: 9-Mar-2021
  • (2021)ObfusXProceedings of the 26th Asia and South Pacific Design Automation Conference10.1145/3394885.3431600(548-554)Online publication date: 18-Jan-2021
  • (2021)Design Constraint Based AttacksSplit Manufacturing of Integrated Circuits for Hardware Security and Trust10.1007/978-3-030-73445-9_2(31-62)Online publication date: 13-Mar-2021
  • (2020)How Secure Is Split Manufacturing in Preventing Hardware Trojan?ACM Transactions on Design Automation of Electronic Systems10.1145/337816325:2(1-23)Online publication date: 2-Mar-2020
  • (2020)Special Session: Novel Attacks on Logic-Locking2020 IEEE 38th VLSI Test Symposium (VTS)10.1109/VTS48691.2020.9107641(1-10)Online publication date: Apr-2020
  • (2019)Protect Your Chip Design Intellectual PropertyProceedings of the International Conference on Omni-Layer Intelligent Systems10.1145/3312614.3312657(211-216)Online publication date: 5-May-2019
  • (2019)Analysis of Security of Split Manufacturing Using Machine LearningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.292971027:12(2767-2780)Online publication date: Dec-2019
  • (2012)IntroductionThe Next Era in Hardware Security10.1007/978-3-030-85792-9_1(1-34)Online publication date: 24-Feb-2012

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