research-article

TAAL: Tampering Attack on Any Key-based Logic Locked Circuits

Authors:

Ujjwal GuinAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 26, Issue 4

Article No.: 28, Pages 1 - 22

https://doi.org/10.1145/3442379

Published: 09 March 2021 Publication History

Abstract

Due to the globalization of semiconductor manufacturing and test processes, the system-on-a-chip (SoC) designers no longer design the complete SoC and manufacture chips on their own. This outsourcing of the design and manufacturing of Integrated Circuits (ICs) has resulted in several threats, such as overproduction of ICs, sale of out-of-specification/rejected ICs, and piracy of Intellectual Properties (IPs). Logic locking has emerged as a promising defense strategy against these threats. However, various attacks about the extraction of secret keys have undermined the security of logic locking techniques. Over the years, researchers have proposed different techniques to prevent existing attacks. In this article, we propose a novel attack that can break any logic locking techniques that rely on the stored secret key. This proposed TAAL attack is based on implanting a hardware Trojan in the netlist, which leaks the secret key to an adversary once activated. As an untrusted foundry can extract the netlist of a design from the layout/mask information, it is feasible to implement such a hardware Trojan. All three proposed types of TAAL attacks can be used for extracting secret keys. We have introduced the models for both the combinational and sequential hardware Trojans that evade manufacturing tests. An adversary only needs to choose one hardware Trojan out of a large set of all possible Trojans to launch the TAAL attack.

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cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 26, Issue 4

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July 2021

209 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/3447538

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University of Notre Dame, USA

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Publication History

Published: 09 March 2021

Accepted: 01 December 2020

Revised: 01 November 2020

Received: 01 April 2020

Published in TODAES Volume 26, Issue 4

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Kamali H(2024)From Full-Custom to Gate-Array ASIC for Hardware IP Protection2024 IEEE 17th Dallas Circuits and Systems Conference (DCAS)10.1109/DCAS61159.2024.10539912(1-5)Online publication date: 19-Apr-2024
https://doi.org/10.1109/DCAS61159.2024.10539912
Rahman MZamiri Azar KFarahmandi FMardani Kamali HThapliyal HDeMara RPartin-Vaisband IKatkoori S(2023)Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic LockingProceedings of the Great Lakes Symposium on VLSI 202310.1145/3583781.3590273(685-690)Online publication date: 5-Jun-2023
https://dl.acm.org/doi/10.1145/3583781.3590273
Zhong YGuin U(2023)Complexity Analysis of the SAT Attack on Logic LockingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2023.324093342:10(3143-3156)Online publication date: 30-Jan-2023
https://dl.acm.org/doi/10.1109/TCAD.2023.3240933
Leonid TSai T NSharma PB R(2023)Securing the Digital Devices Through System on Chip Control and External Attack Detection Using FPGA2023 International Conference on Data Science and Network Security (ICDSNS)10.1109/ICDSNS58469.2023.10245853(1-5)Online publication date: 28-Jul-2023
https://doi.org/10.1109/ICDSNS58469.2023.10245853
Bokor Siddik MAlam S(2023)PUF-based Hardware Trojan: Design and Novel Attack on Encryption Circuit2023 International Conference on Electrical, Computer and Communication Engineering (ECCE)10.1109/ECCE57851.2023.10101599(1-5)Online publication date: 23-Feb-2023
https://doi.org/10.1109/ECCE57851.2023.10101599
Jadhav GShukla SSingh V(2023)On Attacking Scan-based Logic Locking Schemes2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)10.1109/DFT59622.2023.10313561(1-4)Online publication date: 3-Oct-2023
https://doi.org/10.1109/DFT59622.2023.10313561
Sharma RSharma GPattanaik MPrashant V(2023)Structural and SCOAP Features Based Approach for Hardware Trojan Detection Using SHAP and Light Gradient Boosting ModelJournal of Electronic Testing: Theory and Applications10.1007/s10836-023-06080-939:4(465-485)Online publication date: 22-Sep-2023
https://dl.acm.org/doi/10.1007/s10836-023-06080-9
Zamiri Azar KMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KMardani Kamali HFarahmandi FTehranipoor M(2023)Design-for-Testability and Its Impact on Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_9(213-249)Online publication date: 23-Sep-2023
https://doi.org/10.1007/978-3-031-37989-5_9
Zamiri Azar KMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KMardani Kamali HFarahmandi FTehranipoor M(2023)Multilayer Approach to Logic LockingUnderstanding Logic Locking10.1007/978-3-031-37989-5_11(279-307)Online publication date: 23-Sep-2023
https://doi.org/10.1007/978-3-031-37989-5_11
Alrahis LPatnaik SHanif MSaleh HShafique MSinanoglu O(2022)GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-Based Oracle-Less Unlocking Schemes for Provably Secure Logic LockingIEEE Transactions on Emerging Topics in Computing10.1109/TETC.2021.310848710:3(1575-1592)Online publication date: 1-Jul-2022
https://doi.org/10.1109/TETC.2021.3108487
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