STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience
Rapid growth in Deep Neural Network (DNN) workloads has increased the energy footprint of the Artificial Intelligence (AI) computing realm. For optimum energy efficiency, we propose operating a DNN hardware in the Low-Power Computing (LPC) region. However,...
Global Placement Exploiting Soft 2D Regularity
Cell placement is a step of paramount importance in chip physical design and requests relentless effort for continuous improvement. Recently, designs with two-dimensional (2D) processing element arrays have become popular primarily due to their deep ...
Physics-Informed Learning Based Multiphysics Simulation for Fast Transient TSV Electromigration Analysis
Through Silicon Vias (TSVs) are vulnerable to electromigration (EM) degradation due to their high local current densities, thereby reducing the reliability of 3D ICs with stack dies and TSVs. Due to the broad application of 3D ICs, it is necessary to ...
Harnessing Machine Learning in Dynamic Thermal Management in Embedded CPU-GPU Platforms
With increasing transistor density, modern heterogeneous embedded processors often exhibit high temperature gradients due to complex application scheduling scenarios which may have missed design considerations. In many use cases, off-chip ”active” cooling ...
SIMTAM: Generation Diversity Test Programs for FPGA Simulation Tools Testing Via Timing Area Mutation
Field-Programmable Gate Array (FPGA) timing simulation is essential in electronic circuit design, allowing for the verification of timing characteristics like delays and clock frequencies. However, bugs in timing simulation tools can lead to inaccurate ...
PACE: A Piece-Wise Approximate Floating-Point Divider with Runtime Configurability and High Energy Efficiency
Approximate computing emerges as a viable solution to enhance energy efficiency in applications sensitive to human perception, particularly on edge devices. This work introduces a novel piece-wise approximate floating-point divider that boasts resource ...
ISOAcc: In-situ Shift Operation-based Accelerator For Efficient in-SRAM Multiplication
Digital SRAM-based CIM architectures must balance three critical factors: quantized neural network bitwidth, accuracy loss, and computational efficiency, each crucial to optimizing performance and efficiency. In Domain Specific Accelerators (DSAs), ...
Enhancing the Effectiveness of STLs for GPUs via Bounded Model Checking
- Nikolaos Deligiannis,
- Tobias Faller,
- Josie Esteban Rodriguez Condia,
- Riccardo Cantoro,
- Bernd Becker,
- Matteo Sonza Reorda
Graphics Processing Units (GPUs) are becoming widespread, even in safety-critical applications. In that case, it is imperative to guarantee that the probability of producing critical failures due to hardware faults is lower than a given threshold. To ...
