Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
skip to main content
10.5555/603095.603205acmconferencesArticle/Chapter ViewAbstractPublication PagesiccadConference Proceedingsconference-collections
Article

Algorithm level re-computing: a register transfer level concurrent error detection technique

Published: 04 November 2001 Publication History

Abstract

In this paper we propose two algorithm-level time redundancy based Concurrent Error Detection (CED) schemes that exploit diversity in a Register Transfer (RT) level implementation. RT level diversity can be achieved either by changing the operation-to-operator allocation (allocation diversity) or by shifting the operands before re-computation (data diversity). By enabling a fault to affect the normal result and the re-computed result in two different ways, RT level diversity yields good CED capability with low area overhead. We used Synopsys Behavior Complier (BC) to implement the technique.

References

[1]
J.H. Patel, L.Y. Fung, "Concurrent Error Detection in ALUs by Recomputing with Shifted Operands," IEEE Transaction on Computer, Vol. C.31, No.7, pp. 589 - 595, Jul. 1982.
[2]
J.H. Patel, L. Fung, "Concurrent Error Detection in Multiply and Divide Arrays," IEEE Transactions on Computer, Vol. c32, No. 4, pp. 417-422, Apr. 1983.
[3]
R. H. Minero, A.J. Anello, R.G. Furey, L.R Palounek, "Checking by Pseuduplication," US3660646, May 1972.
[4]
B.W. Johnson, J.H. Aylor, H.H. Hana, "Efficient Use of Time and Hardware Redundancy for Concurrent Error Detection in a 32-bit VLSI Adder," IEEE Journal of Solid-State-Circuits, pp. 208-215, Feb. 1988.
[5]
T.H. Chen, L.G. Chen, Y.S. Chang, "Design of Concurrent Error-Detectable VLSI-Based Array Dividers," Proceedings of IEEE International Conference on Computer Design, pp. 72-75, Oct. 1992
[6]
D.A. Reynolds, G. Metze, "Fault Detection Capabilities of Alternating Logic," IEEE Transactions on Computers, Vol. C27, No. 12, pp. 1093-1098, Dec. 1978
[7]
T.H. Chen, Y.P. Lee, L.G. Chen, "Concurrent Error Detection in Array Multipliers by BIDO," Proceedings of IEE Computers and Digital Techniques. Vol. 142, No.6, pp. 425 - 430, Nov. 1995.
[8]
B.W. Johnson, "Design and Analysis of Fault-Tolerant Digital Systems," Addison-Wesley, 1989.
[9]
E. Swartzlander, Y.M. Hsu, "Efficient Time Redundancy for Error Correcting Inner-Product Units and Convolvers," Proceedings of IEEE International workshop on defect and fault tolerance in VLSI systems, pp. 198-206, Nov. 1995.
[10]
W.L. Gallagher, E.E. Swartzlander, "Fault Tolerant Newton-Raphson Dividers using Time Shared TMR," Proceedings of IEEE International Symposium on defect and fault tolerance in VLSI systems, pp. 240 - 248, Nov. 1996.
[11]
W.L. Gallagher, E.E. Swartzlander, "Error-Correcting Goldschmidt Dividers Using Time Shared TMR," Proceedings of IEEE International Symposium on defect and fault tolerance in VLSI systems, pp. 224 - 232, Nov. 1998.
[12]
S. Mitra, E.J. McCluskey, "Combinational Logic Synthesis for Diversity in Duplex System", Proceedings of IEEE International Test Conference, pp. 179-188, Oct. 2000.
[13]
S. Mitra, E.J. McCluskey, "Which Concurrent Error Detection Scheme to Choose", Proceedings of IEEE International Test Conference, pp. 985-994, Oct. 2000.
[14]
R. Karri, A. Orailoglu, "Scheduling with Rollback Constraints in High-level Synthesis of Self-Recovering ASICs," Proceedings of Fault Tolerant Computing, pp. 519-526, Jul. 1992
[15]
S.S. Ravi, R. Narasimhan, D.J. Rosekrantz, "Efficient Algorithms for Analyzing and Synthesizing Fault-Tolerant Datapaths," Proceedings of IEEE International workshop on defect and fault tolerance in VLSI systems, pp. 81 - 89, Nov. 1995.
[16]
R. Karri, B. Iyer, "Introspection: A register Transfer Level Technique for Concurrent Error Detection and Diagnosis," ACM Transactions on Design Automation of Electronic Systems, vol. 7, no. 1, Jan. 2002.
[17]
R. Karri, A. Orailoglu, "Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors," IEEE Transactions on Reliability, pp. 404 - 412, Sep. 1996.
[18]
G. Lakshminarayana, A. Raghunathan, N.K. Jha, "Behavioral Synthesis of Fault Secure Controller/Datapaths using Aliasing Probability Analysis," Proceedings of Fault Tolerant Computing, pp. 336 - 345, Jun. 1996.
[19]
L.M. Guerra, M.M. Potkonjak, J.M. Rabaey, "High level synthesis techniques for efficient built-in-self-repair," Proceedings of IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 41 -48, 1993.
[20]
http://www.synopsys.com/

Recommendations

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences
ICCAD '01: Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
November 2001
656 pages
ISBN:0780372492
  • Conference Chair:
  • Rolf Ernst

Sponsors

Publisher

IEEE Press

Publication History

Published: 04 November 2001

Check for updates

Qualifiers

  • Article

Conference

ICCAD01
Sponsor:
ICCAD01: International Conference on Computer Aided Design
November 4 - 8, 2001
California, San Jose

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

  • 0
    Total Citations
  • 179
    Total Downloads
  • Downloads (Last 12 months)0
  • Downloads (Last 6 weeks)0
Reflects downloads up to 09 Nov 2024

Other Metrics

Citations

View Options

Get Access

Login options

View options

PDF

View or Download as a PDF file.

PDF

eReader

View online with eReader.

eReader

Media

Figures

Other

Tables

Share

Share

Share this Publication link

Share on social media