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WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?

Published: 03 October 2000 Publication History

Abstract

Concurrent error detection (CED) techniques (based onhardware duplication, parity codes, etc.) are widely used toenhance system dependability. All CED techniquesintroduce some form of redundancy. Redundant systems aresubject to common-mode failures (CMFs). While most ofthe studies of CED techniques focus on area overhead, fewanalyze the CMF vulnerability of these techniques. In thispaper, for the first time, we present simulation results toquantitatively compare various CED schemes based ontheir area overhead and the protection (data integrity) theyprovide against multiple failures and CMFs. Our resultsindicate that, for the simulated combinational logiccircuits, although diverse duplex systems (with twodifferent implementations of the same logic function)sometimes have marginally higher area overhead, theyprovide significant protection against multiple failures andCMFs compared to other CED techniques like parityprediction.

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cover image Guide Proceedings
ITC '00: Proceedings of the 2000 IEEE International Test Conference
October 2000
ISBN:0780365461

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IEEE Computer Society

United States

Publication History

Published: 03 October 2000

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  • (2018)Tolerating Soft Errors in Processor Cores Using CLEAR (Cross-Layer Exploration for Architecting Resilience)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2017.275270537:9(1839-1852)Online publication date: 1-Sep-2018
  • (2017)Conditions for detecting a logical element fault in a combination device under concurrent checking based on Berger's codeAutomation and Remote Control10.1134/S000511791705011378:5(891-901)Online publication date: 1-May-2017
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