Article

Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design

Authors:

Ashish Srivastava,

Dennis Sylvester,

David BlaauwAuthors Info & Claims

DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 1

Page 10718

Published: 16 February 2004 Publication History

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Abstract

We present a sensitivity based algorithm for total power including dynamic and subthreshold leakage power minimization using simultaneous sizing, Vdd and Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. Acomparison with traditional CVS based algorithms demonstrates the advantage of the algorithm including an average power reduction of 37% at primary input activities of 0.1. We also investigate the impact of various low Vdd values on total power savings.

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Cited By

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Tie MDong HWang TCheng XDe Micheli GAl-Hashimi BMueller WMacii E(2010)Dual-Vth leakage reduction with fast clock skew scheduling enhancementProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871049(520-525)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871049
Wang HMiranda MDehaene WCatthoor F(2009)Design and synthesis of Pareto buffers offering large range runtime energy/delay tradeoffs via combined buffer size and supply voltage tuningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200316917:1(117-127)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2003169
Wu TXie LDavoodi ANarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizingProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393937(45-50)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1393937
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Index Terms

Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization
  2. Integrated circuits
    1. Logic circuits
      1. Combinational circuits

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DATE '04: Proceedings of the conference on Design, automation and test in Europe - Volume 1

February 2004

688 pages

ISBN:0769520855

Publisher

IEEE Computer Society

United States

Publication History

Published: 16 February 2004

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DATE04: Design, Automation and Test in Europe 2004

February 16 - 20, 2004

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Tie MDong HWang TCheng XDe Micheli GAl-Hashimi BMueller WMacii E(2010)Dual-Vth leakage reduction with fast clock skew scheduling enhancementProceedings of the Conference on Design, Automation and Test in Europe10.5555/1870926.1871049(520-525)Online publication date: 8-Mar-2010
https://dl.acm.org/doi/10.5555/1870926.1871049
Wang HMiranda MDehaene WCatthoor F(2009)Design and synthesis of Pareto buffers offering large range runtime energy/delay tradeoffs via combined buffer size and supply voltage tuningIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200316917:1(117-127)Online publication date: 1-Jan-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2003169
Wu TXie LDavoodi ANarayanan VRavikumar CHenkel JKeshavarzi AOklobdzija VPangrle B(2008)A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizingProceedings of the 2008 international symposium on Low Power Electronics & Design10.1145/1393921.1393937(45-50)Online publication date: 11-Aug-2008
https://dl.acm.org/doi/10.1145/1393921.1393937
Papanikolaou AGrabner TMiranda MRoussel PCatthoor FBergamaschi RChoi K(2006)Yield prediction for architecture exploration in nanometer technology nodes:Proceedings of the 4th international conference on Hardware/software codesign and system synthesis10.1145/1176254.1176315(253-258)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176254.1176315
Cho MAhmedtt SPan D(2005)TACOProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129683(582-587)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129683
Chou HWang YChen CTang T(2005)Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian RelaxationProceedings of the 2005 Asia and South Pacific Design Automation Conference10.1145/1120725.1120881(381-386)Online publication date: 18-Jan-2005
https://dl.acm.org/doi/10.1145/1120725.1120881
Chinnery DKeutzer KRoy KTiwari V(2005)Linear programming for sizing, Vth and Vdd assignmentProceedings of the 2005 international symposium on Low power electronics and design10.1145/1077603.1077642(149-154)Online publication date: 8-Aug-2005
https://dl.acm.org/doi/10.1145/1077603.1077642
Gao FHayes JJoyner WMartin GKahng A(2005)Total power reduction in CMOS circuits via gate sizing and multiple threshold voltagesProceedings of the 42nd annual Design Automation Conference10.1145/1065579.1065593(31-36)Online publication date: 13-Jun-2005
https://dl.acm.org/doi/10.1145/1065579.1065593
Hung WXie YVijaykrishnan NKandemir MIrwin MTsai YJoshi RChoi KTiwari VRoy K(2004)Total power optimization through simultaneously multiple-vDD multiple-vTH assignment and device sizing with stack forcingProceedings of the 2004 international symposium on Low power electronics and design10.1145/1013235.1013276(144-149)Online publication date: 9-Aug-2004
https://dl.acm.org/doi/10.1145/1013235.1013276

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Recommendations

Switching-activity driven gate sizing and Vth assignment for low power design

Power-optimal repeater insertion considering Vdd and Vth as design freedoms

Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment

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