Test Compression and Hardware Decompression for Scan-Based SoCs

We present a data compression method and decompression architecture for testing embedded cores in a system-on-a-chip (SOC). The proposed approach makes effective use of Golomb coding and the internal scan chain(s) of the core under test and provides ...

JPEG is an international standard for still-image compression/decompression and has been widely implemented in hardware. In this paper, we describe the development of a JPEG chip which employs a single-chip implementation and an efficient architecture ...

In this paper we present a new test data compression technique and an associated decompression scheme for testing VLSI chips. Our method is based on our novel use of the much utilized in software LZW, particularly LZ77 algorithm. We adapt LZ77 to ...