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The effect of real data cache behavior on the performance of a microarchitecture that supports dynamic scheduling

Authors:

Michael Butler,

Yale PattAuthors Info & Claims

MICRO 24: Proceedings of the 24th annual international symposium on Microarchitecture

Pages 34 - 41

https://doi.org/10.1145/123465.123472

Published: 01 September 1991 Publication History

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Cited By

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Bennett JFlynn MSmotherman MConte T(1997)Prediction caches for superscalar processorsProceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture10.5555/266800.266809(81-90)Online publication date: 1-Dec-1997
https://dl.acm.org/doi/10.5555/266800.266809
Bennett JFlynn M(1997)Prediction caches for superscalar processorsProceedings of 30th Annual International Symposium on Microarchitecture10.1109/MICRO.1997.645800(81-90)Online publication date: 1997
https://doi.org/10.1109/MICRO.1997.645800
Fernandes EVasconcelos N(1994)A study of associative dispatch in superscalar processorsProceedings of Twentieth Euromicro Conference. System Architecture and Integration10.1109/EURMIC.1994.390374(346-352)Online publication date: 1994
https://doi.org/10.1109/EURMIC.1994.390374

Index Terms

The effect of real data cache behavior on the performance of a microarchitecture that supports dynamic scheduling
1. General and reference
  1. Cross-computing tools and techniques
    1. Performance
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
  2. Software organization and properties
    1. Contextual software domains
      1. Operating systems
        Process management
        Scheduling

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Capturing dynamic memory reference behavior with adaptive cache topology

Memory references exhibit locality and are therefore not uniformly distributed across the sets of a cache. This skew reduces the effectiveness of a cache because it results in the caching of a considerable number of less-recently-used lines which are ...
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Memory references exhibit locality and are therefore not uniformly distributed across the sets of a cache. This skew reduces the effectiveness of a cache because it results in the caching of a considerable number of less-recently-used lines which are ...

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MICRO 24: Proceedings of the 24th annual international symposium on Microarchitecture

September 1991

223 pages

ISBN:0897914600

DOI:10.1145/123465

Chairman:
Yashwant K. Malaiya

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 01 September 1991

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Bennett JFlynn MSmotherman MConte T(1997)Prediction caches for superscalar processorsProceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture10.5555/266800.266809(81-90)Online publication date: 1-Dec-1997
https://dl.acm.org/doi/10.5555/266800.266809
Bennett JFlynn M(1997)Prediction caches for superscalar processorsProceedings of 30th Annual International Symposium on Microarchitecture10.1109/MICRO.1997.645800(81-90)Online publication date: 1997
https://doi.org/10.1109/MICRO.1997.645800
Fernandes EVasconcelos N(1994)A study of associative dispatch in superscalar processorsProceedings of Twentieth Euromicro Conference. System Architecture and Integration10.1109/EURMIC.1994.390374(346-352)Online publication date: 1994
https://doi.org/10.1109/EURMIC.1994.390374

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Increasing hardware data prefetching performance using the second-level cache

Capturing dynamic memory reference behavior with adaptive cache topology

Capturing dynamic memory reference behavior with adaptive cache topology

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Increasing hardware data prefetching performance using the second-level cache

Capturing dynamic memory reference behavior with adaptive cache topology

Capturing dynamic memory reference behavior with adaptive cache topology

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