research-article

Thermal-aware memory mapping in 3D designs

Authors:

Ang-Chih Hsieh,

Tingting HwangAuthors Info & Claims

ACM Transactions on Embedded Computing Systems (TECS), Volume 13, Issue 1

Article No.: 4, Pages 1 - 22

https://doi.org/10.1145/2512457

Published: 05 September 2013 Publication History

Abstract

DRAM is usually used as main memory for program execution. The thermal behavior of a memory block in a 3D SIP is affected not only by the power behavior but also the heat dissipating ability of that block. The power behavior of a block is related to the applications run on the system, while the heat dissipating ability is determined by the number of tier and the position the block locates. Therefore, a thermal-aware memory allocator should consider the following two points. First, the allocator should consider not only the power behavior of a logic block but also the physical location during memory mapping and second, the changing temperature of a physical block during execution of programs. In this article, we will propose a memory mapping algorithm taking into consideration these two points. Our technique can be classified as static thermal management to be applied to embedded software designs. Experiments show that for single-core systems, our method can reduce the temperature of memory system by 17.1°C, as compared to a straightforward mapping in the best case, and 13.3°C on average. For systems with four cores, the temperature reductions are 9.9°C and 11.6°C on average when L1 cache of each core is set to 4KB and 8KB, respectively.

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Cited By

Pandey SPanda P(2024)NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN PerformanceACM Transactions on Embedded Computing Systems10.1145/367717823:6(1-30)Online publication date: 11-Sep-2024
https://dl.acm.org/doi/10.1145/3677178
Pandey SSethi SPanda P(2024)3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.336723543:8(2263-2276)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3367235
Shen YSchreuders LPathania APimentel A(2023)Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power RegulationACM Transactions on Embedded Computing Systems10.1145/360804022:5s(1-26)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3608040
Show More Cited By

Index Terms

Thermal-aware memory mapping in 3D designs
1. Hardware

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Published In

cover image ACM Transactions on Embedded Computing Systems

ACM Transactions on Embedded Computing Systems Volume 13, Issue 1

August 2013

332 pages

ISSN:1539-9087

EISSN:1558-3465

DOI:10.1145/2501626

Issue’s Table of Contents

Copyright © 2013 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 05 September 2013

Accepted: 01 December 2011

Revised: 01 September 2011

Received: 01 February 2010

Published in TECS Volume 13, Issue 1

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Cited By

Pandey SPanda P(2024)NeuroTAP: Thermal and Memory Access Pattern-Aware Data Mapping on 3D DRAM for Maximizing DNN PerformanceACM Transactions on Embedded Computing Systems10.1145/367717823:6(1-30)Online publication date: 11-Sep-2024
https://dl.acm.org/doi/10.1145/3677178
Pandey SSethi SPanda P(2024)3D-TemPo: Optimizing 3-D DRAM Performance Under Temperature and Power ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2024.336723543:8(2263-2276)Online publication date: 1-Aug-2024
https://dl.acm.org/doi/10.1109/TCAD.2024.3367235
Shen YSchreuders LPathania APimentel A(2023)Thermal Management for 3D-Stacked Systems via Unified Core-Memory Power RegulationACM Transactions on Embedded Computing Systems10.1145/360804022:5s(1-26)Online publication date: 31-Oct-2023
https://dl.acm.org/doi/10.1145/3608040
Pandey SPanda P(2022)NeuroMap: Efficient Task Mapping of Deep Neural Networks for Dynamic Thermal Management in High-Bandwidth MemoryIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.319769841:11(3602-3613)Online publication date: 1-Nov-2022
https://dl.acm.org/doi/10.1109/TCAD.2022.3197698
Liu CWu CChen YHung CSaid L(2018)Thermal-aware task and data co-allocation for multi-processor system-on-chips with 3D-stacked memoriesProceedings of the 2018 Conference on Research in Adaptive and Convergent Systems10.1145/3264746.3264771(243-248)Online publication date: 9-Oct-2018
https://dl.acm.org/doi/10.1145/3264746.3264771
Lo WLiang KHwang TFanucci LTeich J(2016)Thermal-aware dynamic page allocation policy by future access patterns for hybrid memory cube (HMC)Proceedings of the 2016 Conference on Design, Automation & Test in Europe10.5555/2971808.2972061(1084-1089)Online publication date: 14-Mar-2016
https://dl.acm.org/doi/10.5555/2971808.2972061
Tsai MChen YChen YChang RFettweis GNebel W(2014)Scenario-aware data placement and memory area allocation for multi-processor system-on-chips with reconfigurable 3D-stacked SRAMsProceedings of the conference on Design, Automation & Test in Europe10.5555/2616606.2617069(1-6)Online publication date: 24-Mar-2014
https://dl.acm.org/doi/10.5555/2616606.2617069

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