GameBoy Programming Manual

PROGRAMMING MANUAL
Version 1.0
DMG-06-4216-001-A
Released 11/09/1999
“Confidential”
This document contains confidential and proprietary information of

Nintendo and is also protected under the copyright laws of the United
States and foreign countries. No part of this document may be released,
distributed, transmitted or reproduced in any form or by any electronic
or mechanical means, including information storage and retrieval
systems, without permission in writing from Nintendo.
 1999 Nintendo of America Inc.
TM and  are trademarks of Nintendo

Introduction
INTRODUCTION
This manual is a combination and reorganization of the information presented in the Game Boy Development
Manual, revision G, and the Game Boy Color User's Guide, version 1.3. In addition, it incorporates all information
related to Game Boy programming, including programming for Super Game Boy and the Game Boy Pocket
Printer.
The abbreviations used in this manual represent the following:

DMG: Game Boy (monochrome), introduced on April 21, 1989
MGB: Game Boy Pocket (monochrome), introduced on July 21, 1996
MGL: Game Boy Light (monochrome), introduced on April 14, 1998
CGB: Game Boy Color (color), introduced on October 21, 1998
Note: Where it is not necessary to distinguish between the different monochrome

models, DMG is used to refer to both monochrome models, and CGB is used to
denote the color Game Boy. Only where it is necessary to distinguish between
the monochrome models is MGB used to denote Game Boy and MGL used to
denote Game Boy Light.
SGB: Super Game Boy, introduced on June 14, 1994

SGB2: Super Game Boy 2, introduced on January 30, 1998
Note: SGB is used to denote both SGB and SGB2 when no distinction is necessary.
SGB2 is used only in cases where distinction is necessary.
3
Game Boy Programming Manual
THIS PAGE WAS INTENTIONALLY LEFT BLANK.
4
Preface: To Publishers
PREFACE: TO PUBLISHERS
NINTENDO GAME BOY COLOR SOFTWARE PRE-APPROVAL

REQUIREMENTS
Prior to submitting your CGB software to Lot Check for approval, it is required that you submit it to the
Licensee Product Support Group for pre-approval. To assist us with the evaluation of your CGB software
and/or product proposal(s), please refer to the following requirements when submitting materials* for approval.
* Please do not send original artwork or materials, as they will not be returned.
CGB software and/or product proposals are evaluated based on the following criteria:
• Use of Color
To ensure that the expectations of the Game Boy Color consumer are met, Mario Club will evaluate the
use of color in all CGB games (dual or dedicated) using the following criteria:
◊ Differentiation - If a game is to be considered CGB-compatible, then it must appear significantly

more colorful than a monochrome Game Boy game when “colorized” by the CGB hardware. The
principal measure of this is the number of colors in the background (BG) and the number of colors in
the objects (OBJ).
◊ Simultaneous Colors - Because CGB hardware automatically “colorizes” monochrome games with
up to four colors in the BG palette and up to six colors for two OBJ palettes (three colors per palette),
a game typically must display more colors than this automatic “colorization” to be considered a CGB
game.
◊ Appropriate use of Color - Objects in the game that are based on reality (trees, rocks, animals, and
so on) should be a color that we would normally associate with them. For fictional objects, colors
should be chosen to show appropriate detail and, when needed, to differentiate unlike objects.
◊ Variety of Colors - The CGB is capable of producing a wide range of colors (32,768 to be exact --
albeit not all at the same time). A CGB game should use this capability of the hardware to yield
distinctly different colors for objects, characters, areas, and so on.
◊ Contrast & Saturation - Two of the elements that make a game look colorful are high contrast and
“saturated” or vibrant colors. Pastel colors on a white background will not seem nearly as colorful as
the same colors on a dark background. Not every game can use a dark background, but the intensity
of the colors should still be maximized as much as possible.
Please detail or demonstrate how your game will utilize color capabilities of the CGB. Use whatever
means will best allow you to do so, such as artists renderings, programmed demos, ROM images, written
descriptions, and so on.
5
• Game Concept content

We do not require an explanation of, or evaluate game concept content for original CGB titles. However, if
you are planning to “colorize” a previously released monochrome game we require that it include game-
play enhancements (beyond simply adding color) to differentiate it from its monochrome counterpart.
Such game-play enhancements may include, but are not limited to: additional stages, levels, or areas; new
characters; additional items; game-play based on color; and so on. These enhancements must be readily
apparent to players familiar with the original monochrome game.
Please submit a written proposal of the enhancements to us for pre-approval. Use whatever additional
means that will best allow you to communicate the game-play enhancements, such as storyboards,
treatments, videotapes, programmed demos, and so on.
• Interim ROM Submissions

We require at least one interim ROM submission to Mario Club (at approximately 50% completion) for
preliminary review of the use of color in every CGB game. By reviewing the interim ROM and providing
you with feedback in the early stages, we also help ensure that your projects stay on schedule. Final pre-
approval is based on Mario Club’s evaluation of a ROM near completion of game development.
If you wish to arrange electronic transfer of the ROM image, please contact Sharon Pfeifle in our Testing
and Engineering department at (425) 861-2768 or by e-mail at “sharpf01@noa.nintendo.com”. Please
notify me when you have made an electronic submission for our review.
• Proposed Developer
Please supply us with the name, address and phone number of the proposed developer. If the developer
is not an Authorized Nintendo CGB Developer, please contact Lief Thompson at
“liefth@noa.nintendo.com” or 425-861-2823, and he will provide you with the application information.
• Schedule Information
Please provide us with an estimated product schedule, including interim ROM submission(s), final Mario
Club submission, submission of the master ROM to Lot Check, and the release date.
• Game Pak Configuration & Game Type

Please provide us with the estimated Game Pak size in Megabits (Mb) and the RAM size if internal
memory is to be used to save game information. Also state whether the game will be compatible with the
monochrome Game Boy hardware or if it is dedicated to CGB hardware. For the current Game Pak prices
and configurations available, please contact Nintendo’s Licensing Department.
You will be contacted with the evaluation results when the Licensee Product Support Group has completed its
evaluation of your ROM or concept submission.
6
Table of Contents
Table of Contents
Page Number
Introduction............................................................................................... 3
Preface: To Publishers ....................................................................... 5
Chapter 1 System ................................................................................10
Chapter 2 Display Functions............................................................. 46
Chapter 3 Sound Functions .............................................................. 70
Chapter 4 CPU Instruction Set.......................................................... 84
Chapter 5 Miscellaneous General Information ............................. 114
Chapter 6 The Super Game Boy System ....................................... 124
Chapter 7 Super Game Boy Sound ................................................ 182
Chapter 8 Game Boy Memory Controllers(MBC).......................... 212
Chapter 9 Pocket Printer ................................................................. 233
Appendix 1 Programming Cautions .................................................. 248
Appendix 2 Register and Instruction Set Summaries ..................... 260
Appendix 3 Software Submission Requirements............................ 276
7
8
Chapter 1: System
CHAPTER 1: SYSTEM ............................................................ 10

1. General System .............................................................................. 10
1.1 System Overview ..................................................................................... 10
1.2 Game Boy Block Diagram ....................................................................... 12
1.3 Memory Configuration............................................................................. 13
1.4 Memory Map ............................................................................................. 14
1.5 Feature Comparison ................................................................................ 15
1.6 Register Comparison............................................................................... 16
2. CPU .................................................................................................. 17
2.1 Overview of CPU Features ...................................................................... 17
2.2 CPU Block Diagram ................................................................................. 19
2.3 Description of CPU Functions ................................................................ 21
À )............................................. 23
2.4 CPU Functions (Common to DMG/CGBÀ
Á )............................................. 28
2.5 CPU Functions (Common to DMG/CBGÁ
2.6 CPU Functions (CGB only)...................................................................... 34
9
CHAPTER 1: SYSTEM
1. GENERAL SYSTEM INFORMATION
1.1 System Overview
Structure
At the heart of the DMG/CGB system is a CPU with a built-in LCD controller designed for
DMG/CGB use.
System
[DMG] [CGB]
Ø Dot-matrix LCD unit capable of Ø Color dot-matrix LCD unit capable of
grayscale display RGB with 32 grayscale shades
Ø 64 Kbit – SRAM (for LCD display) Ø 128 Kbit – SRAM (for LCD display)
Ø 64 Kbit – SRAM (working memory) Ø 256 Kbit – SRAM (working memory)
Ø Infrared communication link (photo
transistor, photo LED)
Features common to DMG/CGB

Ø 32-pin connector (for ROM cartridge connection)
Ø 6-pin subconnector (for external serial communication)
Ø DC-DC converter for power source
Ø Sound amp
Ø Keys for operation
Ø Speaker
Ø Stereo headphone connector
Ø Input connector for external power source
Types of Game Pak Supported

1 Game Boy Game Pak
(Software that uses only the Game Boy functions. When used with Game Boy Color, 4-
10 colors are displayed.)
2 Game Boy Color Game Pak
Ø Game Pak supported by CGB (for use with both CGB and DMG)
Ø Game Pak for CGB only (software that runs only on CGB)
Operating Modes (the following modes apply only to CGB)

1 DMG Mode (when using software for DMG)
The new registers, expanded memory area, and new features for CGB are not used.
Color applications previously associated with palette data BGP, OBP0, and OBP1 are
performed by the system.
10
Chapter 1: System
2 CGB Mode (when using software supported or used exclusively by CGB )

The new registers, expanded memory area, and new features of CGB are available.
Note To operate in CGB mode, specific code must first be placed in the ROM
data area of the user program. For more information, see Chapter 5,
Section 2, Recognition of CGB support (CGB only) in ROM Data.
Power Source
Ø Battery/AC adapter/Battery charger
Accessories (as of April 1999)

DMG Accessories
Ø Communication Cable
Ø Battery Charger Adapter
MGB/CGB Accessories
Ø Communication Cable
Ø AC Adapter
Ø Battery Pack Charger Set
The 6-pin serial communication subconnector and the AC adapter input connector of the DMG hardware
that preceded MGB are shaped differently than those of MGB and CGB. Thus, two types of accessories
are available — those exclusively for DMG and those exclusively for MGB/CGB. In addition, a
conversion connector is necessary for communication between DMG and MGB/CGB.
11
1.2 GAME BOY BLOCK DIAGRAM

External Power Source
Battery Terminal
LCD Panel
Power Switch
DC-DC Power to
LCD Driver Converter System
Headphone
Terminal Volume
Amp
Speaker
Display RAM
DMG: 64 Kbit
CGB: 128 Kbit
8-bit
Infrared Microprocessor
Communication
(CGB only)
Work RAM
DMG: 64 Kbit
6-pin CGB: 256 Kbit
Subconnector
Operating
Keys Game Boy
Hardware Unit
Mask ROM
Program
SRAM
(Backup)
Game Pak
12
Chapter 1: System
1.3 MEMORY CONFIGURATION

In DMG and CGB, the 32 KB from 0x0 to 0x7FFF is available as program area.
0x000-0x0FF: Allocated as the destination address for RST instructions and the starting address for
interrupts.
0x100-0x14F: Allocated as the ROM area for storing data such as the name of the game.
0x150: Allocated as the starting address of the user program.
The 8 KB from 0x8000 to 0x9FFF is used as RAM for the LCD display. In CGB, the amount of RAM
allocated for this purpose is 16 KB (8 KB x 2), twice the amount allocated for the LCD display in DMG,
and this RAM can be used in 8 KB units using bank switching. The 8 KB RAM areas are divided into the
following 2 areas.
1 An area for character data
2 An area for BG (background) display data (Character code and attribute)
The 8 KB from 0xA000 to 0xBFFF is the area allocated for external expansion RAM.
The 8 KB from 0xC000 to 0xDFFF is the work RAM area.
In DMG, the 8 KB of working RAM is implemented without change. In CGB, bank switching is used to
provide 32 KB of working RAM. This 32 KB area is divided into 8 areas of 4 KB each.
1 The 4 KB from 0xC000 to 0xCFFF is fixed as Bank 0.
2 The 4 KB from 0xD000 to 0xDFFF can be switched between banks 1 though 7.
Note Use of the area from 0xE000 to 0xFDFF is prohibited.
0xFE00 to 0xFFFF is allocated for CPU internal RAM.
0xFE00-0xFE9F: OAM-RAM (Holds display data for 40 objects)

0xFF00-0xFF7F & 0xFFFF: Specified for purposes such as instruction registers and system controller
flags.
0xFF80-0xFFFE: Can be used as CPU work RAM and/or stack RAM.
13
1.4 MEMORY MAP

Note In DMG, there is no bank switching at 0x8000-0x9FFF and 0xC000-
0xDFFF.
0x000
Interrupt Address
RST Address
0x100
ROM Data
Area
0x150 Program Start Address
User Program Area

32 KB 0x8000 Lower Dot Data
0x8001 Upper Dot Data
0x8000
Bank 1
Bank 0
Character Data
Character Data
(CGB only)
0x9800
BG Display Data 1 (CGB only)
Character Codes Attributes
0x9C00
BG Display Data 2 (CGB only)
Character Codes Attributes
0xA000
External Expansion
Working RAM
8 KB
(CGB Only)
0xC000
(DMG)
Bank 0 (Fixed)
Unit Working RAM
0xD000
8 KB
Banks 1-7 (Switchable)
0xE000
Use of area 0xE000 - 0xFDFF prohibited
0xFE00
OAM (40 OBJs) 7 6 5 4 3 2 1 0 0xFE00
(40 x 32 bits) (OBJ 0)
0xFEA0 Y0
X0
0xFF00
Port/Mode Registers Character Code
Control Register Color Palette (CGB)
Sound Register Character Bank (CGB)
Palette (DMG)
0xFF80 Left/Right
Up/Down
Working & Stack RAM Priority
127 bytes Y39
0xFFFE X39
0xFFFF Character Code
0xFE9F
(OBJ 39)
14
Chapter 1: System
1.5 FEATURE COMPARISON

Item DMG CPU CGB CPU
CPU Speed 1.05 MHz 1.05 MHz (normal mode)
(system operating frequency) 2.10 MHz (double-speed mode)
Game Boy RAM
Work and Stack RAM 127 x 8 bits ←
Work RAM 8,192 bytes 32,768 bytes
OAM 40 x 28 bits 40 x 32 bits
For LCD display 8,192 bytes 16,384 bytes
Game Pak Memory Space
ROM (without MBC) 32,768 bytes ←
RAM (without MBC) 8,192 bytes ←
LCD Controller
Display Capacity 160 x 144 dots 160 x 144 x RGB dots
Block Structure
BG, window 8 x 8 dots ←
Object 8 x 8 dots or 8 x 16 dots ←
Number of Usable Characters
BG 256 512
OBJ 8 x 8 256 512
8 x 16 128 256
Grayscale: BG, window 4 shades, 1 palette 4 colors, 8 palettes
( DMG mode: 4 colors, 1 palette)
Grayscale: Object 3 shades, 2 palettes 3 colors, 8 palettes
(DMG mode: 3 colors, 2 palettes)
Object priority
Different x coordinates Object with smallest x coord . Object with lowest OBJ number
(DMG mode: Object with lowest x
coord.)
Same x coordinates Object with lowest OBJ number ←
Timer & Divider Stages 8-bit timer x 1 ←
16 stages x 1 ←
Serial Input/Output 8 bits x 1 ←
Baud Rate 8K 8K/256K (16K/512K in high-speed mode
DMA Controller
Existing DMA 0x8000~0xDFFF→OAM 0x0~0xDFFF→OAM
Horizontal blank DMA --- Game Pak & Work RAM→VRAM
General-purpose DMA --- Game Pak & Work RAM→VRAM
Interrupt features
Internal Interrupts 4 types (maskable) ←
External Interrupts 1 type (maskable) ←
Input/Output Ports
Serial Input/Output Ports SIN, SCK, SOUT ←
Infrared Communication Port --- R0, R1, R2, R3
Sound Output Circuit 4 sounds ←
Monaural (VIN) External Sound
Mixable Input
←: Same as in column at left
15
1.6 REGISTER COMPARISON

DMG CPU CGB CPU
Use Register Address Register Address
Port/Mode P1 FF00 ← ←
Registers SB FF01 ← ←
SC FF02 ← ←
DIV FF04 ← ←
TIMA FF05 ← ←
TMA FF06 ← ←
TAC FF07 ← ←
--- KEY1 FF4D
--- RP FF56
Bank Control --- VBK FF4F
Registers --- SVBK FF70
Interrupt IF FF0F ← ←
Flags IE FFFF ← ←
IME ←
LCD Display LCDC FF40 ← ←
Registers STAT FF41 ← ←
SCY FF42 ← ←
SCX FF43 ← ←
LY FF44 ← ←
LYC FF45 ← ←
DMA FF46 ← ←
BGP FF47 ← ←
OBP0 FF48 ← ←
OBP1 FF49 ← ←
WY FF4A ← ←
WX FF4B ← ←
--- HDMA1 FF51
--- HDMA2 FF52
--- HDMA3 FF53
--- HDMA4 FF54
--- HDMA5 FF55
--- BCPS FF68
--- BCPD FF69
--- OCPS FF6A
--- OCPD FF6B
OAM FE00~FE9F ← ←
Sound Registers NR x x FF10~FF26 ← ←
Waveform RAM FF30~FF3F ← ←
←: Same as in column at left
16
Chapter 1: System
2. CPU
2.1 OVERVIEW OF CPU FEATURES
The CPUs of DMG and CGB are ICs customized for DMG/CGB use, and have the following features.
CPU Features
Central to the 8-bit CPU are the following features, including an I/O port and timer.
Ø 127 x 8 bits of built-in RAM (working and stack)
Ø RAM for LCD Display: <DMG> 8 KB/<CGB>16 KB ( )
Ø Working RAM: <DMG> 8KB/<CGB> 32 KB
Ø Built-in 16-stage Frequency Divider
Ø Built-in 8-bit Timer
Ø 4 types of Internal Interrupts (maskable)
Ø 1 type of External Interrupt (maskable)
Ø Built-in DMA Controller
Ø Input Ports P10 ~ P13
Ø Output Ports P14 and P15
Ø Serial I/O Ports SIN, SCK, SOUT
Ø Infrared I/O Port <CGB only>
LCD Controller Functions

Game Boy is equipped with functions that provide control of the images displayed
on the LCD. Character data used for display is held in system RAM.
Ø DMG: 4 shades of gray; CGB: 32 shades of gray for each RGB color
Ø 160 x 144-dot liquid crystal display
Ø 8 x 8-dot composition of background and window characters
Ø 8 x 8 or 8 x 16-dot composition of OBJ characters
Ø Up to 40 objects displayable in 1 screen
Ø Up to 10 objects displayable on 1 horizontal line
Ø 40 x 32 bits of built-in RAM (OBJ-RAM for LCD)
Ø Control of 256 x 256-dot background
Ø Vertically and horizontally scrollable background
Ø Window-like functions
Sound Functions
Each system is equipped with 4 types of sound synthesis circuitry.
Ø Sound 1: Quadrangular waveform, sweep and envelope functions
Ø Sound 2: Quadrangular waveform, envelope functions
Ø Sound 3: Arbitrary waveform, generated
Ø Sound 4: White noise, generated
Ø 2 output channels (output can be allocated to a channel)
Ø Synthesized output with external sound input <CGB only>
17
Miscellaneous
Ø An internal monitor program is built into DMG/CGB CPUs. When power is
turned on or the Game Boy is reset, the internal monitor program first
initializes components such as the ports, then passes control to the user
program.
Ø Instruction cycles
<DMG> 0.954 µs (source oscillation: 4.1943 MHz)
<CGB> 0.954 µs/0.477 µs, switchable (source oscillation: 8.3886 MHz)
18
Chapter 1: System
2.2 CPU BLOCK DIAGRAM

Game Boy (DMG/MGB) CPU
/RESET D0~D7 VDD GND TEST1,2
....
/RD DMA
Timing
Data Buffer Controller
/WR Control
/CS
CPU Core ROM

A0
P10
A1 PC P11
. RAM Port P12
127 bytes P1
. SP P13
.
. Address A F P14
Buffer P15
. Interrupt Controller
. B C
.
. D E VIN
.
A14 H L Sound 1
A15 NR10-NR14 SO1
Synthesizer
Circuit
•@•@•@•@•@•@•@•@•@ Sound 2
Ø Divider NR20-NR23
•@•@
DIV SO2
Sound 3
NR30-NR33
Timer
TIMA TMA TAC
Sound 4
NR40-NR42
OAM RAM Waveform Sound

CK1
CG RAM Control
40 x 28 bit
CK2 32 x 4 NR50-NR52
SIO LCD Controller S

SIN
FR
SCK SB LCDC STAT SCY SCX LY LYC WX WY CPL
SC OBP0 OBP1 BGP
LCD ST
SOUT
Drive CP
Signal CPG
Buffer
LD0
LD1
LCD Display RAM Interface
MD0~MD7 MA0~MA12 /MCS /MWR /MRD

19
Game Boy Color CPU

/RD/WR/CS MD0-MD7 D0-D7 /NMI P00-P03 P10-P13
....
/MRD Keyport
Timing
Data Buffer
/MWR Control
/CS1
RAM
Interrupt
127 bytes
Controller
CPU Core
A0-A15
ROM
PC 2 Kbytes
SP Sound 1
NR10-NR14
Address Buffer
Synthesizer Circuit
A F SO1
Sound 2
MA0-MA12 NR20-NR23 SO2
B C
Sound 3
NR30-NR33
RA0,RA1 D E VIN
Sound 4
H L NR40-NR42
Waveform Sound
PHI Divider RAM Control
32x4 NR50-NR52
DIV
CK1
C. G Timer
CK2 TIMA TMA TAC Palette RAM
LDR0-LDR5
LDG0-LDG5
SCK
LCD Drive Signal Buffer LDB0-LDB5
LCD Controller DCK
SI SIO OAM RAM
40x28 bit (DMA Controller) SPL
SO LP
PS
SPS
Infrared CLS
R0-R4 Comm Port/ MOD
LCD Display RAM Interface REVC
General
Purpose
Port
VDD3 M1
VDD5
/RESET
GND
MD8-MD15 TEST0-TEST2 /MCS0,/MCS1 PSMO1 PSMO0
20
Chapter 1: System
2.3 DESCRIPTION OF CPU FUNCTIONS

Interrupts
There are five types of interrupts available, including 4 types of maskable internal interrupts and 1 type of
maskable external interrupt. The IE flag is used to control interrupts. The IF flag indicates which type of
interrupt is set.
Ø LCD Display Vertical Blanking
Ø Status Interrupts from LCDC (4 modes)
Ø Timer Overflow Interrupt
Ø Serial Transfer Completion Interrupt
Ø End of Input Signal for ports P10-P13
DMA Transfers
DMA transfers are controlled by the DMA registers.
<DMG>
DMG allows 40 x 32-bit DMA transfers from 0x8000-0xDFFF to OAM (0xFE00-0xFE9F). The transfer
start address can be specified in increments of 0x100 for 0x8000-0xDFFF.
<CGB>
In addition to the DMA transfers method for DMG (from 0x0000-0xDFFF in CGB), CGB enables two new
types of DMA transfer — horizontal blanking and general-purpose DMA transfers.
Note, however, that when performing a DMG-type DMA transfer on CGB, some consideration must be
given to specifying the destination RAM area.
For more information, see the DMA Functions section in Chapter 2.
1 Horizontal Blanking DMA Transfer

Sixteen bytes of data are automatically transferred for each horizontal blanking period
during a DMA transfer from the user program area (0x0000-0x7FFF) or external and
hardware working RAM area (0xA000-0xDFFF) to the LCD display RAM area
(0x8000-0x9FFF).
2 General-Purpose DMA Transfer
Between 16 and 2048 bytes of data (specified in 16-byte increments) are transferred
from the user program area (0x0000-0x7FFF) or external and hardware working RAM
area (0xA000-0xDFFF) to the LCD display RAM area (0x8000-0x9FFF), during the
Vertical Blanking Period.
Timer
The timer is composed of the following:
Ø TIMA (timer counter)
Ø TMA (timer modulo register)
Ø TAC (timer control register)
Controller Connections
Ø P10-P13: Input ports
Ø P14-P15: The key matrix structure is composed of the output ports.
21
At user program startup, the status of the CPU port registers and mode registers are as follows.
Register Status
P1 0
SC 0
TIMA 0
TAC 0
IE 0
LCDC $83 BG/OBJ ON, LCDC OPERATION
SCY 0
SCX 0
LYC 0
WY 0
W 0
Stack: 0xFFFE
Interrupt Enable (IE) DI
Standby Modes
The standby functions are HALT mode, which halts the system clock, and STOP mode, which halts
oscillation (source oscillation).
HALT Mode
Game Boy switches to HALT mode when a HALT instruction is executed.
The system clock and CPU operation halt in this mode. However, operation of source oscillation
circuitry between terminals CK1 and CK2 continues. Thus, the functions that do not require the
system clock (e.g,, DIV, SIO, timer, LCD controller, and sound circuit) continue to operate in this
mode.
HALT mode is canceled by the following events, which have the starting addresses indicated.
1) A LOW signal to the /RESET terminal
Starting address: 0x0000
2) The interrupt-enable flag and its corresponding interrupt request flag are set
IME = 0 (Interrupt Master Enable flag disabled)
Starting address: address following that of the HALT instruction
IME = 1 (Interrupt Master Enable flag enabled)
Starting address: each interrupt starting address
STOP Mode
Game Boy switches to STOP mode when a STOP instruction is executed.
The system clock and oscillation circuitry between the CK1 and CK2 terminals are halted in this
mode. Thus, all operation is halted except that of the SI0 external clock. STOP mode is canceled by
the following events, and started from the starting address.
3) A LOW signal to the /RESET terminal
Starting address: 0x0000
4) A LOW signal to terminal P10, P11, P12, or P13
Starting address: address following that of STOP instruction
When STOP mode is canceled, the system clock is restored after 217 times the oscillation clock
(DMG: 4 MHz, CGB: 4 MHz/8 MHz), and the CPU resumes operation.
When STOP mode is entered, the STOP instruction should be executed after all interrupt-enable
flags are reset, and meanwhile, terminals P10-P13 are all in a HIGH period.
22
Chapter 1: System
À)
2.4 CPU FUNCTIONS (COMMON TO DMG/CGBÀ
The CPU functions described here are those that are identical in DMG and CGB. CPU functions that are
enhanced in CGB are described in Section 2.5, CPU Functions (Common to DMG/CGBÁ). CPU
functions that cannot be used for DMG are described in Section 2.6, CPU Function (CGB only).
2.4.1 Controller Data
The P1 ports are connected with a matrix for reading key operations.
VDD P14 P15
Res. x4
RIGHT A
P10
LEFT B
P11
All inputs are
UP SELECT pulled High
P12
DOWN START
P13
23
When key input is read, a brief interval is interposed between P14 and P15 output
and reading of the input, as shown below.
Example: KEY LD A, $20 ; Read U, D, L, R keys
LD ($FF00), A ; Port P14 ← LOW output
LD A, ($FF00) ; Register A ← Port P10-P13
LD A, ($FF00) ; Perform this operation twice
.
.
LD A, ($10) ; Reads keys A, B, SE, ST
LD ($FF00), A ; Port P15 ← LOW output
LD A, ($FF00) ; Register A ← Ports P10-P13

LD A, ($FF00) ; Perform this operation 6 times
LD A, ($FF00) ;
. ;
. ;
LD A, $30 ; Port reset
LD ($FF00), A
.
RET
The interrupt request flag (IF: 4) is set by negative edge input at one of the
P13-P10 terminals. Negative edge input requires a LOW period of 24
times source oscillation (DMG = 4 MHz, CGB = 4 MHz/8 MHz).
The interrupt request flag (IF: 4) also is set when a reset signal is input to
the /RESET terminal with a P13~P10 terminal in the LOW state.
2.4.2 Divider Registers
The upper 8 bits of the 16-bit counter that counts the basic clock frequency (f) can be referenced. If an
LD instruction is executed, these bits are cleared to 0 regardless of the value being written. f =
(4.194304 MHz).
24
Chapter 1: System
2.4.3 Timer Registers
The main timer unit. Generates an interrupt when it overflows.
The value of TMA is loaded when TIMA overflows.
The timer consists of TIMA, TMA, and TAC.

The timer input clock is selected by TAC.
TIMA is the timer itself and operates using the clock selected by TAC.
TMA is the modulo register of TIMA. When TIMA overflows, the TMA data is loaded into TIMA.
Writing 1 to the 2nd bit of TAC starts the timer.
The timer should be started (the TAC start flag set) after the count up pulse is selected. Starting the
timer before or at the same time as the count up pulse is selected may result in excessive count up
operation.
Example
LD A, 3 ;Select a count pulse of f/28

LD (07), A ;TAC ← 3 set
LD A, 7 ;Start timer
LD (07), A ;
If a TMA write is executed with the same timing as that with which the contents of the modula register
TMA are transferred to TIMA as the result of a timer overflow, the same data is transferred to TIMA.
25
2.4.4 Interrupt Flags
Bit reset enabled
Interrupts are controlled by the IE (interrupt enable) flag.

The IF (interrupt request) flag can be used to determine which interrupt was requested.
The 5 types of interrupts are as follows.
Interrupt starting
Cause of Interrupt Priority
address The LCDC interrupt mode
can be selected (see STAT register).
Vertical blanking 1 0x0040
Mode 00
Mode 01
LCDC status interrupt 2 0x0048 Mode 10
LYC=LY consist
Timer overflow 3 0x0050
Serial transfer completion 4 0x0058
P10-P13 input signal goes low 5 0x0060
When multiple interrupts occur simultaneously, the IE flag of each is set, but only that with the highest
priority is started. Those with lower priorities are suspended.
26
Chapter 1: System
When using an interrupt, set the IF register to 0 before setting the IE register.
The interrupt process is as follows:
1 When an interrupt is processed, the corresponding IF flag is set.

2 Interrupt enabled.
If the IME flag (Interrupt Master Enable) and the corresponding IE flag are set, the
interrupt is performed by the following steps.
3 The IME flag is reset, and all interrupts are prohibited.
4 The contents of the PC (program counter) are pushed onto the stack RAM.
5 Control jumps to the interrupt starting address of the interrupt.
The resetting of the IF register that initiates the interrupt is a hardware reset.
The interrupt processing routine should push the registers during interrupt processing.
When an interrupt begins, all other interrupts are prohibited, but processing of the highest level interrupt
is enabled by controlling the IME and IE flags with instructions.
Return from the interrupt routine is performed by the RET1 and RET instructions.
If the RETI instruction is used for the return, the IME flag is automatically set even if a DI instruction is
executed in the interrupt processing routine.
IF the RET instruction is used for the return, the IME flag remains reset unless an EI instruction is
executed in the interrupt routine.
Each interrupt request flag of the IF register can be individually tested using instructions.
Interrupts are accepted during the op code fetch cycle of each instruction.
27
Á)
2.5 CPU FUNCTIONS (COMMON TO DMG/CGBÁ
This section describes the CPU functions that have been enhanced in CGB. Functions that are identical
in DMG and CGB are described in Section 2.4, CPU Functions (Common to DMG/CGBÀ). CPU
functions not available in DMG are described in Section 2.6, CPU Functions (CGB only).
2.5.1 Serial Cable Communication
Note In DMG mode, bit 1 of the SC register is set to 1 and cannot be changed,
but the transfer speed is fixed at 8 KHz.
Serial I/O (SIO) is controlled by the SB and SC registers.

The lowest bit (SC0) of the SC register can be used to select shift clock to be either the external clock
from the SCK terminal or the internal shift clock.
Sending and receiving occur simultaneously with a serial transfer.
If the data to be sent is set in the SB register and the serial transfer is then started, the received data is
set in the SB register when the transfer is finished.
Serial transfer procedure:
1 The data is set in the SB register.

2 Setting the highest SC register bit (SC 7) to 1 starts the transfer.
3 The 3-bit counter is reset and after 8 counts of the shift clock, the transfer is performed
until overflow occurs.
4 SC7 is reset.
5 If the serial transfer completion interrupt is enabled, the CPU is interrupted.
28
Chapter 1: System
When the shift clock goes low, the contents of the SB register are shifted leftward and the data is output
from the highest bit. When the shift clock goes high, input data from the SIN terminal are output to the
lowest bit of the SB register.
When the SCK terminal is in external-clock mode, it is pulled up to VDD.
If the highest bit of the SC register (SC7) is set, reading and writing to the SB register is prohibited.
An SIO serial transfer should be started (highest SC bit set) after the external or internal shift clock is
selected. Excessive shifting may result if the transfer is started before or at the same time as the shift
clock is selected.
If a transfer is performed using the external clock, the data is first set in the SB register, then the SC
register start flag is set and input from the external clock is awaited. The transfer start flag must be set
each time data is transferred.
The maximum setting for an external clock is 500 KHz.
Serial communication (SIO) specifications are essentially the same for DMG and CGB. In CGB,
however, the operating speed of the internal shift clock can be set to high by specifying a speed in bit
1.
29
SIO Timing Chart
1 2 3 4 5 6 7 8
SCK
SOUT SB7 SB6 SB5 SB4 SB3 SB2 SB1 SB0
SIN
7 6 5 4 3 2 1 0
Read Timing
Output Timing SB
SIO Block Diagram
SIN
7 6 5 4 3 2 1 0
SOUT 8-bit Shift Register
VDD
3-Bit Counter
Resistance
OUT
OR
Gate
SCK 3-State Buffer
IN1 IN2
CTRL
Inverter
IN1
Serial Control (SC)
Switch
OUT
IN2 1 2 3 4 5 6
SC0 SC7
CTRL
External/Internal Clock Selection Transfer Start
Internal Shift Clock (8 KHz/256 KHz)
30
Chapter 1: System
2.5.2 Serial Cable Communication: Reference flowchart
Flow until start of game
Start
(SB) Slave Code
RD Clear
-Select code other than $00 and $FF. (For both slave and
master code).
(SC) $80 -Clear the receive data buffer (RD).
-Both sides wait in receive-wait status.

N
-Game on which Start key pressed first becomes master by
2P Start?
sending master code to other game.
Y
Transfer
Y
RD = Master Code?
Slave Start -Game first notified that it is slave by master code
N sent from master. Subsequently moves to game flow.
Y
RD = Slave Code?
Master Start -Data sent when this side becomes master is the slave
N
code. Game subsequently moves to game flow.
N
V_BLANK?
SIO Interrupt
Y
RD (SB)
RD = Slave Code?
Transfer
TD: Transfer
(SB) TD Data Buffer
(SB) Slave Code
Timing of
1ms WAIT receive
(SC) $81 synchronized
with Power Up.
(SC) $80
RET
RETI
31
Flow after game start
If Master If Slave
Master Game Slave Game
Key Input Key Input
TD (Transfer Data) TD (Transfer Data)
Transfer Game Processing
Game Processing
N
SIO Finished?
N
V_BLANK Slave waits for
Y finish of SIO to
Y Transfer synchronize with
master. (This is an
example; not
necessary to
(SC) $81 implement this
way.)
SIO Interrupt RET SIO Interrupt
RD (SB)
RD (SB)
(SB) TD
(SB) TD
RETI (SC) $80
Set SIO Completion Flag
RETI
Data subsequently sent by the master is placed in (SB) and then sent to the slave at the
same time as the (SC) is set to $81. At exactly that same time, the master receives the
slave data. An SIO interrupt is then set in the slave and, as the flowchart indicates, the
slave sets the data to be sent to the master (current data).
Because the data sent from the slave are those loaded at the time of the previous
interrupt, the data sent to the master are one step (one pass through the main program)
behind the current slave data. Exactly the converse is true when this process is viewed
32
Chapter 1: System
from the perspective of the slave. An SIO interrupt is set in the master, and the master
sets the data to be sent to the slave (current data). In this case, because the data sent
from the master are those loaded at the time of the previous interrupt, the data sent to
slave are one step (one pass through main program) behind the current master data.
(*The data of the master and slave can be synchronized by setting the data for each
back 1 pass.)
In the example, 1 byte is sent per frame. (This is not required.) If several bytes are sent
continuously, a transmission interval longer than the processing time of other interrupts
(e.g. V_BLANK) should be used (usually around 1 mS). The reason is that if an attempt
is made to communicate with the slave during another interrupt, the slave cannot receive
the data until after the interrupt is finished. If the next data is transmitted before the
other interrupt is finished, the slave will be unable to receive the initial data of the
transmission.
33
2.6 CPU FUNCTIONS (CGB ONLY)

This section describes CPU functions that can be used only with CGB. Functions that are identical in
DMG and CGB are described in Section 2.4, CPU Functions (Common to DMG/CGBÀ). For information
on CPU functions enhanced in CGB, see Section 2.5, CPU Functions (Common to DMG/CGBÁ).
2.6.1 Bank Register for Game Boy Working RAM
The 32 KB of Game Boy working RAM is divided into 8 banks of 4 KB each. The CPU memory space
0xC000-0xCFFF is set to Bank 0, and the space 0xD000-0xDFFF is switched between banks 1-7.
Switching is performed using the lowest 3 bits of the bank register, SVBK. (If 0 is specified, Bank 1 is
selected.)
Note This register cannot be written to in DMG mode.
2.6.2 CPU Operating Speed
The speed of the CGB CPU can be changed to suit different purposes. In normal mode, each block
operates at the same speed as with the DMG CPU. In double-speed mode, all blocks except the liquid
crystal control circuit and the sound circuit operate at twice normal speed.
Normal mode: 1.05 MHz (CPU system clock)

Double-speed mode: 2.10 MHz (CPU system clock)
u Switching the CPU Operating Speed
Immediately after the CGB CPU is reset (immediately after reset cancellation), it operates in normal
mode. The CPU mode is switched by executing a STOP instruction with bit 0 of register Key 1 set to a
value of 1. If this is done in normal mode, the CPU is switched to double-speed mode; otherwise it is
switched to normal mode. Bit 0 of register Key 1 is automatically reset after the operating speed is
switched. In addition, bit 7 of register Key 1 serves as the CPU speed flag, indicating the current CPU
speed.
34
Chapter 1: System
Note When bit 0 of register Key 1 is set to 1, the standby function cannot be
used. When using the standby function, always confirm that bit 0 of
register Key 1 is set to 0. When switching the CPU speed, all interrupt-
enable flags should be reset and a STOP instruction executed with bits 4
and 5 of the P1 port register set to 1, as with the standby function (STOP
mode). When the CPU speed is switched, a return from STOP mode is
automatic, so it is not necessary to generate a STOP mode cancellation.
However, until the CPU speed has been changed and the system clock
returns, bits 4 and 5 of the P1 port register should be made to hold the
value 1.
Approximately 16 ms is required to switch from normal to double-speed mode, and approximately 32 ms

is needed to switch from double-speed to normal mode. In double-speed mode, the DIV register
(0xFF04) and the TIMA register (0xFF05) both operate at double speed. Battery life is shorter in double-
speed mode than in normal mode. The use of double-speed mode requires the corresponding mask
ROM and MBC.
35
Flow of Switching (when switching to double-speed mode)
In case the CPU operating speed needed to be switched, the current speed should always be checked
first using the speed flag (bit 7 of the KEY 1 register). This ensures that the speed will be switched to the
intended speed.
Read the speed flag

(Bit 7 of register Key 1)
No
Speed flag = 0?
Yes
Enable speed switching Switching unnecessary

(Set bit 0 of register Key 1)
Reset interrupt-request register IF
Reset interrupt-enable register IE
Set bits 4 and 5 of the P1 port register to 1
Execute STOP instruction
Switching Routine (example)

LD HL, KEY1
BIT 7, (HL)
JR NZ, _NEXT
SET 0, (HL)
XOR A
LD (IF), A
LD (IE), A
LD A, $30
LD (P1), A
STOP
_NEXT
36
Chapter 1: System
2.6.3 Infrared Communication
2.6.3.1 Port Register
The CGB system is equipped with an infrared communication function. An infrared signal can be output
by writing data to bit 0 of register RP. A received infrared signal is latched internally in the CPU by
positive edge of the system clock. (System clock goes to HIGH from LOW.) The latched data can be
read beginning from bit 1 of register RP by setting bits 6 and 7 to 1.
Note When data is not sent or received, always set the values of register RP to
0x00. This register cannot be written to in DMG mode.
2.6.3.2 Controlling Infrared Communication
Sender:
Setting bit 0 of the CPU register RP to 1 causes the LED to emit light; setting it to 0 turns off the LED.
Receiver:
If the photo transistor detects infrared light, bit 1 of register RP is set to 0; if no infrared light is detected,
this bit is set to 1.
2.6.3.3 Basic Format
When the receiver recognizes the unmodified signal from the sender as a logical value of 1 or 0, the
receiver actually cannot distinguish between the continuous transmission of 1s and the absence of
received infrared light. The status of the receiver is identical under these conditions. Consequently, to
ensure proper data transmission from sender to receiver in Game Boy Color infrared communication,
signals are distinguished by the size of the interval between the rising edge of the pulse of one received
signal to the rising edge of the subsequent received signal.
37
The following illustrates signals from a sender.
Double-speed 25 53 (units: µs)

Normal speed
“0” signal sent 25 76 1
RP register 0 bit
0
Double-speed 36 66
Normal speed
“1” signal sent 40 93 1
0
Double speed 50 65
Normal speed
Synchronous pulses 99 132 1
0
Double-speed 57 56 57
Normal speed
Connected pulses
114 112 114
Scatter in the source oscillation of Game Boy Color produces slight individual
differences.
2.6.3.4 Preparing for Data Transmission and Reception
To use infrared communication, data reception must be enabled by setting bits 6 and 7 of Game Boy
Color register RP to 1. However, even with both of these bits set to 1, data cannot immediately be
received. After setting bits 6 and 7 to 1, at least 50 ms should be allowed to pass before using the
infrared port.
38
Chapter 1: System
2.6.3.5 Transmitted Data
When data is transmitted and received, it is transmitted in packets. Each packet comprises the 4 parts
shown below, and each part is sandwiched between synchronous pulses. For more information, see
Section 2.6.3.7, Details of Data Transmission and Reception.
The data that comprises a packet is transmitted 1 bit at a time beginning from the MSB.
Transmission Packet
Connector Header Data Checksum
Connector:
Signal that implements an infrared communication connection between 2 Game Boy Colors. This is
always required in the initial packet. When the receiver receives the connector and recognizes it as a
connecting pulse, the receiver returns the same pulse to the sender. The sender then determines
whether this signal is a normal connecting pulse. If it is not recognized as a normal pulse, transmission
is interrupted at this stage. With continuous communication that is not halted before completion, this part
of the packet is unnecessary from the second packet onward.
Header:
Data indicating the type of data being sent and the total number of bytes.
Byte 1: Communication command

0x5A: transmission of raw data
At present, any value other than 0x5A causes an error.
(To be used for by other devices in future)
Byte 2: Total number of data in data portion of the packet

0x01-0xFF: Number of data
0x00: Indicates completion of communication to receiver.
Data:
The transmitted data itself. Maximum of 255 bytes.
There are no data if completion of communication is indicated to the receiver.
(The data portion of the packet consists only of a synchronous pulse.)
Checksum:
2 bytes of data consisting of the sum of the header and all data in the data portion of the packet.
Following this, the communication status is returned from receiver to sender.
2.6.3.6 Flow of Data Transmission and Reception
When data is transmitted and received, both Game Boy Colors are first placed in receive status. The
one with the send indicator is then designated as the sender, and the other one is designated as the
receiver. The flow of data transmission is shown below.
Connector Header Data Checksum Header

Sender
Connector Communication status

Receiver
39
1 Sender transmits connecting pulse.

2 The receiver calculates the width of the received connecting pulse. If the value is correct,
the receiver returns the same connecting pulse to the sender.
3 The sender calculates the width of the connecting pulse returned by the receiver. If the
value is correct, the sender determines that a connection has been properly established.
4 The header is transmitted.
5 The data is transmitted.
6 The checksum is transmitted.
7 The receiver returns the communication status to the sender.
8 When communication is complete, the header of the subsequently transmitted packet is
set to 0x00 + 0x00.
2.6.3.7 Details of Data Transmission and Reception
Connector (Indicates reading of the register RP)
Light emission
Sender
Light detection
Light emission
Receiver
Light detection
The two Game Boy Colors perform initial data reception, then the one designated as the sender (e.g., by
operations such as pressing button A) begins transmission. The connecting portion of the packet is
unnecessary from the second packet onward.
40
Chapter 1: System
The following illustrates the flow for implementing a connection.
Start of infrared
communication
N
o
Read bit 1 of register Y
RP Transmission e
Signal received?
N
o
Value read=0?
Y
e
Pulse-width measurement Transmission of
(software measurement of connecting pulse
H and L periods)
N
Received signal a o
proper connecting Start of reception,
pulse? measurement of width of
received pulse
Y
e
Send connecting pulse N Is the received signal

o the correct connecting
pulse?
Y
Communication Error e
Connection established Connection established
(receiver) (sender)
Header
Light emission by sender
Synchronous pulse OOH Number of data transmitted Synchronous pulse
Light detection by receiver

One byte indicating the data type and 1 byte indicating the number of transmitted data are
sandwiched between synchronous pulses.
Data
Light emission by sender
Synchronous pulse Transmitted data Synchronous pulse
Light detection by receiver

Between 1 and 255 bytes of transmitted data are sandwiched between
synchronous pulses.
41
A 2-byte checksum consisting of the sum of the header and transmitted data is sandwiched between
synchronous pulses. The receiver uses the checksum to determine whether the transmission was
performed properly and notifies the sender of the results of communication status.
The following section describes the details of communication status determination.
2.6.3.8 Communication Status
0x00: Communication OK
0x01: Checksum error
The results of the checksum calculated by the receiver do not agree with the checksum sent by the
sender.
In the following cases, the communication status cannot be returned to the sender even if an error is
generated during communication (no response from receiver).
♦ The wrong communication protocol is used.

♦ Data is transmitted using the wrong pulse width.
♦ One of them is operating in double-speed mode and the other is operating in normal mode.
♦ Communication is affected by sunlight or obstruction of the signal light.
2.6.3.9 Communication Error Processing
If an error described above in Communication Status is generated, the following error codes are returned
by subroutine.
Error Code Error Description

Checksum error (same for sender and receiver):
01 The results of the checksum calculated by the receiver
and the checksum sent by the sender do not agree.
Pulse width error:
Generated by the receiver when the width of the pulse of
02 the signal sent by the sender is too wide or narrow.
Generated by the sender when the width of the pulse of
the signal sent by the receiver is too wide or narrow.
Communication error:
Communication prevented by other causes.
The subroutine provided by Nintendo treats as an error
the case when the data value of the second byte of the
04
received header exceeds the number of data items to be
received, as determined beforehand by the receiver.
The routine also generates an error if the communication
command value of byte 1 of the header is not 0x5A.
42
Chapter 1: System
2.6.3.10 Communication Examples
The following figure shows the flow of processing when errors occur during communication. This should
be used as a reference when implementing data communication.
Hardware Unit 1 Hardware Unit 2
Send status Receive status
Connector
NG
If connector not returned by receiver.
Connector
OK
Data(1)
NG If status not returned from receiver.
Data (1) are re-sent, so caution is required.1
Data(1)
NG
If status is NG.
Data(1)
OK
OK, so data (1) are received.
Data(2)
OK
OK, so data (2) are received.
END
NG If status not returned from receiver.
Note that it is easy for sender to enter an
endless loop. 2
END
NG
If completion indicator is NG.
END
OK
OK, so both units end communication.
Finish Finish
43
1) Data(1) and Data(2) each represent 1 packet for transmission, not including the connector.
2) END signifies the packet used to indicate the completion of transmission (not including the
connector).
2.6.3.11 Usage Notes
When programming use of the infrared port, please note the following.
♦ When transmitting more than 256 bytes of data, ensure that the receiver keeps track of
which packet number is being received. When a communication error (status not returned
even though data was received) is generated, the sender will re-send the data, and the
receiver may lose track of the packet number (see note 1 of previous section).
♦ The sender is prone to entering an endless loop when the packet signifying transmission
completion is received. Therefore, the receiver should remain in receive status for
approximately 300 µs after returning the status (see note 2 of previous section).
♦ Depending on the power reserve of the battery, infrared communication may cause a
sudden drop in battery voltage and a complete loss of power.
♦ Ensure that the speed of the two communicating Game Boy Colors is the same (both
double-speed or both normal speed during communication).
♦ Noise can be heard from the speaker and headphones during communication, but this does
not indicate a problem with the hardware.
♦ Ensure that faulty or uncontrolled operation does not occur when infrared communication
signals are input from other game software and devices. Use particular care when using the
same subroutine to communicate between various types of games, because fault y or
uncontrolled operation is especially likely to occur in such cases. (Before performing data
communication, confirm that the other hardware participating in the transmission is using the
same game. This can be accomplished by means such as exchanging a unique key code.)
The following are items to note when using an infrared communication subroutine other than that
provided by Nintendo.
♦ Ensure that error-handling is implemented to prevent the program from entering

an endless loop when communication is interrupted by sunlight or obstruction of
the signal light.
♦ To reduce power consumption, use a maximum infrared LED emission pulse
duration of 150 µs and a duty ratio of approximately 1/2.
♦ Do not leave the infrared LED or photo transistor ON when not using infrared
communication.
2.6.3.12 Specifications
1) Communication Speed
Normal-speed mode: approximately 7.5 Kbps
Double-speed mode: approximately 10.5 Kbps
2) Communication distances: Minimum, 10 cm, Typical, 15 cm
º
3) Recommended directional angle: approximately ± 15
44
Chapter 2: Display Functions
CHAPTER 2: DISPLAY FUNCTIONS ............................................. 46

1. General Display Functions ............................................................. 46
1.1 Character Composition............................................................................46
1.2 LCD Display RAM .....................................................................................47
1.3 Character RAM .........................................................................................47
1.4 BG Display ................................................................................................50
1.5 LCD Screen...............................................................................................52
1.6 LCD Display Registers.............................................................................54
1.7 OAM Registers .........................................................................................58
1.8 DMA Registers..........................................................................................60
1.9 OBJ Display Priority ................................................................................64
2 LCD Color Display (CGB only) ......................................................... 65
2.1 Color Palettes ...........................................................................................65
2.2 Color Palette Composition ......................................................................65
2.3 Writing Data to a Color Palette................................................................66
2.4 Overlapping OBJ and BG ........................................................................67
2.5 Display Using Earlier DMG Software (DMG mode)................................67
45
CHAPTER 2: DISPLAY FUNCTIONS
1. GENERAL DISPLAY FUNCTIONS

1.1 Character Composition
♦ The basic character size is an 8 x 8-dot composition.

♦ With characters of the basic size:
128 OBJ-only characters are available (256 with CGB)
128 characters can be registered both as OBJ and BG characters (256 with CGB)
128 BG-only characters are available (256 with CGB)
♦ On DMG, characters can be represented using 4 shades of gray (including transparent).

♦ On CGB, characters can be represented using 32 shades for each color of RGB.
♦ The basic character size can be switched to an 8 x 16-dot composition for OBJ characters only. In this
case, however, only even-numbered character codes can be specified.
Even if an odd-numbered character code is specified, the display will be the same as that seen with an
even-numbered code.
♦ Up to 40 OBJ characters can be displayed in a single screen, and up to 10 characters can be displayed on
each horizontal line. (Stored in OAM (Display RAM: 0xFE00-0xFE9F))
♦ The display data for OBJ characters is stored in OAM (Display RAM: 0xFE00~0xFE9F) in the following
order:
y-axis coordinate
x-axis coordinate
Character code
attribute data
♦ Data is written to OAM from working RAM by DMA transfer.
♦ OBJ characters are automatically displayed to the screen using the data written to OAM.
♦ Data specification ranges for OBJ characters:

0x00 ≤ character code ≤ 0xFF
0x00 ≤ X ≤ 0xFF
0x00 ≤ Y ≤ 0xFF
46
1.2 LCD Display RAM
The DMG CPU has 8 KB (64 Kbits) of built-in LCD display RAM.
The CGB CPU has 16 KB (128 Kbits) of built-in LCD display RAM.
In CGB, 16 KB of memory can be joined in the 8 KB (64-Kbit) memory area (0x8000-0x9FFF) by bank
switching using the register VBK (0xFF4F). Bank switching is used exclusively in CGB and cannot be used in
DMG mode.
♦ Mapping of LCD Display RAM
The 16 KB of memory in CGB is partitioned into 2 x 8 KB by register VBK.

Bank 0 Bank 1
0x8000
Character Data Character Data
0x9800 BG Display Data 1

0x9C00
BG Display Data 2
0x9FFF
♦ Bank Register (CGB) for LCD Display RAM
Bank 0 is selected immediately after cancellation of a reset signal.

This function is available only in CGB. In DMG mode, bit 0 is forcibly set to 0, and its value cannot be
changed to 1.
1.3 Character RAM
♦ Character data can be written to the 6144 bytes from 0x8000 to 0x97FF.
♦ By default, the area from 0x8000 to 0x8FFF is allocated for OBJ character data storage.
♦ The register LCDC can be used to select either 0x8000-0x8FFF or 0x8800-0x97FF as the area for storing
BG and window character data.
♦ If the BG character data is allocated to 0x8000-0x8FFF, this data shares an area with OBJ data, and the
character dot data that corresponds to the CHR codes is also the same.
♦ By means of bank switching, CGB can store twice the amount of character data in LCD display RAM that
DMG can store. In this case, both Bank 1 and Bank 0 have the same mapping as the area in DMG.
47
Character Code Mapping
With BG character data allocated to 0x8800-0x97FF:

Data for 1 dot
CHR Code Address Bank 0 Shade Lower Bank 1 (CGB only)
7 6 5 4 3 2 1 0 Shade Upper
X00 0x8000
OBJ Code OBJ Code
"000" "100"
0x800F Dot Data Dot Data
X01 0x8010 OBJ Code OBJ Code
"001" "101"
X80 0x8800 OBJ Code & BG

OBJ Code & BG
Code Code
0x880F "080" Dot Data "180" Dot Data
X81 0x8810
OBJ Code & BG OBJ Code & BG
Code "081" Dot Code
0x881F Data "181" Dot Data
Area Shared
by OBJ and
BG
XFE 0x8FE0 OBJ Code & BG OBJ Code & BG
Code "0FE" Dot Code "1FE" Dot
0x8FEF Data Data
XFF 0x8FF0 OBJ Code & BG
OBJ Code & BG
Code "0FF" Dot Code "1FF" Dot
0x8FFF Data Data
X00 0x9000 BG Code "100"
BG Code
"000" Dot Dot Data
0x900F Data
X7F 0x97F0 BG Code BG Code

"07F" Dot "17F" Dot
0x97FF Data Data
• The case of 8 x 8 dots/block for both BG and OBJ:
CHR Codes:
<DMG> <CGB>
OBJ: 256 x 1 OBJ: 256 x 2
BG: 256 x 1 BG: 256 x 2
Note Because bank switching is not available in DMG mode, Bank 1 on the right side of
the figure is not available in this mode.
48
♦ The case of 8 x 16 dots/block (OBJ) and 8 x 8 dots/block (BG):

CHR Code Address
Bank 0 Bank 1 (CGB only)
X00 0x8000
0x800F OBJ Code OBJ Code

"000" Dot "100" Dot
X01 0x8010
Data Data
0x801F
X02 0x8020
OBJ Code "002" OBJ Code
0x802F Dot Data "102" Dot
X03 0x8030 Data
0x803F
X80 0x8800
OBJ Code "080" BJ Code "180" &
& BG Code "080" BG Code "180"
X81 0x8810 OBJ Code "080" OBJ Code "180"
& BG Code "081" & BG Code "181"
Area Shared by OBJ

and BG
XFE 0x8FE0 OBJ Code "0FE" OBJ Code "1FE"

& BG Code "0FE" & BG Code
0x8FEF Dot Data "1FE" Dot Data
XFF 0x8FF0
BJ Code "0FE" & OBJ Code "1FE"
BG Code "0FF" & BG Code "1FF"
0x8FFF Dot Data Dot Data
X00 0x9000 BG Code "000" BG Code "100"
Dot Data Dot Dat
0x900F
X7F 0x97F0 BGB Code

BGB Code
"17F" Dot
"07F" Dot
Data
0x97FF Data
CHR Codes:
<DMG> <CGB>
OBJ: 128 x 1 OBJ: 128 x 2
BG: 256 x 1 BG: 256 x 2
2) If BG character data is allocated to 0x8000-0x8FFF, these data share an area with OBJ data, and
the dot data that correspond to the CHR codes also are the same.
Note Because bank switching is not available in DMG mode, Bank 1 on the right side of
the figure is not available in this mode.
49
1.4 BG Display
Two screens of BG display can be held, Data 1 or Data 2.

Whether the BG display data is allocated to 0x9800-0x9BFF or to 0x9C00-0x9FFF is determined by bit 3 of the
LCDC register (0xFF40).
Because bank switching is not available in DMG mode, Bank 1 on the right side of the figure is not present in
this mode.
Bank 0 Bank 1 (CGB only)
0x9800 BG Display Data 1
0x9C00
BG Display Data 2
0x9FFF
Data for 32 x 32 character codes (256 x 256 dots) can be specified from 0x9800 or 0x9C00 as BG
display data. Of these, data for 20 x 18 character codes (160 x 144 dots) are displayed to the LCD
screen.
The screen can be scrolled vertically or horizontally one dot at a time by changing the values of scroll
registers SCX and SCY.
50
1) With BG display data allocated to 0x9800-0x9BFF:

256 dots
(32 blocks)
160 dots
(20 blocks)
RAM Address Block No.
0x9800 CHR Code & ATRB 0 0 1 2 19 20 30 31
0x9801 CHR Code & ATRB 1
32 33 34 51 52 62 63
0x9802 CHR Code & ATRB 2
64 65 66 83 84 94 95
144 dots
0x9BFD CHR Code & ATRB 1021 (18 blocks) 96 97 98 115 116 126 127
0x9BFE CHR Code & ATRB 1022

0x9BFF CHR Code & ATRB 1023
544 545 546 563

ATRB: Attrubute
576 577 578
608 609 610
256 dots
(32 blocks)
992 993 994 1022 1023
Portion displayed to LCD

when (SCX, SCY) = (0,0)
Portion displayed to LCD when
(SCX, SCY) = (152, 8)
Note: Attributes specified only with CGB
2) With BG display data allocated to 0x9C00-0x9FFF:
RAM Address Block No.

0x9C00 CHR Code & ATRB 0
Correspondence between LCD screen and block numbers as
0x0C01 CHR Code & ATRB 1 shown in preceding figure.
0x9C02 CHR Code & ATRB 2
0x9FFD CHR Code & ATRB 1021
0x9FFE CHR Code & ATRB 1022
0x9FFF CHR Code & ATRB 1023
ATRB: Attribute
Note: Attributes specified only with CGB.
51
1.5 LCD Screen
♦ Window Display
Specifying a position on the LCD screen using registers WX and WY causes the window to open
downward and to the right beginning from that position.
Window display data also can be specified as character codes, beginning from 0x9800 or 0x9C00 in
external SRAM.
OBJ character data is displayed in the window in the same way as the BG screen.
WX
O 159
O
LCD Screen Area
WY
Window Display Area
143
52
u Screen Timing
160 Segments
144 lines LCD Display Screen 15.66ms
10 lines
1.09ms
Vertical Blanking Period
108.7µs/1 line
Frame frequency: 59.7Hz
53
1.6 LCD Display Registers
54
STAT indicates the current status of the LCD controller.
Mode 00: A flag value of 1 represents a horizontal blanking period and means that the CPU
has access to display RAM (0x8000-0x9FFF).
When the value of the flag is 0, display RAM is in use by the LCD controller.
Mode 01: A flag value of 1 indicates a vertical blanking period and means that the CPU has
access (approximately 1 ms) to display RAM (0x8000-0x9FFF).
Mode 10: A flag value of 1 means that OAM (0xFE00-0xFE90) is being used by the LCD
controller and is inaccessible by the CPU.
Mode 11: A flag value of 1 means that the LCD controller is using OAM (0xFE00-0xFE90)
and display RAM (0x8000-0x9FFF). The CPU cannot access either of these areas.
In addition, the register allows selection of 1 of the 4 types of interrupts from the LCD
controller. Executing a write instruction for the match flag resets that flag but does not change
the mode flag.
Changing the values of SCY and SCX scrolls the BG screen vertically and horizontally one dot (or pixel) at a
time.
55
LY indicates which line of data is currently being transferred to the LCD driver. LY takes a value of 0-153, with
144-153 representing the vertical blanking period.
When the value of bit 7 of the LCDC register is 1, writing 1 to this again does not change the value of register
LY.
Writing a value of 0 to bit 7 of the LCDC register when its value is 1 stops the LCD controller, and the value of
register LY immediately becomes 0. (Note: Values should not be written to the register during screen display.)
Register LYC is a register compared with register LY. If they match, the Matchflag of the STAT register is set.
NOTE The following 3 registers (BGP, OBP0, and OBP1) are valid in DMG and DMG
mode of CGB. For information on CGB color palette settings, see Section 3, LCD
Color Display.
56
The grayscales (2 bit) for the character dot data is converted by the palette data (BG: register BGP; OBJ:
OBP0 or OBP1) and output to the LCD driver as data representing 4 shades (including transparent).
0 ≤ WY ≤ 143
With WY = 0, the window is displayed from the top edge of the LCD screen.
7 ≤ WX ≤ 166
With WX = 7, the window is displayed from the left edge of the LCD screen.
57
Values of 0-6 should not be specified for WX.
WX
0 159
0
LCD screen area
WY
Window Display Area
143
OBJ characters are displayed in the same manner in the window as on BG.
1.7 OAM Registers
OBJ (Object)
♦ Data for 40 objects (OBJ) can be loaded into internal OAM RAM in the CPU (0xFE00-OxFE9F), and 40
objects can be displayed to the LCD. Up to 10 objects can be displayed on the same Y line.
♦ Each object consists of a y-coordinate (8 bits), x-coordinate (8 bits), and CHR code (8 bits) and
specifications for BG and OBJ display priority (1 bit), vertical flip (1bit), horizontal flip (1 bit), DMG-mode
palette, (1 bit), character bank (1bit), and color palette (3 bits), for a total of 32 bits.
♦ An 8 x 8- or 8 x 16-dot block composition can be specified for an OBJ using bit 2 of the LCDC register.
With an 8 x 16-dot composition, the CHR code is specifed as an even number, as in DMG.
58
OAM Register
OBJ1-OBJ39 have the same composition as OBJ0.
Note In DMG mode, the lower 4 bits of the attribute flag are invalid; only the flags in
the upper 4 bits including the palette flag are valid.
59
1.8 DMA Registers
1.8.1 DMA Transfers in DMG
DMA transfers of 40 x 32 bits of data can be performed from the RAM area (0x8000-0xDFFF) to OAM
(OxFE00-0xFE9F). The transfer time is 160 µs.
Note that in DMG, data cannot be transferred by DMA from ROM area 0x0000-0x7FFF.
The starting address of a DMA transfer can be specified as 0x8000-0xDFFF in increments of 0x100.
Note that the method used for transfers from 0x8000-0x9FFF (display RAM) is different from that used for
transfers from other addresses.
Example 1
The following example shows how to perform a DMA transfer of 40 x 32 bits from the expansion RAM area
(0xC000-0xC09F) to OAM (0xFE00-0xFE9F).
During DMA, the CPU is run using the internal RAM area (0xFF80-0xFFFE) to prevent external bus conflicts.
1. The program writes the following instructions to internal RAM (0xFF80-0xFFFE):
Address Machine Code Label Instruction Comment
FF80 3E C0 LD A, 0C0H
E0 46 LD (DMA) , A ;C000-C09F→OAM
3E 28 LD A, 40 ;160-cycle wait
3D L1: DEC A
20 FD JR NZ, L1
C9 RET
2. Example of program that writes the above instructions to internal RAM starting from 0xFF80:
Label Instruction
LD C, 80H
LD B, 10
LD HL, DMADATA
L2: LD A, (HLI)
LD (C), A
INC C
DEC B
JR NZ, L2
•
•
•
DMADATA DB 3EH, 0C0H, 0E0H, 46H, 3EH

DB 28H, 3DH, 20H, 0FDH, 0C9H
60
3. When the DMA transfer is performed, the subroutine written to internal RAM shown in Step 1 above is
executed:
•
CALL 0FF80H :DMA transfer
•
Note The preceding program is used for DMA transfers performed within routines for
processing interrupts implemented by vertical blanking. In all other cases,
however, the program written to internal RAM should be as shown below to
prevent interrupts during a transfer.
Address Machine Code Label Instruction Comment

FF80 F3 DI :Interrupt disabled
3E C0 LD A, 0C0H
E0 46 LD (DMA), A :C000~C09F→0AM
3E 28 LD A, 40 :160-cycle wait
3D L1: DEC A
20 FD JR NZ, L1
FB EI :Interrupt enabled
C9 RET
Example 2
The example below shows a DMA transfer of 40 x 32 bits of data from the display RAM area (0x9F00-0x9F9F)
to OAM (0xFE00-0xFE9H).
Machine Code Label Instruction Comment
3E 9F LD A, 9FH
E0 46 LD (DMA), A :9F00~9F9F→0AM
Data can be transferred by DMA from 0x8000-0x9F9F to OAM either by the method shown in Example 1 or by
using only the above instructions.
1.8.2 DMA Transfers in CGB
Using the Earlier DMA Transfer Method
This DMA method transfers only 40 x 32 bits of data from 0-0xDFFF to OAM (0xFE00-0xFE9F). The transfer
starting address can be specified as 0-0xDFFF in increments of 0x100. The transfer method is the same as
that used in DMG, but when data is transferred from 0x8000-0x9FFF (LCD display RAM area), the data
transferred are those in the bank specified by bit 0 of register VBK. When transferring data from 0xD000-
0xDFFF (unit working RAM area), the data transferred are those in the bank specified by the lower 3 bits of
register SVBK.
Note When the CPU is operating at double-speed, the transfer rate is also doubled.
Using the New DMA Transfer Method

The DMA transfer method provided for DMG has been augmented in CGB with the following DMA transfer
functions.
1) Horizontal Blanking DMA Transfer
61
Sixteen bytes of data can be automatically transferred from the user program area (0-0x7FFF) or external and
unit working RAM area (0xA000-0xDFFF) to the LCD display RAM area (0x8000-0x9FFF) during each
horizontal blanking period. The number of lines transferred by DMA in a horizontal blanking period can be
specified as 1-128 by setting register HDMA5. CPU processing is halted during a DMA transfer period.
2) General-Purpose DMA Transfers

Between 16 and 2048 bytes (specified in 16-byte increments) are transferred from the user program area (0-
0x7FFF) or external and unit working RAM area (0xA000-0xDFFF) to the LCD display RAM area (0x8000-
0x9FFF). As with horizontal blanking DMA transfers, CPU operation is halted during the DMA transfer period.
The unit working RAM area (0xD000-0xDFFF) selected as the transfer source is the bank specified by register
SVBK.
The LCD display RAM area (0x8000-0x9FFF) selected as the transfer destination is the bank specified by
register VBK.
Special Notes
♦ The number of bytes transferred by the new DMA method must be specified in 16-byte increments; byte
counts that are not a multiple of 16 cannot be transferred.
♦ With the new DMA transfer method, transfers are performed at a fixed rate regardless of whether the
CPU is set to operate at normal or double-speed.
♦ Horizontal blanking DMA transfer should always be started with the LCDC on and the STAT mode set to
a value other than 00.
♦ General-purpose DMA transfer should be performed with the LCDC off or during a vertical blanking
period.
♦ When the new DMA transfer method is used to transfer data from the user program area (0-0x7FFF),
mask ROM and MBC for double-speed mode are required.
1.8.3 DMA Control Register: For both DMG and CGB
62
1.8.4 New DMA Control Registers: CGB only
Note These registers cannot be written to in DMG mode.
63
1.9 OBJ Display Priority

As a rule, when objects overlap, the one with the lower OBJ number is given priority. In DMG or DMG mode of
CGB, among overlapping objects with different x-coordinates, priority is given to the object with the smallest x-
coordinate.
1) The case with the same x-coordinate: For both DMG and CGB
B a = No. of OBJ A
b = No. of OBJ B
A c = No. of OBJ C
When a < b < c, objects are displayed as indicated in the figure at left.
2) The case with different x-coordinates: CGB only
a = No. of OBJ A When a < b < c, objects are is

b = No. of OBJ B displayed as indicated in the
c = No. of OBJ C figures below.
B
B
A
A
B C
C C A
3) Different x-coordinates: DMG/CGB in DMG mode
In DMB mode and with objects with different x-coordinates, the object with the smallest x-coordinate is given priority.
A B
a = No. of OBJ A
B b = No. of OBJ B
When a < b, objects are

displayed as indicated in the
A figure at left.
64
2. LCD COLOR DISPLAY (CGB ONLY)

The LCD unit of the CGB system can display 32 shades each for RGB, for a total 32,768 colors. A single color
palette consists of 4 colors selected from among these 32,768 colors. One of 8 palettes can be selected for
each BG and OBJ character. However, because each OBJ includes transparent data, each OBJ color palette
consists of 3 colors. The color palettes for BG and OBJ are independent of one another.
2.1 Color Palettes
♦ Eight palettes each are provided for BG and OBJ.

♦ Each palette consists of 4 colors and is specified by the display dot data (2 bits)
(Palette data numbers 0-3).
♦ The color palettes represent each color with 2 bytes, with 5 bits of data for each color of RGB (32,768
displayable colors).
2.2 Color Palette Composition
1. BG Color Palettes
Color Palette No. Palette Data No.
Color palette H00 Color palette L00 0

Color palette 0
Color palettes 1-7
2. OBJ Color Palettes
OBJ color palettes have the same composition as shown in the figure above.
65
2.3 Writing Data to a Color Palette
Data is written to color palettes using the write-specification and write-data registers. The lower 6 bits of the
write-specification register specifies the write address. When data is written to the write-data register, the data
will be written to the address specified by the write-specification register. If the highest bit of the write-
specification register is set to 1, the write address is then automatically incremented to specify the next
address. (The next address is read from the lower 6 bits of the write-specification register.)
The write-specification and write-data registers also are used to read data from color palettes. When the write-
data register is read, the data at the address specified by the write-specification register is read. When data is
read, the specified address is not incremented even if the most-significant bit of the write-specification register
is set to 1.
Note These registers cannot be written to in DMG mode.
66
2.4 Overlapping OBJ and BG
When objects are displayed, overlapping objects and background are displayed according to the display
priority flags for OBJ and BG, as indicated below. The BG display priority flag can be used to assign BG
display priority to individual characters.
Display Priority Flag Dot Data Screen Display

BG OBJ OBJ BG Palette Data
00 00 BG 00
0: 00 bg BG bg
0: Priori obj 00 OBJ obj
ty to obj bg OBJ obj
Use OBJ OBJ
priority 00 00 BG 00
1: 00 bg BG bg
Priori obj 00 OBJ obj
ty to obj bg BG bg
BG
00 00 BG 00
1: 0 00 bg BG bg
Highest 1 obj 00 OBJ obj
priority to obj bg BG bg
BG
(by
character)
* obj and bg represent dot data (01, 10, 11) for OBJ and BG, respectively.
2.5 Display Using Earlier DMG Software (DMG mode)
When earlier DMG software is used, coloring is performed automatically by the system using registers BGP,
OBP0, and OBP1. However, the display uses 3 palettes, 1 for BG, with 4 colors, and 2 for OBJ, each with 3
colors (excluding transparent; maximum of 10 colors in 1 screen).
1. BG Display
Colors specified in BG color palette No. 0 are displayed by the dot data (2 bits)
whose grayscales are specified by register BGP.
2. OBJ Display
Colors specified in OBJ color palettes No. 0 and No. 1 are displayed by the dot
data (2 bits) whose grayscales are specified by registers OBP0 and OBP1.
The CGB unit automatically selects the display color according to the color palette pre-registered in the CGB
(cannot be changed by a program). However, when turning on power to the CGB, the player can select from a
combination of the 12 colors registered in the unit. This function is available only in DMB mode.
67
68
Chapter 3: Sound Functions
Chapter 3: Sound Functions ..................................................... 70

1. Overview of Sound Functions........................................................... 70
2. Sound Control Registers ................................................................... 72
2.1 Sound 1 Mode Registers ..............................................................................72
2.5 Sound Control Registers..............................................................................80
3. VIN Terminal Usage Notes................................................................. 81
69
CHAPTER 3: SOUND FUNCTIONS

1. OVERVIEW OF SOUND FUNCTIONS
The sound circuitry consists of circuits that generate 4 types of sounds (Sounds 1-4). It can also synthesize
external audio input waveforms and output sounds. (External audio input is a function available only in CGB).
Sound 1: Generates a rectangle waveform with sweep and envelope functions.

Sound 2: Generates a rectangle waveform with an envelope function.
Sound 3: Outputs any waveform from waveform RAM.
Sound 4: Generates white noise with an envelope function.
Each sound has two modes, ON and OFF.
♦ ON Mode
Sounds are output according to data in the mode register for each sound.
The mode register data can be specified as needed while outputting sound.
♦ Initialization Flag
When the default envelope values are set and the length counter is restarted,
the initialization flag is set to 1 and the data is initialized.
♦ Mute
In the following instances, the synthesizer will enter mute status. No sound
will be output regardless of the ON flag setting.
Sounds 1, 2, and 4:
- When the output level is 0 with the default envelope value set to a value
other than 0000 and in DOWN mode
- When the step is 0 with the default envelope value set to a value of 0000
and in UP mode (NR12, NR22, and NR42 set to 0x08 and the initialization
flag set)
Sound 3:
With the output level set to mute
(bits 5 and 6 of NR32 set to 0)
♦ Stop Status
In the following cases, the ON flag is reset and sound output is halted.
-Sound output is halted by the length counter.
-With Sound 1, during a sweep operation, an overflow occurs in addition
mode.
♦ OFF Mode
Stops operation of the frequency counter and D/A converter and halts sound output.
♦ Sounds 1, 2, and 4:
-When the default level is set to 0000 with the envelope in DOWN mode
(initialization not required)
♦ Sound 3:
-When the Sound OFF flag (bit 7 of NR30) is set to 0.
Setting the Sound OFF flag to 1 cancels OFF mode.
70
Sound 3 is started by re-initialization.
♦ All Sounds OFF mode

-Setting the All Sounds ON/OFF flag (bit 7 of NR52) to 0 resets all of the
mode registers (for sounds 1, 2, 3, and 4) and halts sound output. Setting
the All Sounds ON/OFF flag to 1 cancels All Sounds OFF mode.
Note The sound mode registers should always be set after All Sound OFF mode is
canceled. The sound mode registers cannot be set in All Sound OFF mode.
♦ Sound Usage Notes

Use one of the following methods to halt sounds 1, 2, or 4.
1) Use NR51.
2) Set NR12, NR22, and NR42 to 0x08.
3) Set NR14, NR24, and NR44 to 0x80.
71
2. SOUND CONTROL REGISTERS

2.1 Sound 1 Mode Registers
Sound 1 is a circuit that generates a rectangle waveform with sweep and envelope functions. It is set by registers
NR10, NR11, NR12, NR13, and NR14.
♦ Sweep Shift Number

The frequency with one shift (NR13 and NR14) is determined by the following formula.
X (t) = X (t - 1) + X (t - 1) / 2n n = 0 to 7
X (0) = default data X (t-1) is the previous output frequency
If the result of this formula is a value consisting of more than 11 bits, sound output is stopped and the Sound
1 ON flag of NR52 (bit 0) is reset.
In a subtraction operation, if the subtrahend is less than 0, the result is the pre-calculation value X (t ) = X ( t -
1 ). However, if n = 0, shifting does not occur and the frequency is unchanged.
♦ Sweep time (ts)

Frequency varies with each value of ts.
000: Sweep OFF
001: ts=1/f128 (7.8ms)
010: ts=2/f128 (15.6ms)
011: ts=3/f128 (23.4ms)
100: ts=4/f128 (31.3ms)
101: ts=5/f128 (39.1ms)
110: ts=6/f128 (46.9ms)
111: ts=7/f128 (54.7ms) f128=128Hz
Example: When NR10 = 0x79 and the default frequency = 0x400, the sweep waveform appears as follows.
7.8ms 11.7ms 13.6ms
54.7ms 54.7ms 54.7ms
Note When the sweep function is not used, the increase/decrease flag should be set
to 1 (subtraction mode).
72
Sound length = (64 - t1) x (1/256) sec
Waveform Duty Cycles

00 : 12.5%
01 : 25%
10 : 50%
11 : 75%
Length of Envelope Steps:

Sets the length of each step of envelope amplification or attenuation.
Length of 1 step = N x (1/64) sec
When N = 0, the envelope function is stopped.
Default Envelope Value (0000 to 1111B):

16 step levels can be specified using the 4-bit D/A circuit.
Maximum is 1111B, and 0000 is the mute setting.
Example: When NR12 = 0x94, the Amp Gain is as follows.
Amp. Gain
4/64 sec
73
Counter/Continous Selection
0: Outputs continuous sound regardless of length data in register NR11.
1: Outputs sound for the duration specified by the length data in register NR11.
When sound output is finished, bit 0 of register NR52, the Sound 1 ON flag, is reset.
Initialize
Setting this bit to 1 restarts Sound 1.
With the 11-bit frequency data specified in NR13 and NR14 represented by x, the frequency, f, is determined
by the following formula.
f = 4194304 / (4 x 2 x (2048 - X)) Hz
3
Thus, the minimum frequency is 64 Hz and the maximum is 131.1 KHz.
♦ Sound 1 Usage Notes
When no sweep function is used with Sound 1, the sweep time should be set to 0 (sweep OFF). In addition,
either the sweep increase/decrease flag should be set to 1 or the sweep shift number set to 0 (set to 0x08-
0x0F or 0x00 in NR10).
Sound may not be produced if the sweep increase/decrease flag of NR10 is set to 0 (addition mode), the
sweep shift number set to a value other than 0, and the mode set to sweep OFF (e.g. NR10 = 0x01)
If the contents of the envelope register (NR12) needs to be changed during sound operation (ON flag set to
1), the initialize flag should be set after the value in the envelope register is set.
74
Sound 2 is a circuit that generates a rectangle waveform with an envelope function. It is set by registers NR21,
NR22, NR23, and NR24.
Initialize
75
Sound 3 is a circuit that generates user-defined waveforms. It automatically reads a waveform pattern (1 cycle)
written to waveform RAM at 0xFF30-0xFF3F, and it can output a sound while changing its length, frequency, and
level by registers NR30, NR31, NR32, NR33, and NR34.
The settings of the sound length and frequency functions and data are the same as for the Sound 1 circuit.
Output Level:
00: Mute
01: Output waveform RAM data (4-bit length) unmodified.
10: Output waveform RAM data (4-bit length) shifted 1 bit to the right (1/2).
11: Output waveform RAM data (4-bit length) shifted 2 bits to the right (1/4).
76
Initialization Flag
When the Sound OFF flag (bit 7, NR30) is set to 1, setting this bit to 1 restarts Sound 3.
• The initialization flag should not be set when the frequency is changed during Sound 3 output.
• Setting the initialization flag during Sound 3 operation (Sound 3 ON flag = 1) may destroy the contents
of waveform RAM.
• Setting the initialization flags for Sound 1, Sound 2, or Sound 4 does not cause a problem.
♦ Waveform RAM Composition
Waveform RAM consists of waveform patterns of 4 bits x 32 steps.
Address D7 D6 D5 D4 D3 D2 D1 D0
FF30 Step 0 Step 1
FF31 Step 2 Step 3
FF32 Step 4 Step 5
FF3F Step 30 Step 31
Example: Triangular Wave
Data
FF30H -- 01H, 23H, 45H, 67H

FH
89H, ABH, CDH, EFH,
EDH, CBH, A9H, 87H
65H, 43H, 21H, 00H
OH Step
OH 1FH
77
Sound 4 is a white-noise generating circuit. It can output sound while switching the number of steps of the
polynomial counter for random number generation and changing the frequency dividing ratio and envelope data
by registers NR41, NR42, NR43, and NR44.
Selecting the dividing ratio of the frequency:

Selects a 14-step prescalar input clock to produce the shift clock for the polynomial counter.
000 : fx1/23x2
001 : fx1/23x1
010 : fx1/23x1/2
011 : fx1/23x1/3
100 : fx1/23x1/4
101 : fx1/23x1/5
110 : fx1/23x1/6
111 : fx1/23x1/7 f=4/19430MHz
Selecting the number of steps for the polynomial counter:

0: 15 steps
1: 7 steps
78
Selecting the shift clock frequency of the polynomial counter:

0000: Dividing ratio frequency x 1/2
: :
1110: Prohibited code
1111: Prohibited code
Counter/Continuous Selection:
Initialize:
• Sound 4 Usage Notes
79
2.5 Sound Control Registers
Output Level:
000: Minimum level (Maximum level ÷ 8)
111: Maximum level
V i n → SO1 ON/OFF (V i n → SO2 ON/OFF)

Synthesizes audio input from Vin terminal with sounds 1-4 and ouputs the result.
0: No output
1: Output
80
3. VIN TERMINAL USAGE NOTES

• The VIN terminal can be used normally only in CGB. (Since the signal from the VIN terminal is too low to be
used, the VIN terminal cannot be used in DMG.)
• The maximum amplitude of the synthesized output is 3V.
• The design prevents the maximum amplitude from exceeding 3V when only sounds 1-4 are used, even
when the output level for each sound is set to the maximum.
When the output level is set to 0x0F, each sound is output at 0.75V.
0.75V x 4 = 3V
• The maximum amplitude of the synthesized sound output also must be limited to 3V or less when the VIN
terminal is used to input external sound.
Example: Using Sounds 1-4 and the VIN terminal
Use software to adjust the output levels of sounds 1-4 so that they do not exceed 0.6V (3V ÷).
Also limit the output level of the VIN terminal to 0.6V or less (input range of 1.9 - 2.5V).
+1.5V
+0.3
2.2V
-0.3
-1.5V
• The input voltage from the VIN terminal also can be increased if the levels of the internal sounds are low or
if not all 4 sounds are used (total output level of 3V or less).
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82
84
Chapter 4: CPU Instruction Set
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Chapter 5: Miscellaneous General Information
Chapter 5: Miscellaneous General Information...................114

1. Monitor ROM ................................................................................ 114
2. Recognition Data for CGB only in ROM-registered Data ......... 115
3. Power-Saving Routines for the Main Program ......................... 116
4. Software Created Exclusively for CGB...................................... 117
5. Software Created to Operate on CGB........................................ 118
6. Software Created to Operate on CGB: Example........................119

6.1 Program Specifications.......................................................................... 119
6.2 CGB Recognition Method ...................................................................... 120
6.3 Flowcharts............................................................................................... 121
113
CHAPTER 5: MISCELLANEOUS GENERAL INFORMATION
1. MONITOR ROM
The DMG and CGB CPU includes internal monitor ROM.
When power on the hardware is turned on, the monitor ROM checks for errors in the ‘Nintendo’ logo character
data within the game software.
If the data is correct, the Nintendo logo is displayed and the program is then started. If there is an error in the
data, the screen flashes repeatedly.
For information on registering the Nintendo logo character data, refer to Appendix 3 of this manual, Submission
Requirements.
The conditions required for starting the user program are as follows.
Starting Address 0x150 (default value) The starting address can be freely set by writing a
jump destination address at 0x102 and 0x103.
LCDC value 0x91

Stack value 0xFFFE
114
2. RECOGNITION DATA FOR CGB (CGB ONLY) IN ROM-REGISTERED DATA

As with software created for DMG, software for CGB (including software only for CGB) must place data
concerning items such as the name of the game and Game Pak specifications in the 80 bytes of the program
area between 0x100 and 0x14F. In the system, a code indicating whether the software is for CGB should be set
at address 0x143.
Note For an overall description of the ROM area shown below, please refer to
Appendix 3, Submission Requirements.
Setting a value of 0x80 or 0xC0 at this address causes the system to recognize the software as being for CGB.
If 0x00 or any value less than 0x7F (existing DMG software) is set at this address, the software is recognized as
non-CGB software and CGB functions (registers) are not available.
Starting
Address
+0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +A +B +C +D +E +F
0x0100 00 C3 Lo Hi
0x0110 'Nintendo' Character Data (0x104 - 0x133)
0x0120
0x0130 Game
Game Title (0x134 - 0x13E) Code
0x0140 Game Code 33
(0x13F-0x142)
CGB Support Code

Checksum
00: DMG Exclusive Complement
80: DMG/CGB Maker Code
Check
Compatible SGB Support Code Mask ROM Version
C0: CGB Exclusive Destination
Cassette Type
Code
ROM Size RAM Size
CGB/CGB Only: When operating on CGB, up to 56 colors can be displayed on a single screen.
Non-CGB: When operating on CGB, up to 10 colors can be displayed on a single screen.
Note Regardless of the type of game, the following fixed values should be stored at
the following addresses.
• Address 0x100=0x00
• Address 0x101=0xC3
• Address 0x14B=0x33
• Addresses 0x104 – 0x133=‘Nintendo’ character data
115
3. POWER-SAVING ROUTINES FOR THE MAIN PROGRAM

To minimize battery power consumption and extend battery life, inclusion of programs such as those shown
below is recommended.
During waiting for vertical blanking, halt the CPU system clock to reduce power consumption by the CPU and
ROM.
;****** ******
;****** Main Routine ******
;****** ******
MAIN
CALL CONT : Keypad input.
CALL GAME : Game or other processing.
VBLK_WT
HALT : Halt the system clock.
: Return from HALT mode if an interrupt is generated.
: Wait for a vertical blanking interrupt.
NOP : Used to avoid bugs in the rare case that the instruction.
after the HALT instruction is not executed.
LD A, (VBLK_F)
AND A : Generate a V-blank interrupt?
JR Z, VBLK_WT : Jump if a non-V-blank interrupt.
XOR A
LD (VBLK_F), A
JR MAIN
;****** ******
;****** Vertical Blanking Routine ******
;****** ******
VBLK
PUSH AF
PUSH BC
PUSH DE
PUSH HL
CALL DMA
LD A, 1 : Set the V-blank completion flag.

LD (VBLK_F), A
POP HL
POP DE
POP BC
POP AF
RETI
HALT instructions should not be executed while CGB horizontal blanking DMA is executed. (See Appendix 1,
Programming Cautions.)
116
4. SOFTWARE CREATED EXCLUSIVELY FOR CGB

Because the shape of the Game Pak for CGB-only software is the same as that for DMG, CGB-only Game Paks
also can be inserted in DMG. Therefore, a program that displays a message such as that shown below when a
CGB-only Game Pak is mistakenly inserted in DMG should always be included in the software. The upper part
of the message screen should display the official title of the game.
If the title is similar to that of other software (e.g., series software), a subtitle should also be displayed to
distinguish the programs from one another.
For information on software methods of distinguishing game units, see Section 6 of this chapter, Software
Created for CGB: Example.
Sample Message Display
[Game Title]
This software is intended only

for use with Game Boy Color.
Please use it with Game Boy Color.
117
5. SOFTWARE CREATED TO OPERATE ON CGB

As is shown below, CGB and DMG differ slightly in their specifications and operation. When creating
software to operate on CGB, please give appropriate consideration to these differences.
CGB DMG
When objects with different x- When objects with different x-

coordinates overlap, the object with coordinates overlap, the object with the
the lowest OBJ NO. is given display smallest x-coordinate is given display
priority. priority.
In CGB mode, BG display CANNOT BG display CAN be turned on and off
be turned off using bit 0 of the LCDC using bit 0 of the LCDC register
register (address 0xFF40). (address 0xFF40).
When the value of register WX

(address 0xFF4B) is 166, the window is
partially displayed.
When an instruction that register pair

increment is used, if the value of the
register pair is an address that specifies
OAM (0xFE00-0xFE9F), OAM may be
destroyed.
118
6. SOFTWARE CREATED TO OPERATE ON CGB: EXAMPLE

When creating software for CGB, a CGB support code is set in the ROM data area, and processing branches
according to the hardware used internally by the program. For more information, see the flowchart in Part 1
of Section 6.3 of this chapter. Limiting the functions used, as shown below, allows the same processing to be
used for different units without branching. For more information, see the flowchart in Part 2 of Section 6.3 of
this chapter.
The following example describes how to create a program that operates on both CGB and DMG and allows
display of 56 colors when running on CGB . Such means can be used to maintain compatibility with earlier
hardware (DMG) while using CGB functions.
6.1 Program Specifications
• Only bank 0 is used as the character data area.

• Only the bits that specify the color palette (bits 0-2 of bank 1) are used for BG attributes.
Bank 0 Bank 1
0x8000
Character Data Character Data
0x9800 BG attribute
BG CHR Code
0x9C00
BG CHR Code BG attribute
0x9FFF
7 6 5 4 3 2 1 0
0 0 0 0
Fixed at 0 Specify Color Palette
• Both the color palette and DMG-mode palette are set as attribute flags in the OAM register.
7 6 5 4 3 2 1 0
OAM Register 0 Attributes
Color Palette
DMG-Mode Palette
• None of the other expanded CGB functions are used.
119
6.2 CGB Recognition Method
Immediately after program startup, the initial value of the accumulator (register A) is read to determine
whether the hardware on which the program is operating is a DMG (SGB), MGB/MGL (SGB2) , or CGB.
0x01 → DMG (SGB)

0xFF → MGB/MGL (SGB2)
0x11 → CGB
120
6.3 Flowcharts
1) Branched Processing for CGB and DMG/MGB/MGL
CGB support code (0x80) written to ROM

data area (address 0x143)
Start
Supplemental processing for
CGB support
0x11 CGB
Unit Discrimination:
Value of register A is
read
CGB flag 1
0x01 (DMG)
0xFF (MGB/MGL)
Initialization
Color Palette Transfer (rewrite)
OAM Transfer
BG CHR Code Transfer (LCD Display RAM Bank 0)
= 1 (CGB)
CGB?
CGB Flag Check
LCD display RAM switched to bank 1,

=0
(DMG/MGB/MGL) BG attributes transferred.
LCDC ON
Color display in CGB
Monochrome display in DMG/MGB/MGL
LCDC OFF
or blanking
121
2) Uniform processing for CGB and DMG/MGB/MGL
CGB support code (0x80) written to ROM data area

(address 0x143)
Start Supplemental processing for

CGB support
Initialization
Color Palette Transfer (rewrite)
OAM Transfer
BG Attribute Transfer (LCD Display RAM Bank 1)
BG CHR Code Transfer (LCD Display RAM Bank 0)
LCDC ON
Color display in CGB
Monochrome display in DMG/MGB/MGL
LCDC OFF
or blanking
Note The BG attributes should always be transferred before the BG character code.
Even if only the BG attributes are changed, always transfer the character code
from that same address.
122
Chapter 6: The Super Game Boy System
Chapter 6: The Super Game Boy System ............................124

1. Overview......................................................................................... 124
1.1 What is Super Game Boy? .....................................................................124
1.2 Block Diagram.........................................................................................125
1.3 Functions.................................................................................................126
1.4 System Program .....................................................................................126
2. Sending Commands and Data to SUPER NES.......................... 127
2.1 System Commands ................................................................................127
2.2 Data Transfer Using an Image Signal....................................................131
3. System Commands ...................................................................... 132
3.1 System Command Summary .................................................................132
3.2 System Command Details......................................................................133
3.3 Cautions Regarding Sending Commands ............................................167
3.4 Sound Flag Summary .............................................................................167
4. Miscellaneous ............................................................................... 173
4.1 Reading Input from Multiple Controllers ..............................................173
4.2 Recognizing SGB....................................................................................174
4.3 SGB Register Summary .........................................................................176
4.4 Flowchart of Initial Settings Routine.....................................................177
5. Programming Cautions................................................................ 178
5.1 ROM Registration Data...........................................................................178
5.2 Initial Data................................................................................................178
5.3 SOU_TRN default data ...........................................................................179
123
CHAPTER 6: THE SUPER GAME BOY SYSTEM
1. OVERVIEW
1.1 What is Super Game Boy (SGB)?
SGB is a device that enables Game Boy software to be enjoyed on a TV screen. Game Boy software can be
plugged into the SGB, which operates on the Super Nintendo Entertainment System (Super NES).
SGB consists of the basic Game Boy circuitry, and components such as an Intercommunication Device (ICD, with
built-in SGB RAM), the system program, and a CIC.
Basic SGB operation involves conversion by the ICD of 2-bit, 4 grayscale image signals generated by the SGB
CPU to SUPER NES character data and storage of these data in SGB RAM. The system program subsequently
transfers this data by DMA to SUPER NES WRAM and then to VRAM. The above operations are performed
repeatedly to display the Game Boy screen on a TV screen.
Unmodified sound output from the SGB CPU is linked to the SUPER NES sound mixing circuit and is output from
the speaker on the TV.
These operations are controlled by the SGB system program and therefore require no special consideration when
programming for Game Boy.
Game Boy software not specifically created for SGB provides 4 colors in 4 grayscales. These colors are selected
from several color patterns provided in the system program. Programming using the system commands
described later allows a game to be represented using 4 palettes of 4 colors each per screen and SUPER NES
functions such as SUPER NES sound.
Super Game Boy comes in 2 models: the 1994 model, which has no communication connector, and the 1998
model, which is equipped with a communication connector.
This manual uses the term SGB2 when discussing points that concern only the 1998 model. Descriptions that
use the term Super Game Boy or SGB refer to both Super Game Boy models. SGB2 allows game
representations that use SHVC functions for communication play. (SGB2 has not been released in the U.S.
market.)
124
1.2 Block Diagram
SYS CLK 6-Pin Subconnector (SGB2 only)
VISUAL DATA
Address
KEY DATA
System
Address
Program
Data
SGBRA
ROM
M
Register
file
Data
ICD
SGB-CPU
SOUND L, R CIC
W-RAM V-RAM
64Kbit 64Kbit
32P Card Connector
DMG Game SNES62P Card Edge
Pak
125
1.3 Functions
The types of representations indicated below can be implemented using SUPER NES
functions invoked by sending system commands.
For more information, please see Section 3 in this chapter, System Commands.
Image Functions
• Up to 4 palettes of 4 colors each can be represented on a single screen.
• Multiple areas can be specified for each screen, and separate color palette attributes can be specified for
each area.
• Color palette attributes can be specified separately for each character (8 x 8 bits).
Sound Functions
• The rich variety of sound effects included the system program can be generated by the SUPER NES
audio processing unit (APU).
• The sound generator included in the system program can be used by transferring music data.
Controller Functions
• Data from multiple SUPER NES controllers data can be read, providing for multiplayer games that can
accommodate between 2 and 4 players.
Miscellaneous
• SUPER NES program data can be transferred.
1.4 System Program
The system program can provide the following features.
• On the T.V. screen, the system program displays the space outside the game screen (picture frame).
The picture frame has the following features.

• The frame can be selected from among 9 pre-loaded frames.
• A mode in which an image created by the game producer is transferred and displayed as the frame.
• A drawing mode that allows the user to create the frame.
Features of the color palette selection screen are as follows.

• Palettes can be selected from among 32 pre-loaded palettes.
• A mode that allows colors to be set from DMG in DMG games.
A mode is available that allows the user to arrange the colors on a palette.
A screen is provided for changing the key configuration of the controller.
126
• If the commands described in Section 3.2 in this chapter, System Command Details, are sent to the register
file, Super NES functions, such as those described in Section 1.3, Functions, can be used by having the
system program read these commands.
2. SENDING COMMANDS AND DATA TO SUPER NES

The following 2 methods can be used to send data from a DMG program to Super NES.
Send data to the register file using P14 and P15. The size of the register file is 128 bits;
this is referred to as 1 packet.
Send data to SGB RAM using an image signal.
NOTE Data transfers from the register file and SGB RAM to SUPER NES are performed
by the system program.
2.1 System Commands
Using the register file to transmit system commands allows the various SUPER NES functions described below to
be used in games.
The system program receives the commands and performs the specified processing.
• Data Format of System Commands
1) Data Transmission Methods
Using 2 bits in SGB (P14 and P15 of SGB CPU), data is sent to the register file by serial transmission.
127
The system program reads the contents written to the register file.
1. Start write
P14 H
A LOW pulse is output to both P14 and P15.
L This is required for transmission of each packet (128 bits) .
P15 H
2. Write 0
P14 H
P15 is fixed at HIGH, and a
L LOW pulse is output to P14.
P15 H
3. Write 1
P14 H
P14 is fixed at HIGH, and
L a LOW pulse is output to P15.
P15 H
P14
or P15
Pulse Width
P15 a, c, e 5 µ s (min)
or P14
b, d 15 µ s (min)
a b c d e
128
2) Write Example
d0 d1 d2 d3 d4 d5 d6
P14
P15
Start 1 1 0 0 1 0 1
3) Format of Data Transmitted to Register File
Direction of data transmission

d7 d6 d5 d4 d3 d2 d1 d0
00h
System Command No. of Packets Transmitted
No. of packets transmitted: 0x1-0x7

Indicates the total, including the first packet.
System command code: 0x0-0x1F
d7 d6 d5 d4 d3 d2 d1 d0
01h
02h
Transmitted Data
: : : :
0Fh
0 0 transmitted in bit 129.

If 2 or more packets are used for one system command, bits 0x00-0xF of the second packet
onward are used for data.
129
Transmission Procedure
1. Start of write
2. Data transmission (example)
Transmitted Data
d0, d1, d2, d3, d4, d5, d6, d7
00h : 0 1 0 1 0 0 0 0
No. of packets: 0x2 Command code: 0x1
0x01: data
0x02: data
: :
: :
0xF: data
3. Transmission of 0 in bit 129
Bit 129: 0
4. Start of write
5. Data transmission: second packet
0x00: data
0x01: data
: :
: :
0xF: data
1. Transmission of 0 in bit 129
Bit 129: 0
4) Transmission Interval
The interval between completion of transmission of one packet (128 bits + 1 bit) and
transmission of the next packet is set at approximately 60 msec (4 frames).
Transmission ends Transmission starts Transmission ends Transmssion starts
• • •
4 frames 1 packet 4 frames
5) Transmission Bit 129
The data in bit 129 marks the end of one packet, so it should always be transmitted.
130
2.2 Data Transfer Using an Image Signal
Data and programs stored in a cartridge can be transferred using the image signal transmission path (LD0, LD1).
Character data stored in DMG VRAM and displayed are then stored in SGB RAM. The system program usually
transfers these data to SUPER NES VRAM as character data. However, when a specific command is received,
the data is handled as data for command processing.
The displayed image signal is handled directly as data, so be careful to ensure that the OBJ display and window
are set to OFF, the correct values are set for the DMB color palette, and the BG to be displayed is correctly
transferred.
When data is transferred they are displayed to the screen, so the system command MASK_EN must be used to
mask the screen.
For more information, see Section 3.2 in this chapter, System Command Details.
Note Commands that transfer data using image signals are indicated by the heading,
Data Transfer Using VRAM.
131
3. SYSTEM COMMANDS
3.1 System Command Summary
Command Command Code Command Command Code
PALO1 00 DATA_TRN 10
PAL23 01 MLT_REQ 11
PAL03 02 JUMP 12
PAL12 03 CHR_TRN 13
ATTR_BLK 04 PCT_TRN 14
ATTR_LIN 05 ATTR_TRN 15
ATTR_DIV 06 ATTR_SET 16
ATTR_CHR 07 MASK_EN 17
SOUND 08 PAL_PRI 19
SOU_TRN 09
Use prohibited 0D
PAL_SET 0A
Use prohibited 18
PAL_TRN 0B
ATRC_EN 0C
ICON_EN 0E
DATA_SND 0F
132
3.2 System Command Details
Please refer to the following map in the discussion of coordinate settings and color palette area specifications in
the description of the system command functions.
H 160 dots [20 Characters]
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13
00
01
02
03
04
05
06
07
144 dots
[18
characters] 08
09
0A
0B
0C
0D
0E
0F
10
11
DMG Window
133
Setting the Color Palettes and Attributes
DMG Window
SGB Color Palette 00 01 10 11
SGB Color Palette0
SGB Color Palette1 Indirect setting of

attributes by file number
SGB Color Palette2 (Command ATTR-SET)
Direct setting of
attributes
SGB Color Palette3
(Command ATTR-BLK)
(Command ATTR-LIN)
(Command ATTR-DIV)
Attribute Files
(Command ATTR-CHR)
Indirect setting of SGB color
(Command PAL-SET)
ATFO-ATF44
DMG window attribute files

Direct setting of
System Color Palette 00 01 10 11 (45 files)
SGB color palettes
(Command PAL01)
System Color Palette0
(Command PAL23)
(Command PAL03)
(Command PAL12)
.....................
Command PAL-SET/Option
SGB
Color data setting of Game Pak Attribute file
system color palette transfer
(Command PAL- (Command ATTR-TRN)
TRN)
Note Bit 00 of SGB color palettes 0 – 3 have the same color. The color setting in effect
for this bit is the most recent setting.
134
DMG Color Palettes and SGB Color Palettes

With DMG screen data representations, colors in SGB are converted from the grayscale data registered in the
DMG color palettes, rather than being converted from the bit data for the character.
00 01 10 11 (m,n) Bit n layer
DMG palette 00 01 10 11 * 00-11 in the palette are

grayscale data
light 00> 01> 10> 11 dark
Table 1
00 01 10 11
Red Green Gray Black
SGB palette Bit m layer
Table 2
Example: When the grayscale data shown

in Table 1 are specified for the DMG
palette, the character represented on the
DMG LCD is as shown in the DMG
character image figure below and to the
Accordingly, when the color data shown in
Table 2 are specified for the SGB palette,
the character image represented on SUPER
NES is as shown in the SGB character
image figure below and to the right.
DMG Character Image
10 00
However, if bit 11 of the DMG palette is
set to grayscale 00, the portion of 00 01
the DMG character image is displayed
with a 00 grayscale, and the portion 00 11
of the SGB character image is displayed
as red rather than black. 00-11: grayscale data
SGB character image

Thus, in this case, when character data
Gray Red
display using all of the colors on the
SGB palette is desired, a separate
Red Green
grayscale palette (DMG palette) for
SGB must be provided, DMG and SGB
Red Black
must be distinguished, and the
program must be made to branch
accordingly.
(See Section 4.2, Recognizing SGB.)
135
When representing DMG grayscale on SGB, the image can be faithfully represented if 00 of the SGB palette is set to a
light color and 11 to a dark color.
Command: PAL01 (Code: 0x00)
Function: Sets the color data of SGB color palettes 0 and 1.
d7 d0
0x00 0 0 0 0 0 0 0 1
Number of packets: 0x1 (fixed)
Command code: 0x00
d7 d0 d7 d0
0x01 Palette0 Color00 Data LOW 8bit 0x02 -- Palette0 Color00 Data HIGH 7bit
d7 d0 d7 d0
0x09 Palette1 Color01 Data LOW 8bit 0x0A -- Palette1 Color01 Data HIGH 7bit
0x0B Palette1 Color10 Data LOW 8bit 0x0C -- Palette1 Color10 Data HIGH 7bit
0x0D Palette1 Color11 Data LOW 8bit 0x0E -- Palette1 Color11 Data HIGH 7bit
0x0F
0 0 0 0 0 0 0 0
136
Function: Sets the color data for SGB color palettes 2 and 3.
d7 d0
0x00 0 0 0 0 0 0 0 0
Command code: 0x01
d7 d0 d7 d0
d7 d0 d7 d0
0x0F 0 0 0 0 0 0 0 0
137
d7 d0
0x00 0 0 0 0 1 0 0 1
Command code: 0x02
d7 d0 d7 d0
d7 d0 d7 d0
0x0F 0 0 0 0 0 0 0 0
138
Command: PAL12 Code: 0x03
d7 d0
0x00 0 0 0 1 1 0 0 1
Command code: 0x03
d7 d0 d7 d0
d7 d0 d7 d0
0x0F 0 0 0 0 0 0 0 0
139
Command Code: ATTR_BLK (Code: 0x04)
Function: Applies the specified color palette attributes to areas inside and outside the square.
d7 d0
0x00 0 0 1 0 0
Number of packets: 0x1 – 0x7
Command code: 0x04

d7 d0
0x01 -- -- --
Number of data groups: 0x1- 0x12 (max)

(A single group consists of a control code, color palette
specification, and coordinates.)
d7 d0
0x02 -- -- -- -- -- Control Code

Controls the attribute area according to the data in 0x03.
Control Codes
000 No control occurs.
Applies the attributes specified by d1 and d0 of 0x03 only to the area within the
001
square (including the CHR border).
Applies the color palette attributes specified by d3 and d2 of 0x03 only on the
010
square CHR border.
Applies the color palette attributes specified by d1 and d0 of 0x03 only to the
011 area within the square, and applies the color palette attributes specified by d3
and d2 of 0x03 only to the border of the square.
Applies the attributes specified by d5 and d4 of 0x03 only to the area outside the
100
square (including the CHR border).
Applies the color palette attributes specified by d1 and d0 of 0x03 to the area
101 within the square, and applies the color palette attributes specified by d5 and d4
of 0x03 to the area outside of the CHR border. (CHR border is unchanged.)
Applies the color palette attributes specified by d5 and d4 of 0x03 only to the
110 area outside of the square, and applies the color palette attributes specified by
d3 and d2 of 0x03 to the CHR border .
Applies the specified color palette attributes to the area inside the square, to the
111
CHR border line, and to the area outside the CHR border .
The color palette attributes of areas not specified are not changed.
140
d7 d0
0x03 -- -- Specifies the color palette
Color palette number for the area inside the square.

Color palette number for character area on the square
Color palette number for area outside the square.
d7 d0
0x04 -- -- -- Starting point H1 Starting (upper left) and ending (lower right) points of
the square.
0x05 -- -- -- Starting point V1
Coordinate data
0x06 -- -- -- Ending point h1 (H1,V1) H
0x07 -- -- -- Ending point v1
V
(h1,v1)
d7 d0
0x08 -- -- -- -- -- Control Code
0x09 -- -- Specifies the color palette
0x0A -- -- -- Starting point H2
0x0B -- -- -- Starting point V2

Coordinate data
0x0C -- -- -- Ending point h2
Ending point v2
0x0D -- -- --
0x0E 0 0 0 0 0 0 0 0
0x0F 0 0 0 0 0 0 0 0
Note If the number of packets is 1, 0x00 is written to 0x0E and 0x0F. If the number of
packets exceeds 1, the control code and color palette specification code of the
next data item are written to 0x0E and 0x0F, respectively.
141
When the number of packets exceeds 1:

d7 d0
0x0E
-- -- -- -- -- Control Code
0x0F
-- --
Color palette specification ↑Remainder of previous/first packet
0x00 Starting point H3 ↓Second packet
-- -- --

Coordinate data
0x02 -- -- -- Ending point h3
d7 d0
0x04 -- -- -- -- -- Control code
0x05 -- -- Color palette specification
0x06 -- -- -- Starting point H4

Coordinate data
0x08 -- -- -- Ending point h4
d7 d0
0x0A -- -- -- -- -- Control code
0x0B -- -- Color palette specification
0x0C -- -- -- Starting point H5
0x0D -- -- -- Starting point V5

Coordinate data
0x0E -- -- -- Ending point h5
0x0F -- -- -- Ending point v5
0x00 -- -- -- -- -- Control code

Color palette specification
0x01 -- --
0x02 *
*
* The empty area of the packet is filled with 0x00.
Note When there is no area inside the square border (e.g., h1 = H1 + 1), a control code
such as one that sets the color attribute for the area inside the border cannot be
used.
142
Please note that when ATTR_BLK, ATTR_LIN, ATTR_DIV, or ATTR_CHR are used, the data that is sent are valid
even if MASK_EN (freezes screen immediately before masking) is selected.
When using MASK_EN before these commands, use 0x10 or 0x11 as the argument. If 0x01 is used as the
MASK_EN argument, ATTR_TRN and ATTR_SET should be used.
143
Command: ATTR_LIN (Code: 0x05)
Function: Applies the specified color palette attribute to a coordinate line.
d7 d0
0x00 0 0 1 0 1

Command code: 0x05
d7 d0
0x01
Data group: 0x1- 0x6E (max)
d7 d0
0x02 Line Number First data item
Palette number
H/V mode bit
0: Specifies the H coordinate character line number (vertical line)
1: Specifies the V coordinate character line number (horizontal line)
d7 d0
0x03 Character Line
2nd data item
0x04 Character Line

3rd data item
: : : :
0x0D Character Line th
13 data item
th
0x0F Character Line 14 data item
nth Packet
0x00 Character Line
0x01 Character Line
: : : :
0x0F Character Line
* See the note on ATTR_BLK.
144
Example
d7 d0
0x00 0 0 1 0 1 0 0 1
Number of packets transmitted: 1
Command code: 0x05
d7 d0
0x01 0 0 0 0 0 0 1 0 Number of data groups: 2
0x02 1 0 1 0 1 1 1 1
Character line number: 0x0F

Palette number: 1
Coordinate setting: V
0x03 0 0 0 0 0 0 1 0
Character line number: 0x02

Palette number: 0
Coordinate setting: H
Applies the Palette 0 attribute to this line.

→H 02
↓
V
0F Applies the Palette 1 attribute to this line.
* The color of intersection of the two lines is decided by the last line color.
145
Command: ATTR_DIV (Code: 0x06)
Function: Divides the color palette attributes of the screen by the specified coordinates.
d7 d0
0x00 0 0 1 1 0 0 0 1
Number of packets: 0x1
Command code: 0x06
d7 d0
0x01 --
Number of the color palette of the bottom or right division.
Number of the color palette of the top or left division.
Color palette number of the character line on the dividing line.
0: Divide by the H coordinate character line number

(vertical line)
1: Divide by the V coordinate character line number
(horizontal line)
d7 d0
0x02 -- -- -- Coordinate data
* 0x03 - 0x0F should be filled with 0x00.
* See note on ATTR_BLK.
146
Example
d7 d0
0x00 0 0 1 1 0 0 0 1
Number of packets transmitted: 1
Command code: 0x06
d7 d0
0x01 -- 0 1 0 0 1 1 1
Palette: 3
Palette: 1
Palette: 2
Coordinate setting: H
0x02 -- -- -- 0 0 1 1 0
Character line number: 0x06
Sets this character line to the Palette 2 attribute.

→H 06
↓
V
Palette 1 Palette 3
147
Command: ATTRIBUTE_CHR (Code: 0x07)
Function: Specifies a color palette for each character.
d7 d0
0x00 0 0 1 1 1
Command code: 0x07
d7 d0
0x01 -- -- --
H coordinate of start of write

d7 d0
0x02 -- -- --
V coordinate of start of write

d7 d0
0x03
Number of data items to send

Each data item (2 bits) specifies a color palette.
d7 d0
0x04 -- -- -- -- -- -- --
Most significant bit of number of data items sent, specified in

0x03
(The maximum number of data items required is 360.)
d7 d0
0x05 -- -- -- -- -- -- --
Write horizontally: 0; Write vertically
148
START
Horizontal write (H direction)
Pal.No. Pal.No Pal.No Pal.No
0x06
START
Pal.No Pal.No Pal.No Pal.No
0x07
: : : :
Vertical write (V direction)
: : : : START
: : : :
Sending color palette data for entire screen:
: : : :
: : : :
6th Packet
0x0E Pal.No. Pal.No. Pal.No. Pal.No.
0x0F Pal.No. Pal.No. Pal.No. Pal.No. Data items nos. 357, 358, 359, and 360.
* See note on ATTR_BLK.
149
Command: SOUND (Code: 0x08)
Function: Generates and halts internal sound effects and sounds that use internal tone data.
d7 d0
0x00 0 1 0 0 0 0 0 1

Command code: 0x08
d7 d0
0x01 Sound Effect A (PORT1): decay
Sound code
0x02 Sound Effect B (PORT2): sustain
Sound code
0x03
Sound Effect A attributes

Scale: 00<01<10<11
Low High
Volume: 00: high; 01: medium; 10: low

11: enable mute (fade out)
Sound Effect B attributes

Scale: 00<01<10<11
Low High
Volume: 00: high; 01: medium; 10: low
d7 d0
0x04
BGM code
When not used, 0x00 always written.
* For more information, see Section 3.4, Sound Flag Lists.
150
Command: SOU_TRN (Code: 0x09)

(Data transfer using VRAM)
Function: Sends a sound program and sound data to the APU.
d7 d0
0x00 0 1 0 0 1 0 0 1
Command code: 0x09
* The 4 Kbytes of SGB RAM data immediately following the command is sent to APU RAM.
The data to be transferred must be prepared prior to the frame preceding issuance of the command.
The transfer ends 6 frames after the command is issued (not counting the frame in which the command is
issued).
The beginning of the data for transfer contains a 16-bit representation of the number of data items and the
transfer destination address, and the end contains an ending code and the starting address of the program.
For more information, see Chapter 7: Super Game Boy Sound.
APU RAM program area: 0x0400 – 0x2AFF/9.75 Kbytes

APU RAM music data area: 0x2B00 – 0x4AFF/8 Kbytes
APU RAM sampling data area: 0x4DB0-0xEEFF/40.25 Kbytes
Note When SOU_TRN is used, 5 packets of SOU_TRN initialization should be sent to

the register file. For more information, see Section 5.3, SOU_TRN Initialization
Data.
151
Command: PAL_SET (Code: 0x0A)
Function: Applies system color palettes to SGB color palettes.
d7 d0
0x00 0 1 0 1 0 0 0 1

Command code: 0x0A
d7 d0
0x01
Number of the system color palette to apply to SGB color

(LOW)
d7 d0
0x02 -- -- -- -- -- -- --
Number of the system color palette to apply to SGB color

(HIGH)
* The system color palettes selected are palettes 000-511.
Number of the system color palette applied to SGB color palette 1.
d7 d0
0x03 LOW
0x04 -- -- -- -- -- -- -- HIGH
d7 d0
0x05 LOW
0x06 -- -- -- -- -- -- -- HIGH
d7 d0
0x07 LOW
0x08 -- -- -- -- -- -- -- HIGH
152
d7 d0
0x09
Specifies the attribute file (ATF) number

(0x00 – 0x2C)
0: No change
1: Cancels masking after the data is set.
0: Not specified.
1: The specified attribute file number.
* 0x0A - 0x0F should be filled with 0x00.
153
Command: PAL_TRN (Code: 0x0B)

(Data Transfer using VRAM)
Function: Transfers color data to the system color palette.
d7 d0
0x00 0 1 0 1 1 0 0 1

Command code: 0x0B
* The 4 Kbytes of SGB RAM data immediate following the command is handled as system color palette data and
stored in SUPER NES WRAM as data for system color palettes 000 – 511.
The format of data storage in SGB RAM is as follows.
d7 d0
Byte 1 System Color Palette 000 bit 00 color code LOW
-- System Color Palette 000 bit 00 color code HIGH
System Color Palette 000 bit 01 color code LOW
: : : :
System Color Palette 511 bit 10 color code LOW

System Color Palette 511 bit 10 color code
LOW
-- System Color Palette 511 bit 10 color code

Byte 4096 HIGH
The storage addresses are 0x3000 - 0x3FFF.
154
Command: ATRC_EN (Code: 0x0C)
Function: Enables and disables attraction mode.
Enables and disables attraction on the picture frame.

The default setting is enabled (0x00).
If the command is issued during attraction, attraction is stopped.
d7 d0
0x00 0 1 1 0 0 0 0 1
Command code: 0x0C
d7 d0
0x01 -- -- -- -- -- -- --
0: Enables attraction
1: Disables attraction
Example: Attraction start duration for a model (type without communication connector).
The time required for attraction to start for each picture frame is as follows.
(Times shown in parentheses are times required to start attraction a second time.)
Mario 7 min. (5 min.)
Cork 3 min. (5 min.)
Landscape 1 min. (1 min.)
Cinema 3 mins.
Cats 3 mins.
Pencils 3 mins. (5 mins.)
Escher art 7 mins. (5 mins.)
155
Command: ICON_EN (Code: 0x0E)
Function: Enables and disables the icon function.
d7 d0
0x00 0 1 1 1 0 0 0 1
Command code: 0x0E

d7 d0
0x01 -- -- -- -- --
Color palette
0: Enables use of color palettes internal to the

SBG system program.
1: Disables use of color palettes internal to SBG
system program.
Control settings screen
0: Enable settings
1: Disable settings
SGB register file transfer
0: Receive
1: Do not receive
* The default value is 0x00.
156
Command: DATA_SND (Code: 0x0F)

Function: Transfers data to SUPER NES WRAM using the register file.
d7 d0
0x00 0 1 1 1 1 0 0 1

Command code: 0x0F
d7 d0
0x01
Transfer destination address (LOW)
d7 d0
0x02
Transfer destination address (HIGH)

d7 d0
0x03
Bank number
d7 d0
0x04
Number of data items: 0x1 – 0xB (max)
d7 d0
0x05 * Free Addresses
0x06 Bank 0x00

0x1800 - 0x1FFF
: : : : Data
0x0E Bank 0x7E
0xB000 - 0xBFFF
0x0F
Bank 0x7F
0x0000 - 0xFFFF
157
Command: DATA_TRN (Code: 0x10)

Function: Transfers data in SGB RAM to SUPER NES WRAM.
d7 d0
0x00 1 0 0 0 0 0 0 1
Command code: 10H
d7 d0
0x01
Data transfer address (HIGH)
d7 d0
0x02
Data transfer address (HIGH)
d7 d0
0x03
Bank number
* Free Addresses
Bank 0x00 0x1800 – 0x1FFF

Bank 0x7E 0xB000 – 0xBFFF
Bank 0x7F 0x0000 – 0xFFFF
Note When an SHVC program is tranferred to WRAM and executed, 0x00 should be
written to 0x1700 of bank 00. This can be written either by using DATA_SND or
DATA_TRN or by using the transferred program.
158
Command: MLT_REQ (Code: 0x11)
Function: Requests multiplayer mode.
d7 d0
0x00 1 0 0 0 1 0 0 1
Command code: 11H
d7 d0
0x01 -- -- -- -- -- --
0: No request
1: Request
The game program can use a connector for 2
controllers.
(e.g., standard Controllers and Multiplayer 5)
0: 2 players
1: 4 players
(Multiplayer 5 required)
* The default value is 0x00.
159
Command: JUMP (Code: 0x12)
Function: Sets the SUPER NES program counter to the specified address.
d7 d0
0x00 1 0 0 1 0 0 0 1

Command code: 0x12
d7 d0
0x01
Address (LOW)
d7 d0
0x02
Address (HIGH)
d7 d0
0x03
Bank number
d7 d0
0x04
New NMI vector address (LOW)

d7 d0
0x05
New NMI vector address (HIGH)

d7 d0
0x06
Bank number
Note If all addresses from 0x04 to 0x06 are set to 0, the NMI jumps to the original
vector. NMI is disabled in the system program, so it must be enabled to be used.
160
Command: CHR_TRN (Code: 0x13)

Function: Transfers SUPER NES character format data.
d7 d0
0x00 1 0 0 1 1 0 0 1

Command code: 0x13
0x01 -- -- -- -- -- -- 0
0: Data for characters 0x00 – 0x7F

(BG)
1: Data for characters 0x80 – 0xFF

(BG)
The characters are in 16-color (4-bit) mode.
Note The 4 Kbytes of SGB RAM data immediately following this command is handled
as SUPER NES character data and transferred to SUPER NES VRAM.
The format of the tranferred data is based on the SUPER NES character data
format.
The BG character names are allocated to 0x00 – 0xFF.
When character data is used for the picture frame, characters with a character
name setting of 0x00 should consist of null bits, and all dots of characters with
a name setting of 0x01 should be represented by non-null bits.
161
Command: PCT_TRN (Code: 0x14)

Function: Transfers screen data and color data for picture frames created by the software developer.
d7 d0
1 0 1 0 0 0 0 1
0x00
Command code: 0x14
* The 4 Kbytes of SGB RAM immediately following this command are handled as screen data and transferred to
SUPER NES VRAM.
START
DMG Window
(Number of characters: 1,024)

Picture Frame
There should be 1,024 uncompressed characters of screen data.

The inside of the DMG window should be filled with null characters.
Three color palettes, 4-6, are transferred.
The initial data consists of 2,048 bytes of screen data. This is followed by by 3 palettes of color data (2 bytes x
16 x 3).
The format of the transferred data is based on that of SUPER NES screen and color data. However, the BG
priority bit is set to 0, the color palettes to palette numbers 4-6, the higher-order 2 bits of the character name to
00b, and the characters to 8 x 8-bit mode.
162
Command: ATTR_TRN (Code: 0x15)

Function: Transfers attribute files.
d7 d0
0x00 1 0 1 0 1 0 0 1
Command code: 0x15
* The 4 Kbytes of SGB RAM immediately following this command are transferred to WRAM as attribute files.
(The capacity of each attribute file is 2 x 20 x 18/8 = 90 bytes. Thus, 45 attribute files occupy 4,050 bytes,
0xATF0-0xATF44.
The ATF data format (90 bytes total) -- written horizontally from the left edge of the DMG window.
..
Byte 1 Byte 2 ..
d7,d6 d5,d4 d3,d2 d1,d0 d7,d6 d5,d4 d3,d2 d1,d0 ..
..
Byte 6 Byte 7 ..
d5,d4 d3,d2 d5,d4 d3,d2 ..
d7,d6 d1,d0 d7,d6 d1,d0
..
: : : : : : : :
..
Byte 81 Byte 82 ..
d7,d6 d5,d4 d3,d2 d1,d0 d7,d6 d5,d4 d3,d2 d1,d0 ..
..
Byte 86 Byte 87 ..
..
d7,d6 d5,d4 d3,d2 d1,d0 d7,d6 d5,d4 d3,d2 d1,d0
..
(The figure depicts a DMG window with 20 x 18 characters.)
163
Command: ATTR_SET (Code: 0x16)
Function: Applies the specified attribute file to the DMG window.
d7 d0
0x00 1 0 1 1 0 0 0 1
Command code: 0x16
d7 d0
0x01 --
Specifies the attribute file number.

(0x00 – 0x2C)
0: Not changed
1: Cancel masking after attribute file transfer
* 0x02 - 0x0F filled with 0x00.
164
Command: MASK_EN (Code: 0x17)
Function: Masks the DMG window.
d7 d0
0x00 1 0 1 1 1 0 0 1
Command code: 0x17
d7 d0
0x01 -- -- -- -- -- --
00: Cancels masking
01: Freezes the screen immediately before masking.

(No transfers to SUPER NES VRAM are performed from
after the command is issued until masking is canceled.)
10: Masks by setting all SGB color palette color codes

to black.
11: Masks by setting all SGB color palette color codes

to the same color (color of bit 00).
* 0x2- 0xF filled with 0x00.
Note When masking is performed at the start of the game, it should be performed after
the DMG reset is canceled and around the time that the DMG screen is displayed
on SGB. (The timing of the command should be adjusted so that it is issued after
a wait of several frames.) Without this timing, the screen may be momentarily
be displayed in monochrome.
Note Masking with an argument (0X01) of 0x10 or 0x11 is prohibited during a game.
165
Command: PAL_PRI (Code: 0x19)
Function: Specifies the priority of the color palette for the application and the color palette selected by the player.
d7 d0
0x00 1 1 0 0 1 0 0 1
Command code: 0x19
d7 d0
0x01 -- -- -- -- -- -- -- --
0: Priority to the player-selected color palette

1: Priority to the application color palette
* Default is 0.
Priority to Player-Selected Color Palette

When a screen that uses a player-selected color palette is displayed, any color or attribute settings commands
that were sent have no effect on the DMG window.
Priority to Application Color Palette

When a screen that uses a player-selected color palette is displayed and a color or attribute setting command
was sent, the sent colors are displayed in the DMG window.
* The corresponding commands are as follows.
00, 01, 02, 03, 04, 05, 06, 07, 0A, 16 (Code value)
166
3.3 Cautions Regarding Sending Commands
• After each packet (128 bits) is sent, 0 must always be sent in bit 129.
• If a data sequence covers more than 1 packet, byte 1 of each packet after the first is a continuation of the
data of the previous packet.
• 0x00 is written to the unused areas in each packet.
• Note that there are two modes of data transfer: register-file mode and a mode in which 4 Kbytes are
tranferred using SGB RAM.
• Controller key input should not be read while a command is being sent.
3.4 Sound Flag Summary
• Pre-loaded sound effects A and B can be played simultaneously using system commands.
• The A sound effects are formants, primarily action sounds, and the B sound effects are looping sounds,
primarily ambient sounds.
• The interval (frequency) for these sound effects can be set to 4 levels.
• Changing the interval A allows a completely different sound effect to be obtained with the same sound source.
In addition, the volume can be set to 3 levels.
167
3.4.1 Sound Effect A Flags
SOUND Command
0x01 d7-d0 [bit] 0x03 d1-d0 [bit]
Code Flag Meaning Recommended Voices Used

Interval Value
0x00 Dummy flag for retriggering • • 6 • 7
0x80 Sound effect A stop (mute) • • 6 • 7
0x01 Nintendo d1 = 1 • d0 = 1 • • • 7
0x02 Game over sound d1 = 1 • d0 = 1 • • 6 • 7
0x03 Falling sound d1 = 1 • d0 = 1 • • • 7
0x04 Predetermined sound • • • A d1 = 1 • d0 = 1 • • 6 • 7
0x05 Predetermined sound • • • B d1 = 1 • d0 = 1 • • 6 • 7
0x06 Selected sound • • • A d1 = 1 • d0 = 1 • • 6 • 7
0x07 Selected sound • • • B d1 = 1 • d0 = 1 • • • 7
0x08 Selected sound • • • C d1 = 1 • d0 = 0 • • 6 • 7
0x09 Error sound • • • buzzer d1 = 1 • d0 = 0 • • • 7
0x0A Item-catch sound d1 = 1 • d0 = 0 • • 6 • 7
0x0B One knock on door d1 = 1 • d0 = 0 • • 6 • 7
0x0C Explosion • • • small d1 = 1 • d0 = 1 • • 6 • 7
0x0D Explosion • • • medium d1 = 1 • d0 = 1 • • 6 • 7
0x0E Explosion • • • large d1 = 1 • d0 = 1 • • 6 • 7
0x0F Defeat sound • • • A d1 = 1 • d0 = 1 • • • 7
0x10 Defeat sound • • • B d1 = 1 • d0 = 1 • • 6 • 7
0x11 Striking sound (attack) • • • A d1 = 1 • d0 = 0 • • 6 • 7
0x12 Striking sound (attack) • • • B d1 = 1 • d0 = 0 • • 6 • 7
0x13 Air-sucking sound d1 = 1 • d0 = 0 • • 6 • 7
0x14 Rocket launcher • • • A d1 = 1 • d0 = 1 • • 6 • 7
0x15 Rocket launcher • • • B d1 = 1 • d0 = 1 • • 6 • 7
0x16 Bubbling sound (in water) d1 = 1 • d0 = 0 • • • 7
168
SOUND Command
0x01 d7-d0 [bit] 0x03 d1-d0 [bit]

Recommended
Code Flag Meaning Interval Value Voices Used
0x17 Jump d1 = 1 • d0 = 1 • • • 7
0x18 Fast jump d1 = 1 • d0 = 1 • • • 7
0x19 Jet (rocket) firing d1 = 1 • d0 = 0 • • • 7
0x1A Jet (rocket) landing d1 = 1 • d0 = 0 • • • 7
0x1B Cup breaking d1 = 1 • d0 = 0 • • 6 • 7
0x1C Glass breaking d1 = 1 • d0 = 1 • • 6 • 7
0x1D Level up d1 = 1 • d0 = 0 • • 6 • 7
0x1E Air injection d1 = 1 • d0 = 1 • • • 7
0x1F Sword wielding d1 = 1 • d0 = 1 • • • 7
0x20 Falling in water d1 = 1 • d0 = 0 • • • 7
0x21 Fire d1 = 1 • d0 = 1 • • • 7
0x22 Breaking wall d1 = 1 • d0 = 1 • • 6 • 7
0x23 Cancellation sound d1 = 1 • d0 = 0 • • 6 • 7
0x24 Stepping d1 = 1 • d0 = 1 • • 6 • 7
0x25 Block-hitting sound d1 = 1 • d0 = 1 • • 6 • 7
0x26 Sound of picture floating into view d1 = 1 • d0 = 1 • • 6 • 7
0x27 Screen fade-in d1 = 1 • d0 = 0 • • 6 • 7
0x28 Screen fade-out d1 = 1 • d0 = 0 • • 6 • 7
0x29 Window opening d1 = 1 • d0 = 1 • • 6 • 7
0x2A Window closing d1 = 1 • d0 = 0 • • 6 • 7
0x2B Large laser sound d1 = 1 • d0 = 1 • • 6 • 7
0x2C Sound of stone door closing (opening) d1 = 1 • d0 = 0 • • 6 • 7
0x2D Teleportation d1 = 1 • d0 = 1 • • • 7
0x2E Thunder d1 = 1 • d0 = 0 • • 6 • 7
0x2F Earthquake d1 = 1 • d0 = 0 • • 6 • 7
0x30 Small laser sound d1 = 1 • d0 = 0 • • 6 • 7
169
3.4.2 Sound Effect B Flags
SOUND Command
0x02 d7-d0 [bit] 0x03 d5-d4 [bit]

Recommended
0x00 Dummy flag for retriggering 0• 1 • 4 • 5
0x80 Sound Effects B stop (mute) 0• 1 • 4 • 5
0x01 Applause • • • small crowd d5 = 1 • d4 = 0 • • • 5
0x02 Applause • • • medium crowd d5 = 1 • d4 = 0 • • 4 • 5
0x03 Applause • • • large crowd d5 = 1 • d4 = 0 0• 1 • 4 • 5
0x04 Wind d5 = 0 • d4 = 1 • • 4 • 5
0x05 Rain d5 = 0 • d4 = 1 • • • 5
0x06 Storm d5 = 0 • d4 = 1 • 1 • 4 • 5
0x07 Hurricane d5 = 1 • d4 = 0 0• 1 • 4 • 5
0x08 Thunder d5 = 0 • d4 = 0 • • 4 • 5
0x09 Earthquake d5 = 0 • d4 = 0 • • 4 • 5
0x0A Lava flow d5 = 0 • d4 = 0 • • 4 • 5
0x0B Wave d5 = 0 • d4 = 0 • • • 5
0x0C River d5 = 1 • d4 = 1 • • 4 • 5
0x0D Waterfall d5 = 1 • d4 = 0 • • 4 • 5
0x0E Small character running d5 = 1 • d4 = 1 • • • 5
0x0F Horse galloping d5 = 1 • d4 = 1 • • • 5
0x10 Warning sound d5 = 0 • d4 = 1 • • • 5
0x11 Futuristic car running d5 = 0 • d4 = 0 • • • 5
0x12 Jet flying d5 = 0 • d4 = 1 • • • 5
0x13 UFO flying d5 = 1 • d4 = 0 • • • 5
0x14 Electromagnetic waves d5 = 0 • d4 = 0 • • • 5
0x15 Sound of score being raised d5 = 1 • d4 = 1 • • • 5
170
SOUND Command
0x02 d7-d0 [bit] 0x03 d5-d4 [bit]

Recommended
0x16 Fire d5 = 1 • d4 = 0 • • • 5
0x17 Camera shutter (formant) d5 = 0 • d4 = 0 0 • 1 • 4 • 5
0x18 Writing (formant) d5 = 0 • d4 = 0 • • • 5
0x19 Erasing (formant) d5 = 0 • d4 = 0 • • • 5
0x81 Use prohibited (used by system)
0x82 Use prohibited (used by system)
171
3.4.2 Attributes of A and B Sound Effects
SOUND Command
0x03
d7 d6 d5 d4 d3 d2 d1 d0
× × 0 0 Interval (short)
× × 0 1 Interval (med-short)
A × × 1 0 Interval (med-long)
Sound
Effects × × 1 1 Interval (long)
0 0 × × Volume (high)
0 1 × × Volume (med)
1 0 × × Volume (low)
× × 0 0 Interval (short)
× × 0 1 Interval (med-short)
B
Sound
× × 1 0 Interval (med-long)
Effects
× × 1 1 Interval (long)
0 0 × × Volume (high)
0 1 × × Volume (med)
1 0 × × Volume (low)
1 1 Mute ON
• Mute takes effect only when both bits d2 and d3 are set to 1. If the volume is set for either the A or B sound
effect, mute is turned off.
• Fade-out and fade-in take effect with mute-on and mute-off, respectively. Mute-on and mute-off are
implemented for BGM played by A and B sound effects and by the APU.
• There is no independent mute-off flag.
• When the mute flag is set, the volume and interval data for the A (Port 1) and B (Port 2) sound effects also
should be set.
172
4. MISCELLANEOUS
4.1 Reading Input from Multiple Controllers
After a multiplayer request (Command MLT_REQ) is sent, data from controllers 1, 2, 3, and 4 automatically
become readable.
In 2-player mode, data from controller 1 is read first, followed by data from controller 2, then data from controller 1
again, and so on. In 4-player mode, the order is controller 1, controller 2, controller 3, controller 4, controller 1
again, and so on.
In these cases, the next controller for which data is to be read must be determined beforehand by reading P10-
P13 with P14 and P15 high.
P10 - P13 Next Controller to Read
0xF Controller 1
0xE Controller 2
0xD Controller 3
0xC Controller 4
Note Controller data cannot be read if Multiplayer 5 and SUPER NES Mouse are
connected at the same time.
173
4.2 RECOGNIZING SGB

4.2.1 Distinguishing between Game Boy types (DMG, MGB/MGL, SGB, and SGB2)
The program uses the following methods to determine which of the 4 types is operating.
• Checks the initial value of the internal accumulator of the CPU. (distinguishes between previous/new versions
of CPU).
01 → DMG or SGB
FF → MGB/MGL or SGB2
• Sends a muliplayer request (Command MLT_REQ) and determines whether there is a switch to multiplayer
mode.
No switch → DMG or MGB/MGL

Switch → SGB or SGB2
* The following table summarizes these methods.
Initial Value of CPU Internal Switch/No Switch to Game Boy Type

Accumulator Multiplayer Mode
No switch DMG
01
Switch SGB
No switch MGB/MGL
FF
Switch SGB2
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4.2.2 Usage Example: Distinguishing Between the 4 Game Boy Types
START
Distinguish Between the 4 GB

Types
(See 4.2.1)
DMG
MGB/MGL SGB SGB2
DMG Communication Mode O DMG Communication Mode O DMG Communication Mode O

SGB Competition Mode x SGB Competition Mode x SGB Competition Mode O
* Allowing selection by the user

is desirable.
Main Routine
* A sample program for distinguishing between GB types is provided.
175
4.3 SGB Register Summary
The following registers can be used to perform functions such resetting the SGB CPU from a program transferred
to SUPER NES WRAM and receiving and passing data to a DMG program.
Register File Status Reads the status of the register file

[RFS] 0x6002 (RD)
1:Ready
0: mid-transfer or read finished
DMG Reset Register Resets the SGB CPU
[DRR] 0x6003 (WR)
-- 0 0 -- -- 0 1
0: Reset
1: Cancel
Controller Register1 Writes data from controller 1

[CR1] 0x6004 (WR)
ST SE B A D U L R
Data read at P15...................... Data read at P14
Register File Register file for communication

[RF0 - RFF] 0x7000 - 0x700F (RD)
* The RFS flag (0x6002) is cleared to 0 by the reading

of 0x7000.
The SGB CPU can be reset using DRR.
Using RF0 - RFF and RFS allows data sent to the register file by the DMG program to be received by the SUPER
NES program.
CR1 is a register used by the original SGB system program for writing keypad data from controller 1. The SUPER
NES program can use the controller-reading routine of the DMG program to receive data written to this register.
176
4.4 Flowchart of Initial Settings Routine
177
5. PROGRAMMING CAUTIONS
5.1 ROM Registration Data
To use SGB functions (system commands), the following values must be stored at the ROM addresses indicated.
x146 0x03 and 0x14B 0x33
5.2 Initial Data
When writing programs that use the system commands of SGB and SGB2, use the initialization routine of the
game program to send the following 8 packets of default data to the register file.
INIT1 DEFB $79,$5D,$08,$00,$0B,$8C,$D0,$F4,$60,$00,$00,$00,$00,$00,$00,$00
INIT2 DEFB $79,$52,$08,$00,$0B,$A9,$E7,$9F,$01,$C0,$7E,$E8,$E8,$E8,$E8,$E0
INIT3 DEFB $79,$47,$08,$00,$0B,$C4,$D0,$16,$A5,$CB,$C9,$05,$D0,$10,$A2,$28
INIT4 DEFB $79,$3C,$08,$00,$0B,$F0,$12,$A5,$C9,$C9,$C8,$D0,$1C,$A5,$CA,$C9
INIT5 DEFB $79,$31,$08,$00,$0B,$0C,$A5,$CA,$C9,$7E,$D0,$06,$A5,$CB,$C9,$7E
INIT6 DEFB $79,$26,$08,$00,$0B,$39,$CD,$48,$0C,$D0,$34,$A5,$C9,$C9,$80,$D0
INIT7 DEFB $79,$1B,$08,$00,$0B,$EA,$EA,$EA,$EA,$EA,$A9,$01,$CD,$4F,$0C,$D0
INIT8 DEFB $79,$10,$08,$00,$0B,$4C,$20,$08,$EA,$EA,$EA,$EA,$EA,$60,$EA,$EA
178
5.3 SOU_TRN initial data
When using the SOU_TRN system command, send the following 5 packets of SOU_TRN default data to the
register file before SOU_TRN is used.
STI
DB $79, $00, $09, $00, $0B
DB $AD, $C2, $02, $C9, $09, $D0, $1A, $A9, $01, $8D, $00
ST2
DB $79, $0B, $09, $00, $0B
DB $42, $AF, $DB, $FF, $00, $F0, $05, $20, $73, $C5, $80
ST3
DB $79, $16, $09, $00, $0B
DB $03, $20, $76, $C5, $A9, $31, $8D, $00, $42, $68, $68
ST4
DB $79, $21, $09, $00, $01
DB $60, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
ST5
DB $79, $00, $08, $00, $03
DB $4C, $00, $09, $00, $00, $00, $00, $00, $00, $00, $00
179
180
Chapter 7: Super Game Boy Sound
Chapter 7: Super Game Boy Sound...................................................... 182

1. SGB Sound Program Overview ................................................... 182
2. Memory Mapping (SUPER NES APU) ......................................... 183
3. Creating and Transferring Score Data ........................................ 184
3.1 Transferring Score Data ........................................................................184
3.2 Summary of BGM Flags.........................................................................184
3.3 Overview of Creating Score Data .........................................................185
3.4 Setting the NEWS System Working Environment...............................185
3.5 Setting the Working Environment When Using IS-SOUND ................189
3.6 Score Data Format When Using Original Tools ..................................190
3.7 Cautions Regarding Production of Musical Pieces............................202
3.8 Format of Transferred Data...................................................................203
4. SGB Sound Program Source List ............................................... 205
5. Transferring Audio Data to the Score Area ................................ 208
5.1 Required Data and Procedure for Audio Output.................................208
5.2 Transfer File Example............................................................................209
181
CHAPTER 7: SUPER GAME BOY SOUND
1. SGB SOUND PROGRAM OVERVIEW

The SGB sound program is a special SGB program built into the SGB system program. The sound program is
automatically transferred to the SNES APU at system startup.
Using the SGB system commands, pre-loaded sound effects in the sound program can be used in Game Boy
application programs that support SGB (SGB software).
These commands can be used to set each of the 73 types of pre-loaded sound effects to 4 intervals (playback
frequencies) and 3 volume levels.
Also preloaded are music data for BGM (instruments sound sampling data). This easily allows play of score data
created with Kankichi-kun, the tool for creating SNES scores, and score data for KAN.ASM, the standard driver
that is a software tool for IS-SOUND.
In addition, information on the SGB score data format has been made openly available, allowing those using
tools other than the NEWS system or IS-SOUND to create score data in this format.
182
2. MEMORY MAPPING (SUPER NES APU)
[ APU Addresses ]
183
3. CREATING AND TRANSFERRING SCORE DATA

3.1 Transferring Score Data
BGM can be played with the APU by using the SOU_TRN command to transfer original score data to the
prescribed area of APU RAM. The user area is the 8 Kbytes from 0x2B00 to 0x4AFF.
3.2 Summary of BGM Flags
SOUND Command
0x04 d7-d0 [bit]
Code Flag Description
0x00 Dummy flag for retriggering
0x10
0xF
0x80 BGM stop flag
0xFE Use prohibited (used by system)
0xFF Use prohibited (used by system)
Note If 0x01-0x0F are set without score data being transferred, the BGM built into the
system is played.
This BGM is exclusively for use by the system, so 0x01-0x0F should not be
written as a BGM flag without original score data being transferred.
Even if original score data is transferred, there is risk that the sound program
will run uncontrolled if a non-designated code is written.
Muting is in effect when the system is initialized, so the BGM playback settings
must be made after muting is canceled.
184
3.3 Overview of Creating Score Data
Original BGM can be played with the SGB sound program by transferring score data to the APU using system
commands.
Fifty-seven sounds can be used in BGM, and the score data can be up to just under 8 Kbytes in size.
The method used to create a musical piece is nearly identical to that of the standard SNES.
When the NEWS system is used, score data is created using Kankichi-kun. When IS-SOUND is used, score
data created by an external sequencer are processed through MIDI and converted to create score data
supported by the standard sound driver KAN.ASM.
In addition the SGB score data format has been made openly available, allowing those using original tools to
create score data in this format.
In creating musical pieces, please refer to Section 4, SGB Sound Program Source List, when selecting sounds.
Please do not change the order of these source data.
3.4 Setting the NEWS System Working Environment
185
Working Environment Settings for the NEWS System
1. Rename the current sobox directory.
% mv sobox xxxxx
2. Create a new sobox directory.
% mkdir sobox
* SGB can use only specific sound objects. Thus, special SGB source data must be installed. A sobox directory
for SGB use must be created to prevent loss of previously installed source data files with the same names as the
data files to be installed.
3. Move to the sobox directory.
4. From the installation disk, install soread in this directory.
% tar xvf /dev/rfh0a soread
5. Next install the sampling data files (xxx.so . . . ) in this directory.
% soread
Executing the above command causes the sampling data to be automatically installed.
6. Create a new SGB working directory at any location.
% mkdir #####
7. Move to the SGB working directory.
186
8. From the installation disk, install the following files in the working directory: sgbt.asm, sample.kan,
check.kan, kankichib.hex, and kan.equ.
% tar xvf /dev/rfh0a sgbt.asm sample.kan check.kan kankichib.hex kan.equ
* The organization and address settings in kankichib.hex are as shown below.
* Use the installed kankichib.hex file when starting up mapu.
Item Setting
Kan.equ 0x4c30
Kan.tan 0x04c10
Program start address 0x00400
DIR address 0x04b00
Echo end address 0x0ff00
Sound score start 0x02b00

address
9. Make the following changes in the file .cshrc in the home directory.
--- Following are the Sound Generation Environments Settings ---
Before Change After Change
StartOfKan 0x800 0x400
StartOfDirectory 0x3c00 0x4b00
EndOfDirectory 0x3cff 0x4c0f
StartOfAttribute 0x3e00 0x4c30
StartOfTan 0x3f00 0x4c10
StartOfWave 0x4000 0x4db0
EndOfWave 0xcfff 0xeeff
StartOfFumen 0xd000 0x2b00
10. In the home directory, execute the following command: source .cshrc.
187
Cautions When Using Kankichi-kun
1. Copy sample.kan to a newly created score data file, [score_name].kan.
% cp sample.kan xxx.kan
* This avoids the task of creating a source list in source-list order when using mapu.
2. Start mapu.
% mapu -k
* When starting mapu for the first time, press the NICE reset button.
3. The usable sounds (sources) can be checked with mapu. Selecting check.kan allows the sounds to be
checked in source-list order.
* If data in files such as check.kan are changed, the sounds cannot be checked.
4. To actually create a tune, select xxx.kan.
* Source data (sampling data) that SGB can use have been set in xxx.kan. The source list is shown in Section
4, SGB Sound Program Source List. Note that changing the order of the source list will result in sounds different
from the intended sounds when BGM is played.
5. When producing a musical piece, see Section 3.7, Cautions Regarding Production of Musical Pieces. Refer
to the Kankichi-kun Manual.
6. Finally, convert to the file format described in Section 3.8, Format for Transferred Files.
188
3.5 Setting the Working Environment Using IS-SOUND
Environment Required
• Hardware: IS-SOUND connected to a host computer
• Software: IS-SOUND software tools (installed)
Revisions
1. Portions of the IS-SOUND software tool KAN.EQU were revised as indicated below (older versions only).
Before Revisions After Revisions
cut: equ 122+ 0x80 wav: equ 122+ 0x80

fft: equ 123+ 0x80 sel: equ 123+ 0x80
ply: equ 124+ 0x80 cut: equ 124+ 0x80
wav: equ 125+ 0x80 fft: equ 125+ 0x80
sel: equ 126+ 0x80 ply: equ 126+ 0x80
1. Set Gate Table data to 050 · 101 · 127 · 152 · 178 · 203 · 229 · 252.
2. Set Velocity Table data to 025 · 050 · 076 · 101 · 114 · 127 · 140 · 152 · 165 · 178 · 191 · 203
· 216· 229 · 242 · 252.
Note Sound data (sampling data) are required to check music data using IS-SOUND.
Consequently, a program equivalent to the sound program built into the SGB
hardware (including sound-effect data) and sampling data (sound data) have
been provided in a hex file for MS-DOS. The following briefly describes how to
set up this program and data.
Setting the Working Environment
1. Create an SGB working directory at any location, and move to that directory.
2. Copy sgbsound.hex from the disk to the working directory.
3. Start the debugger shvc.
4. Also start the sound debugger ssnd.
5. Execute r sgbsound.hex to load sgbsound.hex.
6. Execute g400 to run the sound program.
7. Press the HOME button to switch to shvc mode.
8. Execute s2140 to write 01 (from the main program, writes 01 to 0 of the sound port).
189
With this procedure, the pre-loaded source data (sampling data) are played in the order shown in Section 4 of
this chapter, SGB Sound Program Source List.
After the data is transferred once, only the score data needs to be transferred to allow music to be checked
again.
Cautions
1. Score data is the data defined in KAN.ASM Version 1.21 as being located from GFT onward. For
information on all items related to converting data from other sequencers to score data, formats, and tool
usage, see the IS-SOUND manual.
2. Set the source data number according to the source list.
3. Set the starting address of the score data to 0x2B00.
4. When producing a musical piece, do so in accordance with Section 3.7, Cautions Regarding Production of
Musical Pieces.
5. Convert to the file format described in Section 3.8, Format for Transferred Files.
3.6 Score Data Format When Using Original Tools
The score data format has been made openly available for the benefit of those using original development tools.
Data that is not in this format will not operate on SGB.
Note that in some cases, program control may be lost.
Score Data
Glossary of Terms
gft Location of tune table definitions (collection of tune label

definitions). Up to 15 tunes can be defined. The order
defined here corresponds to the flag set for port 0 (0x01-
0x0F).
Tune label A label name applied to each tune.
Block A unit several bars long that each tune is divided into.
Parts The channels that make up each block (maximum of 8

parts).
Performance data The aggregate of the score data played by the parts. The
parts in the channels must all be the same length
(number of steps) in a given block.
190
Overall Format of Score Data
Example 1
* Area inside dotted frame = Data table for 1 tune
org 02b00H ; (a) Starting address of score data

gft: ; (b) Tune table
dw bgm1,bgm2, ··· ; Indicate the tune labels
bgm1: ; (c) Tune label 1

dw bgm1_block1 ; (d) Block 01
bgm1 0:
dw 255 ; (e) Repetition code (endless)
dw bgm1_0 ; (e) Repetition starting address
dw 000 ; (f) Tune label end code
;
bgm1_block1: ; (g) Block 01
dw bgm1_block1_0 ; (g) Starting address of Part 0
dw 00 ; (g) Part 4 unused
bgm1 block2:
· · ; (g) Same in Block 2
· ·
bgm1 block3:
· · ; (g) Same in Block 3
· ·
bgm1 block1_0: ; Block 01 (h) Part 0 performance data
db tp1,049,mv1,200,sno,$1a,pv1,180,pan,010
db ecv,255,040,040,edl,002,090,002,tun,050
db 012,P99+V99,c30,d30,e30,f30,024,g30,kyu
db 00 ; (h) Part end code
bgm1 block1_1: ; (h) Part 1 performance data
db sno,$1b,pv1,140,pan,008,tun,030
db 096,P99+V99,g20
db 096,P99+V99,e20
db 096,P99+V99,c20
Continued on next page
191
bgm1 block2_0: Block 02 (h) Part 0 performance data

db sno,$1a,pv1,200,pan,012,tun,050
db • • • • • • • • • • • • • • • • • •
db 00
•
bgm1 block3_0: Block03 (h) Part 0 performance data
db sno,$1a,pv1,200,pan,012,tun,050
db • • • • • • • • • • • • • • • • • •
db 00
•
192
Description of Example 1
(a) The score data map to memory addresses 0x2B00-0x4AFF in the APU.
If this area is exceeded, a portion of the sound program will be destroyed.
(b) gft: is the starting address of the entire tune table.

dw, bgm1, and bgm2... are the tune labels and the starting addresses of the score data items.
(c) The tune label.

The order in which the blocks are played is defined following the tune label.
The dotted frame encloses the data for one tune, bgm1.
(d) Data for each block.
(e) 0x01-0x7F (01-127) is the number of loops (repetitions); 0x82-0xFF (130-255) is an endless loop.
If repetition is not needed, set the end code (0x00) instead of a loop code.
(f) Block definition end code.
(g) Location where the parts of each block are indicated and the part labels are defined.
Defines the part labels for parts 0, 1, 2, . . . 7 in ascending order from top to bottom. 0x00 should be written for
unused parts. Even if some parts are unused, always define 8 parts.
(h) The performance data for each part.
Play Data Overview
Parameters such as temp, volume, pan, source number, echo, velocity, interval, and sound length are set here.
For specific descriptions, see Section 3.6.4, Code Summaries.
First set are the effects parameters – such as main volume, ramp, and echo – for Part 0 of the first block. Once
these are set, they need not be set again (for other blocks or parts) as long as they are not changed.
Next the parameters such as part volume, pan, source number, and tuning are set for each part.
Then the sound length, velocity + gate time, and interval are set in that order. Be careful to ensure that sound
length is always set first, followed by velocity + gate item, then the interval.
If the next sound is the same as the previous sound, the sound length, velocity, and gate time need not be set
again.
Finally, a data end code of 00 is set for Part 0 of each block.
Settings for parts 1-7 are not required.
The lower parts and blocks are set in the same manner.
193
Code Summaries
a) Length Data (step time)

This is the length (step time) to the subsequent sound; it corresponds to the length of the sound envelope.
The code corresponding to each sound envelope is shown in the following table. Please use the appropriate
code in the settings.
Note Length Code Note Length Code Note Length Code
6 18 48
Sixteenth note Dotted eighth Half note
note
9 24 72
Dotted Quarter note Dotted half note
sixteenth note
12 36 96
Eighth note Dotted quarter Whole note
note
Note For triplets and thirty-second notes, convert using the above values.
194
(b) Velocity (volume) + gate time

Velocity expresses the volume as a percentage. Here it can be set to 16 levels using the lower-order 4 bits
(d0 – d3).
Gate time expresses as a percentage the length that the sound is actually emitted. It can be set to 8 levels
using the higher-order 3 bits (d4 – d6).
Changing these values provides legato and staccato effects.
The following table lists the values defined by the SGB sound driver.
The settings are designated using the codes for the listed velocities (VELOCITY) and gate times
(GATE_TIME).
Symbol Code d7 d6 d5 d4 d3 d2 d1 d0 Rate
V10 0x00 x x x x 0 0 0 VELOCITY=010%

V20 0x01 0 VELOCITY=020%
V30 0x02 x x x x 0 0 0 VELOCITY=030%
V45 0x04 x x x x 0 0 1 VELOCITY=045%
V55 0x06 x x x x 0 0 1 VELOCITY=055%
V65 0x08 x x x x 0 1 0 VELOCITY=065%
V75 0x0A x x x x 0 1 0 VELOCITY=075%
V80 0x0B 1 VELOCITY=080%
V85 0x0C x x x x 0 1 1 VELOCITY=085%
V90 0x0D 0 VELOCITY=090%
V95 0x0E x x x x 0 1 1 VELOCITY=095%
V99 0x0F 1 VELOCITY=099%
x x x x 1 0 0
P20 0x00 x 0 0 0 x x x GATE_TIME=020%
P40 0x10 x GATE_TIME=040%
P50 0x20 x 0 0 1 x x x GATE_TIME=050%
P70 0x40 x 0 1 0 x x x GATE_TIME=070%
P90 0x60 x 0 1 1 x x x GATE_TIME=090%
x 1 0 0 x x x
Symbol input example: P99+V99 Code input example: 0x70+ 0x0F
*When setting score data using symbols, assemble after defining the equal statement according to the table
above.
195
c) Interval Data
Intervals for 6 octaves can be set here.
Depending on the sound, however, high sounds may not be heard.
The following table shows the correspondence between code settings and intervals. Please refer to this
table when setting an interval.
*Interval symbols: 0x01- 0xB50

Codes: 0x81-0xC7 (tie = 0xC8 · rest = 0xC9)
*When score data is set using symbols, assemble after defining the equals statement.
Octave 0 Octave 1 Octave 2 Octave 3
Interval Code Interval Code Interval Code Interval Code
C10 0x8C C20 0x98 C30 0xA4
C01 0x81 C11 0x8D C21 0x99 C31 0xA5
D00 0x82 D10 0x8E D20 0x9A D30 0xA6
D01 0x83 D11 0x8F D21 0x9B D31 0xA7
E00 0x84 E10 0x90 E20 0x9C E30 0xA8
F00 0x85 F10 0x91 F20 0x9D F30 0xA9
F01 0x86 F11 0x92 F21 0x9E F31 0xAA
G00 0x87 G10 0x93 G20 0x9F G30 0xAB
G01 0x88 G11 0x94 G21 0xA0 G31 0xAC
A00 0x89 A10 0x95 A20 0xA1 A30 0xAD
A01 0x8A A11 0x96 A21 0xA2 A31 0xAE
B00 0x8B B10 0x97 B20 0xA3 B30 0xAF
196
Octave 4 Octave 5 Misc.
Interval Code Interval Code Tie TIE 0xC8
C40 0xB0 C50 0xBC Rest KYU 0xC9
C41 0xB1 C51 0xBD
D40 0xB2 D50 0xBE
D41 0xB3 D51 0xBF
E40 0xB4 E50 0xC0
F40 0xB5 F50 0xC1
F41 0xB6 F51 0xC2
G40 0xB7 G50 0xC3
G41 0xB8 G51 0xC4
A40 0xB9 A50 0xC5
A41 0xBA A51 0xC6
B40 0xBB B50 0xC7
Note 1: A value of 1 in the right-most position of the interval symbol indicates a .
A is represented as the of one interval lower.
Example: C01=C for interval 0.
Note 2: When specifying a tie, first set the step time (length) and velocity + gate time. (This can be skipped if
unchanged from the previous sound.)
A tie cannot be used at the start of a block.
Note 3: When specifying KYU (a rest), first set the step time (length). (This can be skipped if unchanged from
the previous sound.)
Settings Example:
Length Gt & Vel Interval Code
db 024, P99+V99, C30 ;(0x0A4) for specifying an interval
Length Gt & Vel Tie Code
db 048, P90+V95, TIE ;(0x0C8) for specifying a tie
Length Rest Code
db 096 KYU ;(0x0C9) for specifying a rest
197
d) Special Symbols
The special symbols represent special data for implementing a variety of special effects. These include
sound change, crescendo, panpot change, vibrato, tremolo, and echo. Each symbol has its own parameters.
The following table lists these special symbols, their parameters, and the valid values for these
parameters.
I Special Symbols Summary No. 1
Symbol First Argument Second Third Argument Function

Code (range) Argument(range) (range)
sno SOURCE NAME Sound change

($E0) 0 ≤ X ≤ 127
pan Pan value Panpot (0=L/20=R/10=C)

($E1) 0 ≤ X ≤ 20 (10 = default)
pam No. of steps Pan value Move panpot

($E2) 1 ≤ X ≤ 255 0 ≤ Y ≤ 20 (Y takes effect after X steps)
vib No. of hold steps Rate Depth Vibrato (no. of hold steps is the time
($E3) 0 ≤ X ≤ 255 1 ≤ Y ≤ 255 1 ≤ Z ≤ 255 till vibrato takes effect)
vof Vibrato off

($E4)
mv1 Volume Main volume

($E5) 0 ≤ X ≤ 255 (192 = Default value)
mv2 No. of Steps Volume Move main volume

($E6) 1 ≤ X ≤ 255 0 ≤ Y ≤ 255 (used for crescendo/decrescendo)
(Y takes effect after X steps)
tp1 Rate Tempo

($E7) 1 ≤ X ≤ 82 See Note 1.
tp2 No. of steps Rate Move tempo

($E8) 1 ≤ X ≤ 255 1 ≤ Y ≤ 82 (Used for retardando/accelerando)
(Y takes effect after X steps)
Main key transpose

ktp Transposition level
(1= semitone up/-1= semitone down)
($E9) $E8≤F≤$FF(– value)
– is the two’s complement
$00≤X≤$18
ptp Transposition level Part key transpose

($EA) $E8≤X≤$FF(– value) (1= semitone up/-1= semitone down)
$00≤X≤$18 – is the two’s complement
198
I Special Symbols Summary No. 2
Symbol First Argument Second Argument Third Argument Function

Code (range) (range) (range)
tre No. of hold steps Rate Depth Tremelo (no. of hold steps is the
($EB) 0 ≤ X ≤ 255 1 ≤ Y ≤ 255 1 ≤ Z ≤ 255 time till tremelo takes effect)
tof Tremelo off

($EC)
pv1 Volume Part volume

($ED) 0 ≤ X ≤ 255 (192=Default value)
pv2 No. of steps Volume Move part volume

($EE) 1 ≤ X ≤ 255 0 ≤ Y ≤ 255 (Used for crescendo/decrescendo)
(Y takes effect after X steps.)
pat PAT ADRS(L) PAT ADRS(H) REPEAT PAT Pattern data subroutine
($EF) $00 ≤ X ≤ $FF $00 ≤ Y ≤ $FF 1 ≤ Z ≤ 255 Seen Note 2.
vch No. of steps Vibrato deepens gradually over X

($F0) 1 ≤ X ≤ 255 number of steps
swk No. of hold steps No. of steps Amount of change Start sweep from next sound
($F1) 0 ≤ X ≤ 255 1 ≤ Y ≤ 255 $DC ≤ Z ≤ $FF(– value)
– is the two’s complement
$00 ≤ Z ≤ $24
sws No. of hold steps No. of steps Amount of change Start sweep heading into next sound
($F2) 0 ≤ X ≤ 255 1 ≤ Y ≤ 255 $DC ≤ Z ≤ $FF(– value– is the two’s complement
$00 ≤ Z ≤ $24
sof Sweep off

($F3)
Amount of
tun Tune
change
($F4) (Semitone up with 255)
0 ≤ X ≤ 255
ecv ECHO CHANNEL ECHO-VOL(L) ECHO-VOL(R) Echo volume

($F5) 0 ≤ X ≤ 255 0 ≤ Y ≤ 255 0 ≤ Z ≤ 255 Seen Note 3.
eof Echo off

($F6)
edl ECHO TIME FEED BACK FILTER No. Echo delay

($F7) 1 ≤ X ≤ 15 $9D ≤ Y ≤ $FF(– value) 0 ≤ Z ≤ 10 See Note 4.
$00 ≤ Y ≤ $7F – is the two’s complement
ev2 No. of steps ECHO-VOL(L) ECHO-VOL(R) Move echo volume

($F8) 1≤X≤255 0≤Y≤255 0 ≤ Z ≤ 255 (YZ values take effect after X steps)
199
Symbol First Argument Second Argument Third Argument Function

Code (range) (range) (range)
Sweep (once)
swp No. of hold steps No. of steps SWEEP value
The interval takes effect after the specified
($F9) 0 ≤ X ≤ 255 1 ≤ Y ≤ 255 interval
number of hold steps.
Note 1: The tempo values set by the program data and the actual (musical piece) tempos that correspond to
those values are as follows.
Please refer to this table to make the conversions.
Music Tempo Driver Tempo Music Tempo Driver Tempo
Quarter note = 400 82 Quarter note = 120 25
Quarter note = 30 62 Quarter note = 60 12
Quarter note = 24 49 Quarter note= 30 6
Note 2: Used when the same performance data is repeated (for data compression). Following the pat code, the
L and H addresses and the repetition frequency for the performance data is set. The performance data at the
addresses specified by pat are then read. The data is played the number of times specified by the repetition
frequency. The performance data at the locations specified by pat require an end code of 0x00.
Note 3: When applying echo, ecv and edl are required. The value entered for the echo channel is 1 for echo
used in Part 0, 2 for Part 1, 4 for Part 2, 8 for Part 3, 16 for Part 4, 32 for Part 5, 64 for Part 6, and 128 for Part
7. When echo is used for multiple parts, enter the sum of the channel number values.
Examples
When echo is used for parts 0 and 1, the value entered is 3.

When echo is used for all parts, the value entered is 255.
Note 4: Echo time is the delay duration. It uses RAM area equal to twice the echo time value, expressed in
Kbytes. The echo area in SGB is 4 Kbytes, so a value of 2 or less should be entered. Feedback indicates the
amount of delay returned. Filter No. indicates the type of filter applied to the delayed sound.
0 = no filter; 1 = high-pass filter; 2 = low-pass filter; 3 = band-pass filter
*The symbols marked with a I in the Special Symbols table are applied to all parts. These should be set in the
first part.
*When using a symbol to set a special symbol for score data, assemble after defining the equals statement
according to the Special Symbols table.
*The special symbols and the arguments that follow should be set in the order shown in the tables.
*If using IS-SOUND, load sgbsound.hex according to the steps in Section 3.5, Setting the Working Environment
for IS-SOUND. Transferring the subsequently created score data allows the tunes and sounds to be checked.
200
Cautions
1. The starting address for score data should be set to 0x2B00.
2. Source numbers should be set according to the source list.
3. Musical pieces should be produced according to the instructions in Section 3.7, Cautions Regarding
Production of Musical Pieces.
4. Convert to the file format described in Section 3.8, Format for Transferred Files.
Summary of Play Data Codes
0x00 Part end code
0x10-0x7F Note/rest length data & VELOCITY (volume) + GATE_TIME
0x80-0xC7 Interval (sound length) data (C00-B50) * C01-B50 in SGB
0xC8 Tie (TIE)
0xC9 Rest (KYU)
0xCA-0xDF Use prohibited
0xE0-0xF9 Special symbols
0xFA-0xFF Use prohibited
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3.7 Cautions Regarding Production of Musical Pieces
The echo parameters set in BGM are applied in the same manner for the A and B sound effects.
This is because echo is applied equally to all 8 channels. The parameters have been tuned so
that they can also be used with BGM, so please note this when resetting the parameters.
Score Data Settings

Special
Echo Channel Echo Volume L Echo Volume R
Symbol
ecv ΟΟΟ (Note 1) 40 40
Special
Echo Time Feed Back Filter No.
Symbol
edl 2 (Note 2) 90 2
If echo is not used, specify e o f (special symbol) instead of e c v.
If a value greater than 2 is specified for Echo Time, the sampling data will be destroyed. Up to 15
tunes can be registered (0x01-0x0F). Channels 2 and 3 are allocated for BGM, so these channels
should be used for regular playback of BGM parts.
Microtuning of source data used for notes should be specified using the tun code with the score
data. For tuning values, refer to the recommended tunings in Section 4 of this chapter, SGB
Sound Program Source List (except for percussion instruments).
The recommended tuning values for this source list are based on an interval of C30 (See Section
3.6.4, Interval Data).
Also indicated for each source data item is the score data setting (interval code) for producing
sounds with a C30 interval. Please refer to these settings in inputting score data.
In high and low areas, the tuning of some source data may be somewhat off. Whenever this
occurs, the tuning value must be modified.
For SGB, all tunings are set 50 cents higher than the standard value (A = 440 Hz).
202
3.8 Format of Transferred Data
When Using NEWS
1. Copy s g b t. a s m to a new transfer file, filename.asm.
% cp sgbt.asm yyy.asm
* When making transfer files, create them based on sgbt.asm.
2. Open yyy.asm and modify it as follows.
Line No. Before Changed After Changed
113 gft : 02b00H gft : yyy$, · · · · · · · ·

; ;
115 ; include xxx.dat include yyy.dat
· · · · · ·· · · · ·
* When adding multiple tunes, add them beginning from line 113. Also increase the number of ‘include
ΟΟΟ.dat’ statements after line 115 by the number of tunes.
3. Execute the following command: asm700 yyy.asm.
The above completes creation of the yyy.hex transfer file.
4. Convert the yyy.hex file completed in Step 3 to the format used by the SNES sound generator.
Converting to binary data:
% cat h2b -start 400 -b > yyy.bin

yyy.hex
Converting to hexadecimal data:
% cat h2b -start 400 > ΟΟΟ.asm

yyy.hex
When Using IS-SOUND or Original Tools
The score data file to be transferred is converted to the format used by the sound boot program.
Example:
dw $0030 ; Number of data items to transfer
dw $2b00 ; Transfer destination address
db $00,$01,$02,$03,$04,$05,$06,$07 ; Score data
db $08,$09,$0a,$0b,$0c,$0d,$0e,$0f ; Score data
db $00,$01,$02,$03,$04,$05,$06,$07 ; Score data
db $08,$09,$0a,$0b,$0c,$0d,$0e,$0f ; Score data
db $00,$01,$02,$03,$04,$05,$06,$07 ; Score data
db $00,$01,$02,$03,$04,$05,$06,$07 ; Score data
dw $0000 ; Transfer end code
dw $0400 ; Program start address
203
The number of data items to transfer (2 bytes) and the transfer destination address (2 bytes) are placed at the
starting address of the score data. (Be careful to ensure that the data in this order.)
Finally, the transfer end code (2 bytes) and the program starting address are added. (Be careful to ensure that
the data is in this order.) The transfer end code is $0000.
Cautions Regarding Data Transfer
In SGB, the transfer destination address is $2b00, and the program starting address is $0400. Please be sure to
use the correct addresses, or program control will be lost.
The area used for the transferred score data is approximately 8 Kbytes. A data overflow will destroy the directory.
If the data exceed 4 Kbytes, divide them into 2 files.
Transfer of score data is completely executed using system commands.
204
4. SGB SOUND PROGRAM SOURCE LIST
Kankichi- Envelope Type Recommended

so No. kun so so Name Sound Family /Specific Sound Tuning Interval
No.
0x000 sn0 +d0.so Normal envelope
0x001 sn1 +Dch.so Envelope with extremely short decay
0x002 sn2 +d1.so Electric keyboard envelope
0x003 sn3 +d2.so Sine Family Brass envelope
0x004 sn4 +d3.so Pedal organ envelope
0x005 sn5 +d5.so Banjo envelope
0x006 sn6 +d9.so ’Soft’ envelope
0x007 sn7 sin.so Normal sine wave
0x008 sn8 +d5.so Banjo envelope t u n, 0 1 3
0x009 sn9 +d6.so Bass envelope t u n, 0 1 3

Bass Family 1
0x 00a s10 +d8.so Fretless bass envelope t u n, 0 1 3
0x 00b s11 B1.so Bass 1 t u n, 0 1 3
0x00c s12 +d5.so Banjo envelope t u n, 0 2 0
0x00d s13 +d6.so Bass envelope t u n, 0 2 0

Bass Family 2
0x00e s14 +d9.so ‘Soft’ envelope t u n, 0 2 0
0x00f s15 B2.so Bass 2 t u n, 0 2 0
0x010 s16 +d3.so Pedal organ envelope t u n, 0 4 0
0x011 s17 +d5.so Banjo envelope t u n, 0 4 0

Guitar Family
0x012 s18 +Dch.so Envelope with extremely short decay t u n, 0 4 0
0x013 s19 acg.so Guitar t u n, 0 4 0
0x014 s20 +d1.so Electric keyboard envelope
0x015 s21 +d3.so Pedal organ envelope

Electric Keyboard
0x016 s22 ep.so Family 1 Electric keyboard 1
0x017 s23 ep2.so Electric keyboard 1 t u n, 0 0 3 C20
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Kankichi- Envelope Type/ Recommended

so No. kun so Name Sound Family Specific Sound Tuning Interval
so No.
0x019 s25 +d3.so Electric Keyboard Pedal organ envelope

Family 2
0x01a s26 epf.so Electric keyboard, soft type
0x01b s27 pipe.so Organ Family Pipe organ
0x01c s28 +d8.so Fretless bass envelope t u n, 0 8 0 C20
0x01d s29 +d4.so Strings Family Strings envelope t u n, 0 8 0 C20
0x01e s30 S1.so Strings t u n, 0 8 0 C20
0x01f s31 +d9.so ‘Soft’ envelope t u n, 1 7 0 B00

Chorus Family 1
0x020 s32 cho1.so Chorus 1 t u n, 1 7 0 B00
0x021 s33 +d3.so Pedal organ envelope t u n, 1 6 5 B10

Chorus Family 2
0x022 s34 cho2.so Chorus 2 t u n, 1 6 5 B10
0x023 s35 +Dch.so Xylophone t u n, 0 5 5
0x024 s36 +d1.so Electric keyboard envelope t u n, 0 5 5

Xylophone Family
0x025 s37 +d9.so ‘Soft’ envelope t u n, 0 5 5
0x026 s38 Dxlp.so Xylophone + looping sound t u n, 0 5 5

Brass Family 1
0x028 s40 brs.so Brass 1
0x029 s41 brs8.so Brass Family 2 Brass 2 t u n, 0 2 0 C20
0x02a s42 +Dch.so Envelope with extremely short decay t u n, 0 4 0 C20
0x02b s43 +d5.so Banjo envelope t u n, 0 4 0 C20

Trumpet Family
0x02c s44 +d9.so ‘Soft’ envelope t u n, 0 4 0 C20
0x02d s45 tp3.so Trumpet t u n, 0 4 0 C20
0x02e s46 +d4.so Strings envelope

Bassoon Family
0x02f s47 fg.so Bassoon
0x030 s48 fl.so Flute Family Flute t u n, 0 5 3 C20
206
Envelope Type Recommended

so No. Kankich so Name Sound Family Specific Sounds Tuning Interval
i-kun
0x031 s49 Db.so Bass drum
0x032 s50 +Dch.so Percussion Closed high-hat

Instrument
0x033 s51 Doh.so Family Open high-hat
0x034 s52 sdr3.so Snare 1
0x035 s53 Ds.so Snare 2

Percussion Family
0x036 s54 Dt.so Tom (for stepping down) t u n, 0 1 0
0x037 s55 clp.so SE Family Hand clap
0x038 s56 jet2.so SE Family Jet
* The following (0x39-0x3E) can be used with Kankichi-kun.
0x039 jet1.so Jet
0x03a noiz.so Noise
0x03b glas.so Glass breaking
0x03c shot.so Shot
0x03d river.so River flowing
0x03e wind.so Wind blowing
Settings for source data numbers 0x39-0x3E cannot be specified on Kankichi-kun. These source data can be
used only with sound effects. However, they can be set using tools other than Kankichi-kun.
The shaded portions are the basic source data. The other source data items are the basic source data with
modified envelopes.
The contents of the source list are also listed in the README file located in the sobox directory installed for
NEWS.
The recommended tuning values in the source list are based on an interval of C30. (See Section 3.6.4, Interval
Data.) With high- and low-pass filtering, the tuning of some source data may be somewhat off. Whenever this
occurs, the tuning value must be modified.
The interval value is the score data setting (interval code) for producing sounds with a C30 interval. For SGB,
all tunings are set 50 cents higher than the standard value (A = 440 Hz). The source data items in the empty
areas do not require tuning. (In addition, they can be used without changing the interval).
207
5. TRANSFERRING AUDIO DATA TO THE SCORE AREA

In general, the score area (8 K) is provided for transferring only score data. However, audio data also can be
transferred for output. Audio data can be transferred only if the following conditions are met.
• The data must not exceed the score area (8 K).
• The data is not transferred to areas other than the score area (except for the Directory and sod
data).
If the data is transferred to other areas, the sound effects used by the system may no longer play or may be
altered (strange sounds). Transferring data to other areas may also lead to a loss of program control. Therefore,
please be certain to ensure that the above two conditions are met.
5.1 Required Data and Procedure for Audio Output
1. Sampling data (multiple data items permitted)
2. Score data (score used to play sampling data)
* 1 and 2 combined must occupy less than 8 Kbytes.
* The sound numbers ( so No.) corresponding to the sampling data should be from among one of
the following.
002H,003H,004H & 00CH,00DH,00EH & 02AH,02BH,02CH (hex No.)
Note All numbers other than the above are used for system sound effects or music.
Therefore, be careful to use only the above numbers.
3. Directory and sod data corresponding to the sampling data:
* Directory and sod data are provided for each sound (so No.).
No. of
Start Address Data Structure
Bytes
Directory 0x4B00 Source start address (L)/(H) · Source loop(end)address(L)/(H) 4 bytes
sod 0x4C30 so No./ adsr(1)/adsr(2)/gain/blk No.(2byte) 6 bytes
When the sound number is 0x000, the directory data comprise 4 bytes beginning at 0x4B00, and the sod data
comprise 6 bytes beginning at 0x4C30 (0x000 cannot be used).
Please substitute the directory data and sod data values corresponding to the given sound number.
Note For the sound number, however, be careful not to use any number other those
shown in 2. Use of an incorrect number will cause a loss of program control.
Transferring all of these data and issuing a BGB request will result in audio playback.
208
5.2 Transfer File Example
With sampling data consisting of a single sound with a sound number of 0x002, the Directory data would be the
4 bytes beginning at 0x4B08, and the sod data would occupy the 6 bytes beginning at 0x4C3C. In this case,
ensure that the score data begin at 0x2B00. Starting these data at any location other than 0x2B00 would cause
a loss of program control. The sampling data (audio data) should be transferred to the area between 0x2B00 and
0x3AFF.
dw $0004 ; No. of data items to transfer for Directory

dw $4B08 ; Directory transfer destination address
db $00,$30,$3F,$30 ; Directory data (4 bytes)
;
dw $0006 ; No. of data items to transfer for sod
dw $4C3C ; Sod transfer destination address
db $02,$FF,$E0,$B8,$02,$B0 ; Sod data (6 bytes)
;
dw $0020 ; No. of score data items to transfer
dw $2B00 ; Score data transfer destination address
db $00,$01,$02,$03,$04,$05,&06,$07 ; Score data
db $00,$01,$02,$03,$04,$05,&06,$07 ; Score data
db $00,$01,$02,$03,$04,$05,&06,$07 ; Score data
db $00,$01,$02,$03,$04,$05,&06,$07 ; Score data
;
dw $0040 ; No. of sampling data items to transfer
dw $3000 ; Sampling data transfer destination address
db $00,$01,$02,$03,$04,$05,&06,$07 ; Sampling data
db $00,$01,$02,$03,$04,$05,&06,$07 ; Sampling data
db $00,$01,$02,$03,$04,$05,&06,$07 ; Sampling data
db $00,$01,$02,$03,$04,$05,&06,$07 ; Sampling data
db $00,$01,$02,$03,$04,$05,&06,$07 ; Sampling data
db $00,$01,$02,$03,$04,$05,&06,$07 ; Sampling data
db $00,$01,$02,$03,$04,$05,&06,$07 ; Sampling data
db $00,$01,$02,$03,$04,$05,&06,$07 ; Sampling data
;
dw $0000 ; Transfer end code
dw $0400 ; Program start address
When using multiple sampling data items, also transfer the Directory and sod data specified for each item in Step 2.
Note Be careful not to rewrite the Directory and sod data used by the system.
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THIS PAGE WAS INTENTIONALLY LEFT BLANK
210
Chapter 8: Game Boy Memory Controllers (MBC)
Chapter 8: Game Boy Memory Controllers (MBC) ..............212

1. MBC1.............................................................................................. 212
1.1 Overview..................................................................................................212
1.2 Description of Registers ........................................................................212
1.3 Memory Map............................................................................................214
2. MBC2.............................................................................................. 215
2.1 Overview..................................................................................................215
2.3 Memory Map............................................................................................215
2.4 Backup RAM............................................................................................215
3. MBC3.............................................................................................. 216
3.1 Overview..................................................................................................216
3.3 Accessing the Clock Counters ..............................................................217
3.4 Memory Map............................................................................................218
3.5 Programming Items to Note...................................................................219
4. MBC5.............................................................................................. 221
4.1 Overview..................................................................................................221
4.2 Registers .................................................................................................221
4.3 Memory Map............................................................................................221
4.5 Programming Cautions ..........................................................................223
4.6 Examples of MBC5 programs on DMG and CGB .................................224
5. MBC5 (with rumble feature)........................................................ 225
5.1 Overview..................................................................................................225
5.2 Registers .................................................................................................225
5.3 Memory Map............................................................................................226
5.5 Motor Control ..........................................................................................228
5.6 Programming Cautions ..........................................................................229
5.7 Physical Effects of Vibration on the Body ............................................230
211
CHAPTER 8: GAME BOY MEMORY CONTROLLERS (MBC)

1. MBC1
1.1 Overview
MBC1 is a memory controller that enables the use of 512 Kbits (64 Kbytes) or more of ROM and 256 Kbits
(32 Kbytes) of RAM. It can be used as follows.
♦ To control up to 4 Mbits of ROM

When used to control up to 4 Mbits (512 Kbytes) of ROM, MBC1 can control up to 256 Kbits (32
Kbytes) of RAM.
♦ To control 8 Mbits or more of ROM

When MBC1 is used to control up to 8 MBits (1 MB) or 16 MBits (2 MB) of ROM, the following
conditions apply
♦ When used to control 8 MBits of ROM

MCB cannot use ROM addresses 0x080000-0x083FFF (Bank 0x20)
♦ When used to control 16 MBits of ROM

0x8000-0x083FFF (Bank 0x20)
MBC1 cannot use ROM Addresses x100000-0x103FFF (Bank 0x40)
0x180000-0x183FFF (Bank 0x60)
RAM use by MBC1 is restricted to 64 Kbits (8 Kbytes).
1.2 Description of Registers
♦ Register 0: RAMCS gate data (serves as write-protection for RAM)

Write addresses: 0x0000-0x1FFF Write data: 0x0A
Writing 0x0A to 0x0-0x1FFF causes the CS to be output, allowing access to RAM.
♦ Register 1: ROM bank code

Write addresses: 0x2000-0x3FFF Write data: 0x01-0x1F
The ROM bank can be selected.
♦ Register 2: Upper ROM bank code when using 8 Mbits or more of ROM (and register 3 is 0)
Write addresses: 0x4000-0x5FFF Write data: 0-3
The upper ROM banks can be selected in 512-Kbyte increments.
Write value of 0 selects banks 0x01-0x1F
: RAM bank code when using 256 Kbits of RAM (and register 3 is 1)

The RAM bank can be selected in 8-Kbyte increments.
212
♦ Register 3: ROM/RAM change

Write addresses: 0x6000-0x7FFF Write Data: 0-1
Writing 0 causes the register 2 output to control switching of the higher ROM bank.
Writing 1 causes the register 2 output to control switching of the RAM bank.
213
1.3 Memory Map
♦ When Used to Control up to 4 Mbits of ROM
RAM Address CPU Address ROM Address

0x7FFF 7FFFFH
DFFFH
Bank 3 Internal Bank 0x1F
Working
0x6000
RAM
Bank 2 C000H Bank 0x1E
External
0x4000
Expansion
Bank 1
Working
: :
0x2000 A000H RAM : :
Bank 0 : :
0x0000 Display
RAM
Bank 6
8000H 0x18000
Bank 5
Program 0x14000
Switching Bank 4
Area 0x10000
Bank 3
4000H
0x0C000
Bank 2
Program 0x08000
Residence Bank 1
Area 0x04000
Bank 0
0000
0x00000
♦ When Used to Control up to 8 Mbits of ROM
CPU Address ROM Address

0x1FFFFF
0xDFFF Bank 0x7F
Internal
Working Bank 0x7E
RAM
0xC000
: :
External
Expansion
Working Bank 0x61
0x183FFF
0xA000 RAM Bank 0x60 Unusable
0x180000
(If accessed, the Bank 0x61 image appears)
Display : :
RAM
0x8000 Bank 0x41
0x103FFF
Bank 0x40 Unusable
0x100000 (If accessed, the Bank 0x41 image appears)
Program : :
Switching
Area
Bank 0x21
0x083FFF
Bank 0x20 Unusable
0x4000 0x080000
(If accessed, the Bank 0x21 image appears)
: :
Program
Residence
Area Bank 2
0x008000
Bank 1
0000 0x004000
Bank 0
000000
214
2. MBC2
2.1 Overview
Controller for up to 2 Mbits (256 Kbytes) of ROM with built-in backup RAM (512 x 4 bits).
♦ Register 0: RAMCS gate data (serves as write-protection for RAM)

Writing 0x0A to 000-0x0FFF causes the CS to be output, allowing access to RAM.
♦ Register 1: ROM bank code

Write addresses: 0x2100-0x21FF Write data: 0x01-0x0F
The ROM bank can be selected.
2.3 Memory Map

0xDFFF 0x3FFFF
Internal Bank 0F
Working
RAM
0xC000 Bank 0E
(512x4Bit) External
0xA1FF
Expansion
Backup RAM RAM
: :
0xA000 : :
Display
Bank 6
0x8000 0x18000
Bank 5
Program 0x14000
Switching Bank 4
Area 0x10000
Bank 3
0x4000 0x0C000
Bank 2
Program 0x08000
Residence Bank 1
Area 0x04000
Bank 0
0000 00000
2.4 Backup RAM
Allocated to the D0-D3 areas of CPU addresses 0xA000-0xA1FF

Backup RAM is write-protected by a power-on reset.
To protect backup data, avoid removing write protection unless necessary.
215
3. MBC3
3.1 Overview
MBC3 is the memory bank controller that allows use of between 512 Kbits (64 Kbytes) and 16 Mbits (2 MB)
of ROM and 256 Kbits (32 Kbytes) of RAM.
Built into the controller are clock counters that operate by means of an external crystal oscillator (32.768
KHz). The clock counters are accessed by RAM bank switching.
RAM and clock counter data can be backed up by an external lithium battery.

Settings for control registers 0-3 are specified by writing data to the ROM area.
♦ Register 0: Write protects RAM and the clock counters (default: 0)

Allows access to RAM and the clock counter registers.
♦ Register 1: ROM bank code (default: 0, selects ROM bank 1)

Write addresses: 0x2000-0x3FFF Write data: 0x01-0x7F
Allows the ROM bank to be selected in 16-Kbyte increments.
♦ Register 2: RAM bank code (default: 0, selects RAM bank 0)

Allows the RAM bank to be selected in 8-Kbyte increments.
Write addresses: 0x4000-0x5FFF Write data: 0x08-0x0C

Allows a clock counter to be selected.
Data Register Range of Values Function

0x08 RTC_S 0-59 (0-0x3B) Seconds counter (6 bits)
0x09 RTC_M 0-59 (0-0x3B) Minutes counter (6 bits)
0x0A RTC_H 0-23 (0-0x17) Hours counter (5 bits)
0-255 (0-0xFF) Lower-order 8 bits of days
0x0B RTC_DL
counter
bit7 bit0 Higher-order bit and carry bit
0 0 0 0 0 of days counter.
0x0C RTC_DH Bit 0: Most significant bit of days counter
Bit 6: HALT HALT starts and stops the
Bit 7: Carry bit of days counter clock counters.
* The days counter consists of a 9-bit counter + a carry bit. Thus, it can count from 0 to 511 (0x000-
0x1FF).
* Once the carry bit is set to 1, it remains 1 until 0 is written.
* The counters operate when HALT is 0 and stop when HALT is 1.
* Values outside the given counter ranges will not be correctly written.
♦ Register 3: Latches the data for all clock counters (default: 0)

Write addresses: 0x6000-0x7FFF Write Data: 0 → 1
Writing 0 → 1 causes all counter data to be latched. The latched contents are retained
until 0 → 1 is written again.
216
3.3 Accessing the Clock Counters
The clock counter registers are assigned to the external expansion RAM area of the CPU address space.
To access the clock counters, RAM bank switching must first be performed.
External expansion RAM Area (0xA000-0xBFFF) Bank Map

Bank Device Notes
0x00 RAM BANK 0
0x01 RAM BANK 1
0x02 RAM BANK 2
0x03 RAM BANK 3
Not used
0x08 Seconds counter
0x09 Minutes counter
0x0A Hours counter
0x0B Days counter (L)
0x0C Days counter (H)
: Not used
The following are examples of accessing the clock counters.
3.3.1 Reading
The clock counters are accessed by first writing 0x0A to register 0. This opens the gate used to access
the counters. To read clock counter values, write 1 to register 3 to latch the values of all the registers. If
the value of register 3 is already 1, first set it to 0 and then to 1. While this register is set to 1, the clock
counters will operate but the latched values of all of the clock counters will not change. This allows the
clock counters to be read.
For example, the seconds counter register can be accessed and read by first setting the RAM bank to 8,
then reading from any CPU address between 0xA000 and 0xBFFF.
3.3.2 Writing
Writing 0x0A to register 0 opens the access gate, allowing each clock counter register to be written to.
217
3.4 Memory Map
• ROM bank 0 is assigned to the program residence area (0x0000-0x3FFF) of the CPU memory space
(unchangeable).
• One bank from among ROM banks 0x01-0x7F can be assigned to the program switching area (0x4000-
0x7FFF) of the CPU memory space.
• One bank from among RAM banks 0-3 and the clock counter registers (RAM banks 0x08-0x0C) can be
assigned to the external expansion working RAM area (0xA000-0xBFFF) of the CPU memory space.

0xDFFF 0x1FFFFF
Days(H)counter Bank 0x0C Internal
Working Bank 0x7F
RAM
Days(L)counter Bank 0x0B 0x1FC000
0xC000 External : :
Hours counter Bank 0x0A Expansion 0x0FFFFF
Working
0xA000 RAM
Bank 0x3F
Minutes counter Bank 0x09
Display 0x0FC000
Seconds Bank 0x08 RAM
Counter : :
0x8000 0x07FFFF
: : Bank 0xIF
: : Program
RAM Address
: : Switching 0x07C000
Area
0x7FFF
Bank 0x03
: :
0X6000 0x4000 0x0BFFF
Bank 0x02 Bank 0x02
0X4000 0x08000
Program
Bank 0x01 Residence Bank 0x01
Area
0X2000 0x04000
Bank 0x00 Bank 0x00
0000
0000 00000
218
3.5 Programming Cautions
3.5.1 Accessing the Clock Counters
Although counting up of the clock counters themselves and accessing the clock counters from the CPU are
performed asynchronously, clock counter failure may result if both operations are performed at the same
time. To prevent this, MBC3 provides an interface circuit for WR signals from the CPU. Use of this circuit
necessitates a delay when accessing control register 3 and the clock counter registers (RTC_S, RTC_M,
RTC_H, RTC_DL, and RTC_DH). Thus, whenever accessing these registers consecutively, interpose a
delay of 4 cycles between accesses.
When reading clock counter data:
• Latch all clock counter data using control register 3.
4-cycle delay required
• Read the data in the clock counter registers.
When writing values to the clock counters:

• Set data in clock counter register RTC_S.
• Set data in clock counter register RTC_M.
• Set data in clock counter register RTC_H.
• Set data in clock counter register RTC_DL.
• Set data in clock counter register RTC_DH.
219
3.5.2 Condensation
MBC3 uses a crystal oscillator for its clock counter operation, and condensation on the oscillator may halt
its oscillation, preventing the clocks from counting up. Once the condensation disappears, the clocks will
resume counting up from where they stopped. However, please ensure that the counter stoppage does not
result in a loss of program control.
3.5.3 Control Register Initialization
Although control registers 0-3 are initialized (see Section 3.2, Description of Registers) when Game Boy
power is turned on, they are not initialized by a hard reset of SNES when Super Game Boy is used.
Therefore, please be sure to implement a software reset of these registers.
3.5.4 Clock Counter Registers
When commercial Game Boy software that uses MBC3 is shipped from the factory, the values of the clock
counter registers are undefined. Therefore, please ensure that these registers are initialized.
220
4. MBC5
4.1 Overview
Supports CGB double-speed mode.
MBC5 can use up to 64 Mbits of ROM (512 banks of 128 bits each) and
1 Mbit of RAM (16 banks of 64 Kbits each).
Upwardly compatible with MBC1.
4.2 Registers
Name Addresses (hex)

RAMG 0000-1FFF
ROMB 0 2000-2FFF
ROMB 1 3000-3FFF
RAMB 4000-5FFF
4.3 Memory Map
CPU Address
RAM 0xFFFF ROM
Unit
Highest bank, Registers Highest bank,
0x0F 0x1FF
Maximum of 1 0xE000
Mbit Internal
: : Working
Set by RAMB register. : : 0xC000 RAM
Accessible only External
when RAMG register
: :
Bank 0x01 Expansion
is 0x0A. Working RAM
0xA000
Bank 0x00 : :
Display Up to 64 Mbits
RAM Set by the
: : ROMB0,
0x8000 ROMB1
registers
Empty Bank Switching : :
(no image) Area
Bank 0x00 - Bank
0x6000 0x1FF : :
0x5000 RAMB (Default bank 0x01)
: :
0x4000
ROMB1
0x3000
Program Residence
ROMB0
Area
0x2000 Fixed at
Bank 1
Bank 0x00
RAMG
Bank 0
0x0000
Writing Reading
During a write, data is written to the bank control registers at
CPU addresses 0x0000-0x7FFF. During a read, the contents of
ROM are read from these addresses.
221

♦ Register for Specifying External Expansion Memory (RAMG)
Specifies whether external expansion RAM is accessible. Access to this RAM is enabled by writing 0x0A to
the RAMG register space, 0x0000-0x1FFF. Writing any other value to this register disables reading to and
writing from RAM.
♦ Lower ROM Bank Register (ROMB0)

Specifies the lower-order 8 bits of a 9-bit ROM bank.
The ROM bank can be changed by writing the desired ROM bank number to the ROMB0 register area,
0x2000-0x2FFF.
♦ Upper ROM Bank Register (ROMB1)

Specifies the higher-order 1 bit of a 9-bit ROM bank.
The ROM bank can be changed by writing the desired ROM bank number to the ROMB1 register area,
0x3000-0x3FFF.
♦ RAM Bank Register (RAMB)

Specifies the RAM bank
The RAM bank can be changed by writing the desired RAM bank number to the RAMB register area,
0x4000-0x5FFF.
Note Although the bits marked with are ignored by MBC5, they should
be used after being set to 0. The default values are set automatically when
power is turned on.
222
4.5.1 When Migrating from MBC1 to MBC5
♦ Use of Register 1
If an MBC1 program uses register 1 (ROM bank control register) addresses 0x3000-0x3FFF, the bank
intended for selection by ROMB1 in MBC5 will not be selected.
Addresses 0x2000-0x2FFF of register 1 should be used by programs that use MBC1.
♦ Use of Register 2
Note that in MBC1, programs that use 8 Mbits or more use register 2 (ROM or RAM bank control
register) for the high ROM bank. Consequently, in MBC5 the RAM bank is different while the ROM
bank is unchanged.
♦ ROM Banks 0x20, 0x40, and 0x60
ROM banks 0x20, 0x40, and 0x60 cannot be used in MBC1, but they can be used in MBC5.
♦ MBC1 Register 3 (ROM/RAM change)
Because the addresses of ROM and RAM are independent of each other in MBC5, ROM/RAM
switching is unnecessary.
Any write instructions to register3 left in a program that uses MBC1 are ignored by MBC5 and have no
effect.
4.5.2 General Notes
♦ Memory Image
If a memory device is used that uses less than the maximum amount of memory available (ROM: 64
Mbits; RAM: 1 Mbit) , a memory image is generated for the empty bank area. Therefore, please do not
develop software that uses an image, because it may cause failures.
♦ RAM Data Protection
To protect RAM data, it is recommended that RAM access be disabled when RAM is not being
accessed (RAMG ← 0x00) .
♦ Specifying External Sound Input (VIN)
Always use the sound control register (NR50) with bits 7 and 3 (VIN function OFF) set to 0. Because
the VIN terminal is used in development flash ROM cartridges, using the register with VIN set to ON
will produce sound abnormalities.
223
4.6 Examples of MBC5 programs on DMG and CGB
♦ Set the bank switching area (0x4000-0x7FFF) to 0x1FF.
LD A,$FF
LD ($2000),A ;ROMB0 setting
LD A,$01
LD ($3000),A ;ROMB1 setting
|
|
|
♦ Set the external expansion memory area (0xA000-0xBFFF) to 0x0F.
LD A,$0F
LD ($4000),A ; RAMB setting
LD A,$0A
LD ($0000),A ; Enable access to RAM
|
| RAM Access Processing
|
LD A,$00
LD ($0000), A ; Disable access to RAM
224
5. MBC5 (WITH RUMBLE FEATURE)

5.1 Overview
This cartridge is the same as the previous MBC5 cartridge but also includes a rumble motor and size AAA
battery to power the motor. The motor is controlled by the program using the MBC5 RAM bank register
(RAMB, bit 3).
MBC5 supports CGB normal- and double-speed modes.
Up to 64 Mbits (512 banks of 128 Kbits each) of ROM and 256 Kbits of RAM (4 banks of 64 Kbits each) can
be used.
5.2 Registers
Name Addresses (hex) Notes

RAMG 0000-1FFF
Each register executes its control
ROMB 0 2000-2FFF
using any one of the address spaces
ROMB 1 3000-3FFF
at left.
RAMB 4000-5FFF
225
5.3 Memory Map
CPU Address
RAM 0xFFFF
ROM
Unit
Bank 3 Registers Highest bank, 0x1FF
0xE000
Maximum of 256 Internal
Kbits (Banks 0-3) Bank 2 Working
RAM : :
Set by register RAMB Bank 1 0xC000 External
Accessible only when Expansion
RAMG is 0x0A Working RAM : :
Bank 0
0xA000 Display Maximum 64
RAM : : Mbits
Set by registers
0x8000 ROMB0 and
ROMB1
Empty
(no image) Bank Switching : :
Area
0x6000 Bank 0x00 - Bank
0x1FF
0x5000 RAMB (Default bank 0x01) : :
0x4000
ROMB1
0x3000
ROMB0 Program Residence
0x2000 Area Bank 1
Fixed at Bank 0
RAMG
Bank 0
0x0000
Write Read
* During a write, data is written to the bank control registers at
CPU addresses 0x0000-0x7FFF. During a read, the contents of
ROM are read from these addresses.
226

♦ Register for Specifying External Expansion Memory (RAMG)
Specifies whether external expansion RAM is accessible. Access to this RAM is enabled by writing 0x0A
to the RAMG register (any single address in 0x0000-0x1FFF). Writing any other value to this register
disables reading to and writing from RAM.
♦ Lower ROM Bank Register (ROMB0)

Specifies the lower-order 8 bits of a 9-bit ROM bank.
The ROM bank can be changed by writing the desired ROM bank number to the ROMB0 register (any
single address in 0x2000-0x2FFF).
♦ Upper ROM Bank Register (ROMB1)

Specifies the higher-order 1 bit of a 9-bit ROM bank.
The ROM bank can be changed by writing the desired ROM bank number to the ROMB1 register (any
♦ RAM Bank Register (RAMB)

Specifies the RAM bank.
The RAM bank can be changed by writing the desired RAM bank number to the RAMB register (any
Bits 0-1: Register for RAM bank setting

Bit 3: Motor control register (1: motor ON; 0: motor OFF)
Note Be sure to set the bits marked with to 0 before using them. The
default values are set automatically when power is turned on.
227
5.5 Motor Control
5.5.1 Vibration Level
Control of the rumble motor consists of setting it to ON or OFF.

The vibration level can be controlled by sending pulses of combined ON/OFF instructions in short
cycles. Please comply with the following points when implementing vibration control.
(1) Set the frame rate to 1 frame per 1/60 second and control vibration frame by frame.
(2) At the start of vibration control, send a startup pulse (at least 2 ON frames).
A startup pulse also should be sent if the width of an OFF pulse is 3 or more consecutive
frames. This is necessary because startup from a complete stop requires a certain amount of
time.
(see Ex. 5)
5.5.2 Vibration Pulse Examples

RAMB
Bit 3
ON
Example 1:
Strong
OFF
2Frames 1 2
ON Startup
Example 2:
Pulse
Slightly strong
OFF
2Frames 1 1
Example 3: ON Startup
Pulse
Slightly weak
OFF
2Frames 2 1
ON Startup
Example 4: Pulse
Strong
OFF
2Frames 3 2
Example 5: ON Startup Startup
3 consecutive Pulse Pulse
OFF frames
OFF
228
IMPORTANT
5.6.1 Memory Image

If a memory device is used that uses less than the maximum amount of memory available
(ROM: 64 Mbits; RAM: 256 Kbits) , an empty bank area (memory image) results. Please do not
access this empty bank area. Doing so may result in faulty operation.
5.6.2 RAM Data Protection

To protect RAM data, it is recommended that RAM access be disabled (RAMG 0x00) when
RAM is not being accessed.
5.6.3 Specifying External Sound Input (VIN)

Always use the sound control register (NR50) with bits 7 and 3 set to 0 (VIN function OFF).
Because the VIN terminal is used in development flash ROM cartridges, using the register with
VIN set to ON will produce sound abnormalities.
5.6.4 Disabling Vibration Using the SGB, SGB2, or 64GB Pak

When MBC5 is used by SGB, SGB2, or the 64GB Pak, vibration should be turned off by the
program to prevent failures caused by a faulty connection. For methods of recognizing SGB
and SGB2, see the description of the MLT_REQ command in Chapter 6, Section 3.2, System
Command Details. With the 64GB Pak, vibration is controlled by the N64 software. Therefore,
N64 software programs that support MBC5 should not write data to bit 3 of the RAM bank
register.
5.6.5 Limiting the Period of Continuous Vibration

To prevent physical effects in the user such as numbness as a result of continuous vibration,
limit the duration of continuous vibration as indicated below, regardless of the vibration strength
(see Section 5.5.2, Vibration Pulse Examples).
• The duration of continuous vibration should generally be limited to a maximum of 1

minute.
• The period of no vibration between the finish of one period of vibration and the start of the
next period generally must be at least as long as the vibration time.
The above points are guidelines that should be followed in most cases. However, if adhering to
these guidelines is made difficult by factors such as the game content, take appropriate
measures while keeping in mind the points noted in Section 6.7, Effects of Vibration on the
Body.
5.6.6 Disabling Vibration for Resets and Pauses

Vibration should be halted during resets and pauses.
When power is turned on, the unit should not be vibrated until some input is received from the
controller.
229
5.6.7 Rumble Feature Selection

The user should be allowed to set the rumble feature to ON or OFF or to select strong, mild, or
OFF by means such as an initial-settings screen at the start of the game. In addition, the
program should allow the user to easily change these settings even during a game if, for
example, they are uncomfortable with the vibration. Such changes also should be allowed a
pause.
5.6.8 Changes in Vibration Level with Battery Use

If the battery that powers the motor (Size AAA alkaline battery) wears out, the perceived
vibration level will be reduced even if the requested vibration level remains the same.
Therefore, rumble operation should be checked both when the battery is new (1.6 V) and when
it is at the end of its life (1.1 V).
5.7 Physical Effects of Vibration on the Body
Users have occasionally experienced numbness for some time after continuous vibration lasting several
tens of seconds to several minutes. This may occur regardless of the strength of the vibration (see
Section 5.5.2, Vibration Pulse Examples).
Unfortunately, the effects of continuous vibration on the body are not yet clear. Thus, the guidelines
presented in Section 5.6.5, Limiting the Period of Continuous Vibration, are intended to give priority to
user safety. However, software development requires free thinking and original ideas, and there may
well be cases in which the use of continuous vibration in a game is desirable.
Because each game is different, the limitations presented in Section 5.6.5 are by their nature not
restrictions that should be enforced digitally. It is instead preferable for the developer to adequately
consider user safety when determining the game’s content.
For example, even supposing that continuous vibration does last for more than 1 minute, it may not pose
a safety problem if it is used infrequently, such as only when special events occur. Conversely, if
vibrations lasting several seconds to several tens of seconds are repeated at short intervals, the effects
on the user may be the same as with continuous, long-term vibration.
Thus, the guidelines presented in Section 5.6.5 are not absolute restrictions. However, even if a
program varies from these guidelines, the following points should be considered minimum requirements
and strictly observed.
• Continuous vibration should not exceed 3 minutes for any reason.
• Because the effects of continous vibration vary from person to person, the strength of these effects
on the user should not be determined independently by the developer. Rather, this determination
should be arrived at after considering the opinions of many others during debugging and other
phases of development.
230
Chapter 9: Pocket Printer
Chapter 9: Pocket Printer .....................................................233

1. Overview ........................................................................................ 233
2. Communication Specifications ................................................... 233
2.1 Bidirectional Communication ...............................................................233
2.2 Transfer Interval for Each Byte .............................................................233
2.3 Packets and the Transfer Interval.........................................................233
2.4 Synchronism Check when Connecting ...............................................233
3. Communication Data Definitions ................................................ 234
3.1 Transferring to the Printer.....................................................................234
3.2 Receiving from the Printer ....................................................................235
3.3 Handling Errors ......................................................................................235
4. Packet Details................................................................................ 237
4.1 The Initialization and Connection Packet ............................................237
4.2 Print Instruction Packet.........................................................................237
4.3 Data Packet.............................................................................................238
4.4 Data-End Packet.....................................................................................239
4.5 Break Packet...........................................................................................239
4.6 NUL Packet .............................................................................................239
4.7 Packet Error............................................................................................239
4.8 Other Packets .........................................................................................239
5. Printer Status and Packets .......................................................... 240
6. Printer Print Sequence ................................................................. 241
7. Processing Connection Eval./Preamble Detection Failure....... 242
7.1 Connection Evaluation (includes cable disconnection) ....................242
7.2 Preamble Detection Failure...................................................................242
8. Print Data ....................................................................................... 243
9. Compression Algorithm ............................................................... 244
10. Hardware Specifications ............................................................ 245
10.1 General Specifications ........................................................................245
10.2 Dimensions and Weight ......................................................................245
11. Miscellaneous.............................................................................. 245
231
11.1 Cautions when Debugging..................................................................245

11.2 Sample Programs Provided by Nintendo (subroutines)...................245
232
CHAPTER 9: POCKET PRINTER
1. OVERVIEW
These specifications define the serial protocol used to send print and control data from Game Boy
to the Pocket Printer (abbreviated to printer). Game Boy sends data to the printer in packets, and
the printer responds by returning 2 bytes of status information.
2. COMMUNICATION SPECIFICATIONS
2.1 Bidirectional Communication
Serial transfers between Game Boy and the printer are performed in the Game Boy specification
communication format (bidirectional).
The shift clock is furnished by the Game Boy. Both Game Boy and the printer start transmission
from the most significant bit (MSB).
For more information , see Chapter 1, Section 2.5.1, Serial Cable Communication.
Game Boy Printer
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
2.2 Transfer Interval For Each Byte
An interval of 270 µs to 5 ms must be interposed between each byte sent. Thus, care should be
exercised regarding factors like interrupts when programming.
2.3 Packets and the Transfer Interval
Each type of data sent by the Game Boy is sent in a packet. An interval of 270 µs to 117 ms
must be allowed between the transfer of each packet. Thus, care should be exercised regarding
factors like interrupts when programming.
2.4 Synchronism Check when Connecting
After the connection between the Game Boy and printer is confirmed, the Game Boy sends a
NUL packet every 100 msec for a synchronism check of the connection. If the Game Boy
determines that a connection is unnecessary and does not send a NUL packet in the prescribed
time, the printer will determine that the connection is abnormal and will wait in an initialized state
for a signal from the Game Boy.
233
3. COMMUNICATION DATA DEFINITIONS
This section defines the following data items (packet types and data) by function.
3.1 Transferring to the Printer
The packet types are as follows.
Packet Type Code

Initialization and connection 01
packet
Print instruction packet 02
Data packet 04
Data end packet 04
Break packet 08
NUL packet 0F
Each of the above packet types is in the following format.
Preamble Header Data Checksum Dummy
Preamble: 2 bytes of data: 0x88 x 1 + 0x33 x 1. Abbreviated PA below.

Header: 4 bytes of contiguous data that represent the following.
Byte 1. Packet type
01: Initialization and connection packet
02: Print instruction packet
04: Data packet
08: Break packet
0F: NUL packet
Byte 2: In the case of a data packet, indicates compression/no compression.
If another type of packet, fixed at 0x00.
Bytes 3 and 4: Data volume (2 bytes), number of bytes of data
Data: Data in Game Boy character data format. Print instruction data.
Checksum: 2 bytes of data representing the sum of the header + all data in the data
portion of the packet.
Dummy: 2 bytes of dummy data used to obtain status information from the printer.
In the data received from the printer in place of the dummy data, byte 1
holds the peripheral device number and byte 2 holds the printer status.
234
3.2 Receiving from the Printer

The printer returns 2 bytes of status data.
Byte 1: Device number

1 0 0 0 0 0 0 1
The value of the MSB is always 1. The lower-order 7 bits represent the device number.
The Pocket Printer is device no. 1.
Byte 2: Status
LowBat ER2 ER1 ER0 Untran Full Busy Sum
LowBat: 1 = Low-battery error bit

0 = Battery OK
ER2: 1 = Other error
ER1: 1 = Paper jam (abnormal motor operation)
ER0: 1 = Packet error
Untran: 1 = Unprocessed data present
0 = No unprocessed data present
Full: 1 = Image data full
0 = Image data not full
Busy: 1 = Printer busy
0 = Printer ready
Sum: 1 = Checksum error
0 = Data OK
Status information is sent in reply to each 2 bytes of dummy data sent by the Game Boy.
* The status returned by the printer is FF FF when the printer is not connected to the Game Boy
or not powered on.
3.3 Handling Errors
Either an error number listed below or the error number plus a description of the error would be
sent to the display screen in response to an error flag in byte 2. (This information is also
presented in the user’s manual of the Pocket Printer. That information must be used together with
the information given here.)
Status: Byte 2 Error No.

low Bat = 1 01
FF FF 02
ER1 = 1 03
ER2 = 1 04
* Error No. 02 is represented using both status bytes.
ER0 = 1 likely indicates program failure.

When an error is generated, always sever communication with the printer and inform the user of
the type of error.
235
A value other than 0x81for the first status byte means that a device other than the Pocket Printer
is connected. This should be conveyed to the user as an error message.
236
4. PACKET DETAILS
4.1 The Initialization and Connection Packet
This packet is used to initialize the printer and check the connection. If the Game Boy sends a packet for
checking the printer connection and a printer is connected, it returns a 2-byte status code and initializes for the
start of print processing. This packet must always be sent when the Game Boy starts to access the printer. It
allows transferred data to be invalidated (reset).
Actual Data
88 33 01 00 00 00 01 00 00 00
PA Header Checksum Dummy

This packet has no data section.
Normal status: 0x81 and 0x00 (For more information, see Section 3, Communication Data Definitions.)
Not connected: 0xFF and 0xFF.
4.2 Print Instruction Packet

Used for print instructions for single-sheet mode and copy mode (for specifying the number of
sheets).
Example
88 33 02 00 04 00 01 13 E4 40 3D 01 00 00
PA Header Data Checksum Dummy
Data: Byte 1 specifies the number of sheets. 0-255 (1 in the example). 0 means line feed only.
Data: Byte 2 indicates the number of line feeds. Higher-order 4 bits represents the number of feeds before
printing.
Lower-order 4 bits represents the number after printing. Each
value is 0x00-0x0F.
* 1 feed = 2.64 mm
Data: Byte 3 holds the palette values. Default is 00. Palettes are defined by every 2 bits beginning
from high bit. (See Chapter 2, Section 2.3, Character RAM.)
Data: Byte 4 is the print density adjustment. 0x00-0x7F. Default values are 0x40 and 0x80 or greater.
00 < 0x40 < 0x7F
-25% 0% +25%
When printing continuous images from multiple screens, setting the number of line feeds to 0 after one screen’s
worth of data is printed (9 data packets and a data-end packet) enables printing to be continued from one
image to the next without a break.
Cautions Regarding Print Instructions (Caution Required)
• Although applications can print 2-255 pages continuously, this may take a long time. Thus, the user should
be provided with a means of halting a print job in progress. (See Section 4.5, Break Packet.)
• Whenever possible, the print density data should be backed up to avoid the inconvenience of adjusting the
density at each startup.
237
• If a print instruction packet is set within 100 msec of when the motor is stopped, the position where printing
resumes may be incorrect. Always send print instruction packets at least 100 msec after the motor has been
stopped.
• Always set the number of line feeds before printing to 1 or greater and the number after printing to 3 or
greater, except in the case of the previously mentioned continuous printing , when both values are 0. Other
values for these parameters may in result in faulty operation, such as double printing on the same line or
failure of the last printed line to reach the paper cutter.
4.3 Data Packet
Sends print data that are in character data format. The print data is sent in 1-byte increments for the specified
number of bytes.
Example
88 33 04 00 80 02 Data0 ~ DataN-1 C1 C2 00 00
PA Header Data Checksum Dummy
Notification of compression/no compression: Maximum number of data bytes is 0x280

(NoError through 0x3FF): (16 (bytes/color) x 20 (colors) x 2 (colors)).
Nine of these packets represent 1 printed sheet. (160 dots x 144 dots)
Byte 2 of the header is the compression/no compression notification byte.
* 1: Compression (* upper 4 bits have no effect)
* 0: No compression
Transmission of compressed data is accomplished by compressing one line at a time -- each line consisting of
20 characters horizontally and 2 characters vertically -- and sending the number of compressed bytes in order,
beginning from the first line.
If the compressed lines exceed 0x280 bytes, the non-compressed data is sent as is (mixture of compressed
and non-compressed packets). If the extended data do not fill an entire line when the packets are processed,
the printer returns a packet error.
If an instruction to stop printing is received while print data is being sent, an initialization packet can be sent
instead of the next data packet.
One Game Boy screen of data is represented by 9 data packets. However, a data-end packet can be sent even
if the number of data packets sent is less than 9. In this case, the printer will print only the number of lines
received. Line feeds can be performed by sending a data-end packet with no data packet and issuing a print
instruction. The printer will then feed the number of lines indicated by the instruction.
Sending the following print instruction packet with a data-end packet but no data packet would specify that 5
sheets be printed, with 1 line feed before printing and 3 line feeds after printing, and that the pre-printing line
feeds be ignored. The number of line feeds performed would therefore equal the product of number of sheets to
be printed and the number of post-printing line feeds specified. Thus, in this example, the number of line feeds
would be 15.
Example
88 33 02 00 04 00 05 13 E4 40 42 01 00 00
238
4.4 Data-End Packet
Actual Data
88 33 04 00 00 00 04 00 00 00

A data length of 0 for the data packet header represents the end of the print data. This must always be sent to
end print data transmission.
4.5 Break Packet
Used to discontinue printing. The break packet is sent by means of the user’s instructions and forcibly stops
printing. (Printing is halted after 1 line is printed.)
Actual Data
88 33 08 00 00 00 08 00 00 00

4.6 NUL Packet
A functionless packet for requesting the current status of the printer. The printer may occasionally be halted
unintentionally while printing (e.g., paper jam, low battery), so a NUL packet should always first be sent to check
the printer’s status.
Actual Data
88 33 0F 00 00 00 0F 00 00 00

4.7 Packet Error
Except in the case of a checksum error, if a packet of one of these types is sent but does not match the
specification described, the printer will return a packet error.
4.8 Other Packets
Packets other than the types mentioned above are ignored by the printer.
239
5. PRINTER STATUS AND PACKETS
The following table shows the packets that can and cannot be sent from the Game Boy to the printer while the
printer is in various states.
Disconnected Immediately Print Buffer While While

after Full Printing Feeding
Connected
Connection/initialization packet Ο Ο Ο s s
Print instruction packet ? x Ο s s
Data packet ? Ο x s s
Data-end packet ? Ο x s s
Break packet ? s s Ο s
NUL packet ? Ο Ο Ο Ο
Ο = OK; s = ignored; x = packet error; ? = undefined
* The user could push the feed button while data is being transferred. In this case, the entire data packet would
be ignored, so the same packet would need to be re-sent.
240
6. PRINTER PRINT SEQUENCE

The print sequence used in the Game Boy.
241
7. PROCESSING OF CONNECTION EVALUATION AND PREAMBLE DETECTION

FAILURE
7.1 Connection Evaluation (includes cable disconnection)

To check whether a printer is connected to the Game Boy, it sends a NUL packet. If nothing is connected, the value 0xFF
is received; if there is a connection, 0x00 is received.
Game Boy Printer

Not Connected
NUL packet sent No data reception detected
↓ ↓
0xFF received
↓ No data for 120 ms
Evaluates as not connected
↓
Evaluates as not connected; print data cleared
Cable connected here
NUL packet sent NUL packet detected
↓ ↓
0x00 received Status of 0x00 sent
↓ ↓
Evaluates as connected Evaluates as connected
↓ ↓
Connection-check packet
sent after 100 msec delay Connection confirmed, ACK returned
. .
. .
The printer prepares to print data again; it is not cleared while data is received.
7.2 Preamble Detection Failure

If preamble detection fails during data reception, the flow of the Game Boy and printer sequences are as shown below in
parallel.
Game Boy Printer
Printer normal
Printer status normal ↓
↓ Wait to receive data
Start communication ↓
↓ Data reception
Cable disconnects during data transfer ↓
↓ Preamble detection failure
Printer status = 0xFF ↓
↓ Set status to 0xFF
Confirm reset of printer connection ↓
↓ 80 msec delay
Check connection after 100 msec ↓
Printer initialization
242
8. PRINT DATA
The print data transferred in data packets is in character data format.
Printing Example
Line1
Line2
Line3
Line4
Line5
Line6
Line7
Line8
Line9
X00 X01 X02 X03 .... X09 X0A X0B X0C ... X13
Y0
Y1
Transfer Order
Y0.X00 --> Y0.X01 --> Y0.X02 --> ··· Y0.X13: 2 x 8 x 20 = 0x140 bytes
Y1.X00 (2 x 8) --> Y1.X01 --> ··· Y1.X13: 2 x 8 x 20 = 0x140 bytes
Total 0x280 bytes
1 CHAR =
2 bytes (higher grayscale, then lower grayscale) x 8 dots
vertically
243
9. COMPRESSION ALGORITHM
Compressed data essentially consist of control codes specifying the data type and length and the
actual data.
À Control code 1 + raw data

Á Control code 2 + loop data
Control Code Control Code Control Code Control Code Control Code
0x7F ... 0x7E ... 0xFF ... 0x80 ... 0xFE ... ...
RAW Data RAW Data Loop Data Loop Data Loop Data
À Control code 1 + Raw data

0x7F: Next 0x80 bytes are raw data
0x0-0x7E (N): Next < N + 1 data items (0x01-0x7F) are raw data
Á Control code 2 + Loop data

0xFF: Repeat the next < 1 byte of data for 0x81 bytes
0x80-0xFE: Repeat the next < 1 byte of data for 2 (80) – 0x80 (FE) items
Example
0x09 0xA0 0xA1 0xA2 0xA3 ... 0xAA 0x7F 0x80 0x81 0x82 ... 0xFF 0xFF 0x55 0x80 0xAA
0x10 bytes of raw data 0x80 bytes of raw data 0x81 items of 0x55, 0x02 items of 0xAA
244
10. HARDWARE SPECIFICATIONS
10.1 General Specifications
• Printing method: Thermal serial dot

• Print direction: Left to right (facing direction of paper feed)
• Total dot count: 16 x 160 (H x W/line)
• Dot pitch: 0.165 mm x 0.167 mm (H x W)
• Dot dimensions: 0.14 mm x 0.164 mm (H x W)
• Paper feed pitch: 2.64 mm
• Print width: Approximately 6.6 mm
• Printing speed: Approximately 1.1 lines/sec
10.2 Dimensions and Weight
• Dimensions: 72.2 mm x 139.5 mm x 56.0 mm (W x D x H)

• Weight: Approximately 190 g (not including battery)
11. MISCELLANEOUS
11.1 Cautions when Debugging
The printer comes in two types, each made a different manufacturer (Seiko Systems and Hosiden). During
final game debugging, the game should be checked with at least 1 printer of each type. The manufacturer
can be determined from the serial number on the back of the unit (Printers with PS serial numbers are made
by Seiko; those with PH serial numbers are made by Hosiden.) Many of the Seiko printers obtained on the
market are the normal Pocket Printer, while many of the printers made by Hosiden are manufactured
according to the special Pocket Printer Pikachu Yellow specification. However, depending on the needs of
the manufacturers, there is no guarantee that this distinction will hold true in the future. If obtaining a printer
proves difficult, please contact Nintendo for a special consultation.
11.2 Sample Programs Provided by Nintendo (subroutines)
Modifying a program to suit the intended use is permitted. However, in creating the original program, values
for timing and other parameters were calculated to allow normal operation. These parameters must
therefore be carefully considered when modifying a program.
245
246
Appendix 1: Programming Cautions
APPENDIX 1: PROGRAMMING CAUTIONS ......................................... 248

1. Using this Appendix ..................................................................... 248
2. Programming Cautions Regarding Game Boy.......................... 249
2.1 LCDC/VRAM............................................................................................249
2.2 Communication ......................................................................................250
2.3 Sound ......................................................................................................250
2.4 Miscellaneous Notes..............................................................................251
3. Programming Cautions Regarding MBCs ................................. 253
3.1 All MBCs .................................................................................................253
3.2 MBC 3 ......................................................................................................253
3.3 MBC5 .......................................................................................................254
4. SGB Programming Cautions....................................................... 256
4.1 ROM Data ................................................................................................256
4.2 Default Data ............................................................................................256
4.3 SOU_TRN default data ...........................................................................256
5. Programming Cautions Regarding Pocket Printer ................... 257
5.1 Transfer Time Intervals..........................................................................257
5.2 Printing Multiple Sheets Continuously.................................................257
5.3 Print Density ...........................................................................................257
5.4 Operation After the Motor is Stopped ..................................................257
5.5 Feeds.......................................................................................................257
5.6 Point of Caution During Debugging .....................................................257
5.7 Sample Program Provided by Nintendo...............................................257
6. Programming Cautions for U.S. Programmers .......................... 258
247
APPENDIX 1: PROGRAMMING CAUTIONS

1. USING THIS APPENDIX
Purpose and Scope
These programming notes provide information on how to avoid easily made mistakes during program
development, information on unique Game Boy programming issues that require special attention, and special
issues regarding peripheral devices.
Items Covered in this Manual
Many of the topics covered in this appendix also are covered elsewhere in different chapters of this manual.
This appendix consolidates the discussion of these topics. Topics that would be more easily comprehensible to
the reader when presented separately will also be discussed in another chapter, even though this may
duplicate the discussion in this appendix.
Note: Although these notes were created to make every effort to eliminate potential sources of trouble at
market, they do not represent a guarantee that various potential problems on the market can be absolutely
avoided.
248
2. PROGRAMMING CAUTIONS REGARDING GAME BOY

Covers:
DMG: DMG, MGB, and MGL
SGB: SGB and SGB2
CGB: CGB
2.1 LCDC/VRAM
2.1.1 Setting the LCDC to OFF (Recommended)
Covers: DMG and CGB

In early DMGs, a black horizontal line appears on the screen if the LCDC is stopped (LCDC register bit 7 ← 0) at any
time other than during vertical blanking. Therefore, the LCDC should be set to OFF during V-blanking. If the
occurrence of V-blanking cannot be confirmed, the LCDC should be set to OFF when the value of the LY register is 145
(0x91) or greater. These restrictions do not apply in CGB. Thus, when creating software for use on CGB only, the
timing of setting the LCDC to OFF need not be considered.
2.1.2 Window x-coordinate Register (Required)
Covers: DMG, SGB, and CGB

When the window is displayed, the window x-coordinate register (register WX, address 0xFF4B) must be set in the
range 7-165. A setting of 0-6 or 166 is prohibited. Specifying a value of 167 or greater causes the window not to be
displayed.
2.1.3 Displaying Multiple Windows (Required)
Covers: CGB
Multiple windows that divide the screen horizontally into upper and lower areas can be displayed by setting the window
x-coordinate register (WX) to a value of 167 or greater during a horizontal blanking period. Attempting to display
multiple windows by switching the window ON and OFF during H-blanking may result in the lower window not being
displayed.
Display Data WX Value

Window WX=7
BG (Background) 167<WX<255
Window WX=7
LCD Display Screen
Display Data Window

Window ON
BG (Background) OFF
Window ON
LCD Display Screen
249
Reference Notes:
1. Accessing VRAM Outside of a V-blanking period
In early DMGs, accessing VRAM outside of a V-blanking period would corrupt the screen.
2. Length of H-blanking
The length of the H-blanking period changes depending on the conditions of OBJ use, so caution is
recommended when using H-blanking.
2.2 Communication
2.2.1 Communication Rate (Required)
Covers: DMG, SGB2, and CGB

Data may be corrupted if the data transfer rate is too high.
The maximum external clock setting should be 512KHz between CGBs.
It should be 500KHz for others including DMG and SGB2.
Also, it should be 256KHz for communication between CGB and DMG.
2.2.2 Communication Errors (Recommended)
Covers: DMG, SGB2, and CGB

When using the communication function (infrared), the communicating data may be corrupted by noise and such.
Therefore, the program should not go out of control by such data corruption on both the sending and receiving side.
When using the communication function (serial), depending on how program is made, it is confirmed that
communication errors happen rarely.
SIO interrupt processing may be delayed by factors such as the processing of other interrupts. This type of error should
be avoided by establishing a proper communication interval that allows a problem-free exchange of data.
2.2.3 Effects of Other Infrared Devices (Recommended)
Covers: CGB
Adequate care should be taken to ensure against faulty operation and loss of program control even when infrared
communication signal input is received from other game software and devices. Note that such problems may
particularly occur in communication between multiple games that use the same subroutines. (Before performing data
communication, use means such exchanging a unique key code to check whether the same game is on the other
hardware.)
2.3 Sound
2.3.1 Using Sounds 1, 2 , and 3 (Required)
Covers: CGB
With continuous operation mode selected (bit 6 of NR*4 set to 0) for sounds 1, 2, and 3, if the higher-order frequency
data (lower-order 3 bits of NR*4) are changed, the sound length (bits 0-5 of NR*1) must to set to 0 after the frequency
data is set. If the sound length is not set to 0, the sound may stop during playback.
2.3.2 Using Sound 3 (Required)

When sound 3 is used, data should always first be specified for addresses 0xFF30-0xFF3F of waveform RAM. If the
initial flag is set during sound 3 operation (sound 3 ON flag = 1), the contents of waveform RAM will be destroyed.
250
2.4 Miscellaneous Notes
2.4.1 Using Interrupts (Required)

When interrupts are used, the IF register should be cleared before the IE register is set. If the IF register is not first
cleared, an interrupt may be generated immediately after interrupts are enabled.
2.4.2 Reading Keys (Required)
Covers: DMG
An interval of approximately 18 cycles should be used between output from P14 and P15 and reading of input. Without
this interval, normal key input cannot be read.
2.4.3 Using the Timer (Required)

The timer should be started (TAC start flag set) after the count-up pulse is selected. Starting the timer before or at the
same time as the pulse is selected may result in an extra count-up operation at the time of pulse selection.
Example:
LD A,3 ;Selects f/256 as the count-up pulse.
LD (07),A ;Sets TAC ← 3
LD A,7 ;Starts the timer
LD (07),A
If a write instruction is executed for the modulo register TMA with the same timing as the contents of that register are
transferred to TIMA as a result of a timer overflow, the same write data also will be transferred to TIMA..
2.4.4 Using STOP Mode (Required)

When STOP mode is used, all interrupt-enable (IE) flags should be reset before execution of a STOP instruction.
Otherwise, if an interrupt is generated during the period of oscillation stabilization (HALT mode) following STOP mode
cancellation, HALT mode will immediately be canceled, preventing a stable system clock from being provided.
2.4.5 Using Paired Registers (Required)

With instructions that use paired registers BC, DE, and HL, such as the following, there is some chance that OAM RAM
may be destroyed. Therefore, ensure that these paired registers are not set to a value in the range 0xFE00-0xFE9E.
INC ss ; ss : BC, DE, HL
DEC ss
LD A,(HLI)
LD A,(HLD)
LD (HLI),A
LD (HLD),A
2.4.6 Using the HALT Instruction (Required)

When using a HALT instruction, always add an NOP instruction immediately after the HALT instruction. Not adding the
NOP instruction may in rare cases cause the instruction after the HALT instruction not to be executed.
251
2.4.7 Switching the CPU Operating Speed (Recommended)
Covers: CGB
When switching the CPU operating speed, first confirm the current speed by checking the speed flag (bit 7 of register
KEY1). In double-speed mode, both the divider (DIV) and timer (TIMA) registers will also be set for double-speed
operation.
2.4.8 Using Horizontal Blanking DMA (Required)
Horizontal blanking DMA should always be started (bit 7 of HDMA5 set to 1) when the STAT mode is not set to 00. If
horizontal blanking DMA is started when STAT mode is 00, depending on the timing, the data in LCD display RAM may
be destroyed. In addition, execution of a HALT instruction during horizontal blanking DMA may prevent normal
cancellation of the HALT mode or DMA. Therefore, HALT instructions should not be used while horizontal blanking
DMA is being started.
2.4.9 Using General-Purpose DMA (Required)
General-purpose DMA should be started (bit 7 of HDMA5 set to 0) with the LCDC off or during V-blanking. However,
when transferring data during V-blanking, ensure that the transfer period does not overlap with STAT modes 10 or 11.
2.4.10 DMA Transfers to OAM (Required)
In DMG and in CGB in DMG mode, when transferring data to OAM by DMA, the user program area (0x00-0x7FFF)
should not be used as the starting address of the transfer. In some cases, data cannot be transferred from the user
program area normally. CGB mode, however, does enable DMA transfers from the user program area.
2.4.11 Status Interrupts (Required)

When using a status interrupt in DMG or in CGB in DMG mode, register IF should be set to 0 after the value of the STAT
register is set. (In DMG, setting the STAT register value changes the value of the IF register, and an interrupt is
generated at the same time as interrupts are enabled.)
2.4.12 Chattering (Recommended)

To prevent buttons from inadvertently being pressed twice, an interval should be provided between key reads.
(Although this varies with the software, keys are normally read approximately once per frame.)
252
3. PROGRAMMING CAUTIONS REGARDING MBCS

3.1 All MBCs
3.1.1 Protecting RAM Data (Recommended)
To protect RAM data, access to RAM should be disabled (RAMG←0x00) when it is not being accessed.
3.2 MBC3
3.2.1 Accessing the Clock Counters (Required)
If the clock counters themselves are counted up, accessing of the clock counters by the CPU is performed
asynchronously. However, if these operations are performed simultaneously, the clock counters may fail. To prevent
this, MBC3 provides an interface circuit for WR signals from the CPR. Use of this circuit necessitates a delay when
accessing control register 3 and the clock counter registers (RTC_S, RTC_M, RTC_H, RTC_DL, and RTC_DH). Thus,
whenever accessing these registers consecutively, interpose a delay of 4 cycles between accesses.
When reading clock counter data:
• Latch all clock counter data using control register 3.
• Read the data in the clock counter registers.
When writing values to the clock counters:
• Set data in clock counter register RTC_S.
• Set data in clock counter register RTC_M.
• Set data in clock counter register RTC_H.
• Set data in clock counter register RTC_DL.
• Set data in clock counter register RTC_DH.
3.2.2 Condensation (Required)
MBC3 uses a crystal oscillator for its clock counter operation, and condensation on the oscillator may halt its oscillation,
preventing the clocks from counting up. Once the condensation disappears, the clocks will resume counting up from
where they stopped. However, please ensure that the counter stoppage does not result in a loss of program control.
253
3.2.3 Control Register Initialization (Required)
Although control registers 0-3 are initialized (see Section 3.2, Description of Registers) when the Game Boy power is
turned on, they are not initialized by a hard reset of SNES when Super Game Boy is used. Therefore, please be sure to
implement a software reset of these registers.
3.2.4 Clock Counter Registers (Required)
When commercial GB software that use MBC3 are shipped from the factory, the values of the clock counter registers
are undefined. Therefore, please ensure that these registers are initialized.
3.3 MBC5
3.3.1 Memory Image (Required)
If a memory device is used that uses less than the maximum amount of memory available (ROM: 64 Mbits; RAM: 1
Mbit) , a memory image is generated for the empty bank area. Therefore, please do not develop software that uses an
image, because it may cause failures.
3.3.2 Specifying External Sound Input (VIN) (Required)
Always use the sound control register (NR50) with bits 7 and 3 (VIN function OFF) set to 0. Because the VIN terminal is
used in development flash ROM cartridges, using the register with VIN set to ON will produce sound abnormalities.
3.3.3 Disabling Vibration Using the SGB, SGB2, or 64GB Pak (Recommended)
When MBC5 with rumble feature is used by SGB, SGB2, or the 64GB Pak, vibration should be turned off by the
program to prevent failures caused by a faulty connection. For methods of recognizing SGB and SGB2, see Chapter 6,
section 4.2, Recognizing SGB. With the 64GB Pak, vibration is controlled by the N64 software. Therefore, N64
software programs that support MBC5 should not write data to bit 3 of the RAM bank register.
3.3.4 Disabling Vibrations for Resets and Pauses (Recommended)
Vibration should be halted during resets and pauses.

When power is turned on, the hardware should not be vibrated until some input is received from the controller.
254
3.3.5 Limiting the Period of Continuous Vibration (Recommended)
To prevent physical effects in the user such as numbness as a result of continuous vibration, limit the duration of
continuous vibration as indicated below, regardless of the vibration strength.
• Limit the duration of continuous vibration to 1 minute.

• If the nature of the game makes longer periods of continuous vibration unavoidable, limit these periods to 3
minutes.
3.3.6 Rumble Feature Selection (Recommended)
The user should be allowed to set the rumble feature to ON or OFF or to select strong, mild, or OFF by means such as
an initial-settings screen at the start of the game. In addition, the program should allow the user to easily change these
settings even during a game if, for example, they are uncomfortable with the vibration. Such changes also should be
allowed a pause.
3.3.7 Changes in Vibration Level with Battery Use (Recommended)
If the battery that powers the motor (size AAA alkaline battery) wears out, the perceived vibration level will be reduced
even if the requested vibration level remains the same. Therefore, rumble operation should be checked both when the
battery is new (1.6 V) and when it is at the end of its life (1.1 V).
255
4. SGB PROGRAMMING CAUTIONS

4.1 ROM Data (Required)
To use the functions of SGB (system commands), the following values must be stored in ROM at the locations indicated.
0x146 ← 0x03, 0x14B ← 0x33
4.2 Default Data (Required)
When writing programs that use the functions of SGB, use the initialization routine of the game program to send default
data (see Chapter 6) to the register file.
4.3 SOU_TRN Default Data (Required)
When using the SOU_TRN system command, send the SOU_TRN default data (see Chapter 6) to the register file before
SOU_TRN is used.
256
5. PROGRAMMING CAUTIONS REGARDING POCKET PRINTER

5.1 Transfer Time Intervals (Required)
Transfer time intervals vary depending on the manufacturer. The timings indicated in Chapter 9 should be used to avoid
faulty operation with a printer from a particular manufacturer.
5.2 Printing Multiple Sheets Continuously (Recommended)
Between 2 and 255 sheets can be printed continuously by an application. However, because this may take a long time,
the user should be given a means of halting a print job in progress.
5.3 Print Density (Recommended)
Because it is very inconvenient to adjust the density each time the program is started, the print density data should be
backed up whenever possible.
5.4 Operation After the Motor is Stopped (Required)
If a print instruction packet is sent within 100 msec of when the motor is stopped, the print starting position may be
incorrect. Therefore, print instruction packets should always be sent at least 100 msec after the motor is stopped.
5.5 Feeds (Required)
In setting the number of line feeds to be inserted before and after printing (byte 2 of the data portion of the print
instruction packet), always specify a value of 1 or greater for the number of feeds before printing and 3 or greater for the
number after printing. Otherwise, problems can arise, such as double printing twice on a single line or failure of the last
line of print to reach the paper cutter.
5.6 Point of Caution During Debugging (Recommended)
There are two types printers, each made by a different manufacturer (Seiko Instruments and Hosiden). As part of final
debugging, the program should be checked with at least one printer of each type.
5.7 Sample Program Provided by Nintendo (Recommended)
Modifying the program to suit the intended use is permitted. However, in creating the original program, values for timing
and other parameters were calculated to allow normal operation. These parameters must therefore be carefully
considered when modifying the program.
257
6. PROGRAMMING CAUTIONS FOR U.S. PROGRAMMERS

If you are unable to verify that the system is a Super Game Boy, and the Accumulator returns the same value if the
game is inserted in the Super Game Boy or original Game Boy hardware, follow the instructions below.
If your game is Super Game Boy (SGB) enhanced, then you just need to use the MLT_REQ function. Otherwise, you
must use the SGB libraries to verify if the game is in an SGB. (These libraries are located in the CGB files section of
Wario World under SGBlib.zip.) You will need to call the SGBCHK function from these libraries right after the Soft Reset
label. To use this function, you must set the ROM Registration area for SGB ($146h) to $03, which allows access to the
SGB REgisters. (Don't forget to readjust the Complement Check.)
Also, on the Software Submission sheet, make sure you note that the game has a $03 in address $146, but in the
remarks section, explain that the game doesn't use any of the SGB features.
258
260
Appendix 2: Register and Instruction Set Summaries
261
262
263
264
265
266
267
268
269
270
271
272
273
274
Appendix 3: Software Submission Requirements
APPENDIX 3: SOFTWARE SUBMISSION REQUIREMENTS ............ 276

1. The Software Submission Process ............................................. 276
2. Items Required for Submission ................................................... 276
3. Software Verification..................................................................... 277
4. Licensee Game Play Videotape Pass/Fail Guidelines................ 278
5. Licensing Screen Information Pass/Fail Guidelines .................. 278
6. Common Problems ....................................................................... 279
7. A Note on Objectionable Material ................................................ 280
8. Software Submission Checklist ................................................... 281
9. Instructions For Software Specification Sheet........................... 282
10. Character Code List For Game Title Registration .................... 287
11. ROM Registration Data Specification ........................................ 288
11.1 Description of ROM Registration Data ............................................... 289
12. Storing Data to the Floppy Disk ................................................. 293

13. Production Software Selection .................................................. 294
14. Development Software Selection............................................... 295
15. Game Content Guidelines........................................................... 297
16. Game Boy Price Quote Request Form ...................................... 298
275
APPENDIX 3: SOFTWARE SUBMISSION REQUIREMENTS
1. THE SOFTWARE SUBMISSION PROCESS

All software submissions to Nintendo of America Inc. must be forwarded to the attention of NOA Product
Testing Supervisor. Otherwise, the submission’s placement into the testing queue may be delayed. To
help reduce a submission’s turn-around time, it is suggested that licensees assign a primary contact
person for each software submission. All communications with NOA concerning a submission’s testing
status should be forwarded through this individual. The contact person should also be responsible for
notifying any other interested parties.
When a submission is approved, your company's primary contact will be notified immediately in writing.
When a submission is not approved, NOA may send a videotaped copy of the programming problem(s)
which prevent(s) the submission from being approved. This is intended to assist the licensee in
analyzing the cause of the software problem. It is the licensee’s responsibility to send a copy of this tape
to any developer(s) of the software. NOA strongly encourages that copies be sent to the software
developer(s) as quickly as possible.
Software submissions should be sent to the following address:
Nintendo of America Inc.
Attn: Product Testing Supervisor
4820 150th Avenue NE
Redmond, WA 98052
Phone: (425) 861-2674
Fax: (425) 882-3585
2. ITEMS REQUIRED FOR SUBMISSIONS

The following items must be submitted with each Game Boy software submission.
Specification Sheet and Check List

The appropriate Software Specification sheet and the Software Submission Checklist must be filled out
completely and must be correct for the particular program version.
ROM Data
A copy of the ROM data must be submitted in binary format on MS-DOS® 3.5 inch disk(s). The size of
the file must be equal to the size of the EP-ROM (i.e., one 4 Meg EP- ROM = one 4 Meg file). Please
label each disk and include a description of its contents. (See “Storing Data to the Floppy Disk” below.)
Note For software that supports communications, when communications are

delayed for more than one hour after the game starts, in addition to the
above items, you must submit one set of boards with EP-ROM (or a flash
board) in which the game has been advanced to the point where
communication can take place.
Game Play Videotape/Rating Certificate

A video tape containing complete game play is required unless the product has been rated by the
Entertainment Software Ratings Board (ESRB). If the product has been rated by the ESRB, then a copy
of the rating certificate must accompany the submission and no video tape is needed.
276
Screen Text
A printed copy of the complete screen text must be submitted.
Instruction Manual
One copy of the instruction manual must be included with your game submission. If, at the time of
submission the manual is not complete, (submitted as an intermediate version) then you must submit a
list of known bugs.
Note If any of these items are not satisfied, the program will be rejected and will
not be submitted into the approval process until all criteria are met.
3. SOFTWARE VERIFICATION
The following verification process will significantly improve the probability of approval of your software.
1. The licensing screen on all submissions should state “LICENSED BY NINTENDO”.
2. Confirm the Licensing Screen information is correct.
3. Check the spelling on the Licensing Screen and Title Screen, as well as the spelling and
grammar on the screen text.
4. Confirm the use of a TM (™), circle R (), or circle C () where applicable.
5. Run a “Bypass” Test to assure that when the game is powered up, the Licensing Screen is
visible for at least one second, even if any combination of controller buttons are pressed
repeatedly. Also “Power-up” the software repeatedly to assure it does so without
programming failures.
6. Game characters should be moved in all possible directions or positions, regardless of
whether it is required to play the game properly. For instance, if the game does not require
going to a particular area to complete the game, go there anyway to assure there are no
programming problems in going to that location.
7. The software should be paused many times during the test, as this often causes
programming problems to surface.
8. All testing should be recorded onto a videotape, making it easier to review programming
problems.
9. The entire attract mode (demo) should be viewed to assure there are no programming
problems.
10. Routines designed to assist the programmer or developer in “debugging” the software
should be removed from the game prior to submission. This includes routines to determine
hardware type.
277
11. A Game Boy Color dedicated game must include a hardware check upon power-up, which
will display the following message when it is connected to a device other than Game Boy
Color. The official game title must also be displayed in the upper portion of the display
screen.
--<Game Title>--
"This game can only be played on Game Boy Color"
4. LICENSEE GAME PLAY VIDEOTAPE PASS/FAIL GUIDELINES

1. The licensee game play videotape (if included) must be recorded on a VHS tape, Standard
Play speed (SP) for clarity.
2. No editing of the tape is allowed.
3. If more than one tape is needed to show the entire piece of software, then when a second
tape begins it must show that the player is in the exact same place as where the first tape
left off.
4. No codes or “built-up” characters are allowed.
5. All levels or areas must be completed, in succession.
6. Screen text must have correct grammar and spelling.
7. No deviations from NOA Software Standards Policy may be present.
8. The entire ending credits (if any) must be shown.
9. If the product has been rated by the ESRB, then a copy of the rating certificate must
accompany the submission and no videotape is needed.
5. LICENSING SCREEN INFORMATION PASS/FAIL GUIDELINES

The following Licensing information should be included for all software. This can be displayed on one
(1) or two (2) screens.
1. Licensee’s software title.
2. Licensee’s trademark and copyright notice
(_ 19__ Licensee’s name or copyright owner)
3. LICENSED BY NINTENDO
Example
Tom’s Golf or 
 1992 ABC Corporation
LICENSED BY NINTENDO
If a blank screen appears for more than two seconds when powered up, Nintendo suggests placing a
message or graphic on the screen so that consumers do not think their game is inoperable (e.g., --
“Please Wait”--). If a blank screen appears for more than five seconds during game play, a message or
graphic should also be placed on the screen.
278
6. COMMON PROBLEMS
Some possible problems that may prevent approval of your software include, but are not limited to the
following:
1. Software locks up.
2. Scrambled blocks or characters appear on the screen.
3. The software won’t pause.
4. Your character can get stuck somewhere with no possible way to get out.
5. Scrambled graphics at the edges of the screen when the screen scrolls in any direction.
6. Vowels in the passwords or password entry-system.
7. Colored lines at the top or bottom of the screen.
8. Shifting of the screen in any direction.
9. Inconsistent scoring methods.
10. Flashes on screen.
11. Small flickering lines on the screen.
12. Hit or be hit by an enemy but no damage is incurred.
13. Three (3) or four (4) player game can be started without using a four player adapter.
14. Incorrect Licensing Screen; “Licensed by Nintendo” should appear for all formats.
15. Violation of any Programming Cautions in the product programming manual.
16. Communication problems on two-player linkable DMG games.
17. Horizontal or vertical black lines when switching between screens on DMG games.
18. Use of the Nintendo logo or representations of Nintendo products in software without
license agreement.
19. The use of the term Super Nintendo or Nintendo when the Super Nintendo Entertainment
System or Nintendo Entertainment System is the intended reference, respectively. Use of
any term other than Nintendo 64 or N64 when the Nintendo 64 Entertainment System is the
intended reference.
20. Character actions are inconsistent (for instance, a character that cannot fly, being able to
walk off the edge of a platform and stand in midair).
21. Referring to the Nintendo Control Pad or Control Stick by an unacceptable term, such as;
“joypad”, “directional control”, etc.
22. Referring to the Nintendo Controller by an unacceptable term, such as; “joystick”, etc.
23. Referring to the Nintendo Game Pak by an unacceptable term, such as; “Game Cassette”,
etc.
24. Referring to the Game Boy Game Link by an unacceptable term, such as; “Video Link”, etc.
Note If Licensor approval is required, please assure that this has been finalized
before the software submission has been made.
279
7. A NOTE ON OBJECTIONABLE MATERIAL

A copy of the Nintendo “Game Content Guidelines” is included at the end of this document. If you are
unsure of whether an item of text or element of a game is within Nintendo Software Standards, you may
contact our Engineering Department early in the development process and they will discuss
questionable items over the phone. In cases concerning an extensive amount of text, please send it to
the attention of NOA Product Testing Supervisor, at the address listed in below, with the questionable
items highlighted. The material will be evaluated and you will be contacted within a week to ten days.
Nintendo of America Inc.

Attn: Product Testing Supervisor
4820 150th Avenue NE
Redmond, WA 98052
Phone:(425) 861-2674
Fax: (425) 882-3585
280
8. SOFTWARE SUBMISSION CHECKLIST
Note This checklist must be included with the software submission. If any of the
items are not satisfied, the program will be promptly returned and will not
be submitted into the approval process until all criteria are met.
281
9. INSTRUCTIONS FOR SOFTWARE SPECIFICATION SHEET

1. Game Title
Print the planned name for the game. You may use up to 11 characters.
2. Game Code
Print the product code designated by Nintendo. Use “CGB-P-” for CGB-dedicated soft-
ware (software that will not operate on a conventional Game Boy). Otherwise, use
“DMG-P-”.
3. Language
Indicate the primary language used for messages, etc. in the game.
4. DMG Communication Mode
Indicate whether the software has a function which uses an external expansion connector
for Game Boy (or Super Game Boy), like a Game Boy communication cable.
5. Software Type
Indicate whether the game being submitted is DMG exclusive, DMG/CGB compatible, or
CGB exclusive.
6. CGB-related Functions
Check the following items, as appropriate, if you selected "DMG/CGB compatible" or
"CGB exclusive" in item 5.
a. Serial Transfer Speed (check all that apply)
Check all corresponding communication speeds.
b. High Speed ROM Required?
A high speed ROM is required if CPU double-speed mode (Key 1),
horizontal blanking DMA, or general DMA is used.
Note: These 3 functions cannot be used in MBC-1, 2, and 3.
c. IR Communications
If the software has CGB infrared communications capabilities, please
indicate whether the function involves communications with the same
game or with a different game. If you select “different game,” include the
game title in the parentheses.
7. Overseas Version
If the game has been, or will be, sold in another country; indicate the product title and
product code.
8. Contact
Provide the company name, department, address, phone number, fax number, and the
name of a representative that Nintendo should contact with all questions or comments
about the product.
282
9. Submission Date
Provide the submission date and select the method used for submission.
10. Scheduled Release Date
Provide the scheduled release date for the game.
11. ROM Registration Data
Provide the contents registered in the indicated addresses of the master ROM. Refer to
“ROM Registration Data Specification” for details. Enter the ASCII code for the charac-
ters in areas marked with parenthesis “( )”.
12. Game Title Registration
Enter the game title registered in the master ROM using ASCII characters and their
ASCII codes. Also enter the Game Code assigned by Nintendo. Refer to “Character
Code List for Game Title Registration” for these entries.
13. Memory Controller
Indicate the type of memory controller used for this game. If no Memory Controller is
used, mark None.
14. Memory Configuration
Indicate the memory configuration of the game, as follows.
♦ ROM: Indicate the ROM size.
♦ RAM: Indicate whether or not work RAM is installed in the
Game Pak. If work RAM is installed, indicate whether it is
used as an expansion device or contained inside an
MBC. If it is used as an expansion device, indicate the
size of the RAM in the location provided. Also indicate if
work RAM
requires data back-up (battery). When the MBC-3 Clock
Counter function is used, check "Yes" for "Data Back-up",
regardless of which box is checked for "RAM".
283
15. ROM Version

Mask ROM Version
♦ Indicate “0” if submitting the first version of the game.
♦ Indicate the next higher number for each revised version after starting
production.
Submission ROM
♦ Indicate “0” for the first submission
♦ Indicate the next higher number each time the game contents change
without updating the Mask ROM version.
284
Example:
16. File Name and Check Sums

Print the file name on each disk using the following format: *** **-*.GB
Example:
Note: The first disk will be numbered “0.”
If the Initial code is 3 digits (prior to 1994), include an under bar (“_”) after the Initial code to bring it to 4
digits. The file name would appear as follows: “AAJ_10-0.GB”
Enter the check sum of each ROM submitted. To calculate the check sum, add each byte in the ROM
data. The lower 2 bytes of the resulting value is the check sum. Enter the check sum for each ROM
submitted for the master program and the total of their individual check sums. The total is calculated by
adding the individual check sums. This method of calculation is different from the check sum on the
ROM Registration Specification.
285
17. Programming Features

Indicate if special programming is implemented for a specific purpose, such as copy pro-
tection. If special programming is implemented, it must be explained in writing.
If the software is N64 GB Pak compatible, indicate the name of the N64 game and its
product code. (N64 GB Pak is a peripheral device that allows the N64 system to read
data from and write to a standard Game Boy Game Pak. This device is not marketed in
the U.S. For more information, please contact Nintendo Technical Support.)
18. SGB Support
If the software is designed to use Super Game Boy (SGB) functions, check “Yes.” If the
software is not specifically designed to use Super Game Boy functions, but will run on
SGB, indicate ‘No.”
If you checked "Yes" for SGB Support, the SGB Function Code (address 0146H) should
contain "03H". If you checked "No", the data contained in address 0146H should read
"00H".
Also, if you checked "Yes" for CGB Support, complete the following 3 items. Do not
make any marks in these boxes if you checked "No".
a. SGB Support Marking
Check "Yes", if the SGB compatability marking needs to be displayed on
product packaging. Otherwise, check "No".
b. SGB Competition Mode
Indicate whether the game contains a multi-player function for SGB, by
checking the appropriate box.
c. Program Transfer to Super NES
Indicate whether or not the program is transferred to the S-CPU for
execution as a unique program on the Super NES.
286
10. CHARACTER CODE LIST FOR GAME TITLE REGISTRATION
287
11. ROM REGISTRATION DATA SPECIFICATION

Enter information regarding the game title and Game Boy software specifications at the
indicated addresses in ROM.
The ROM registration data address is 80 bytes of CPU memory (0100H ~ 014FH).
ROM registration data is stored using the following format.
Note The following data will be stored in Game Boy Memory for all Game Boy
software.
0100H = 00H
0101H = C3H
014BH = 33H
0104H~0133H = “Nintendo” character data
288
11.1 Description of ROM Registration Data

1. Start Address (0102H, 0103H)
The Game Boy (Super Game Boy) program starts after Initial Program Load (IPL) is run
on the CPU. The low byte of the starting address is stored first, then the high byte.
2. “Nintendo” Character Data (0104H~0133H)
Register the character pattern of “Nintendo” to be displayed when the Game Boy is
turned on. The following hexadecimal data must be store since IPL verifies it when the
program begins.
3. Game Title (0134H~013EH)
Store the game title (up to 11 characters) using ASCII code. The table “Character Code
List for Game Title Registration” is provided for your convenience. Use code 20H for a
space and code 00H for all unused areas in the game title. Please use only those
characters listed in the provided table when registering a game title. The game title
registered should be close to the title under which the game will be marketed. Please do
not register a tentative name which is used for development.
4. Game Code (013FH~0142H)
Store the 4 character game code, assigned by Nintendo, using ASCII code from the table
used in item 3. Please use only "upper case" letters, listed in the provided table, when
registering a game code.
Example:
When the Game Code is "APCJ", the following codes would be
stored.
41H('A') → Address 013FH
50H('P') → Address 0140H
43H('C') → Address 0141H
4AH('J') → Address 0142H
This requirement only applies to new titles. If the program is changed and a master ROM
resubmitted for a game title which has already been marketed, it is not necessary to
insert a game code for this submission. (If the Game Code is added to an existing game,
please be aware of potential problems with software verification routines in serial
communication protocols or GB Pak routines. For example, the Game Titles for the old
version and the new version MAY be different, causing the new version to be
unrecognized by the software verification routine.)
289
5. CGB Support Code (0143H)

Store the code which distinguishes between games that are CGB (Game Boy Color)
compatible, and those that are not.
Address 143H Denotation

00H CGB Incompatible
80H CGB Compatible
C0H CGB Exclusive
CGB Incompatible: A program which does not use CGB functions, but
operates with both CGB and DMG (Monochrome).
CGB Compatible: A program which uses CGB functions, and operates with
both CGB and DMG.
CGB Exclusive: A program which uses CGB functions, but will only operate
on a Game Boy Color unit (not on DMG/MGB). If a user
attempts to play this software on Game Boy, a screen must
be displayed telling the user that the game must be played
on Game Boy Color.
6. Maker Code (0144H, 0145H)
Enter the 2-digit ASCII code assigned by Nintendo. Contact Product Testing, if in doubt.
All letters must be in upper case. For example;
If Maker Code is 01, the ASCII code for 0 (30H) is stored at 0144H and the
ASCII code for 1 (31H) is stored at 0145H.
If Maker Code is FF, the ASCII code for F (46H) is stored at 0144H and
0145H.
7. SGB Support Code (0146H)

Store the Function Code for the game program. Use the table below.
0146H Super Game Boy Function

00H Game Boy (will also run on Super Game Boy)
03H Uses Super Game Boy Functions
Note In order to use Super Game Boy functions, the following data must be
registered.
0146H = 03H and 014BH = 33H
290
8. Cartridge Type (0147H)

Store the appropriate code for the type of cartridge (Game Pak parts configuration) being
used.
Parts Configuration
Address MBC-3 MBC5 Backup
0147H Battery
ROM MBC-1 MBC-2 SRAM
W/ No No W/
RTC RTC Rumble Rumble
00H X
01H X X
02H X X X
03H X X X X
04H
05H X X
06H X X X
07H
08H X X
09H X X X
0FH X X X
10H X X X X
11H X X
12H X X X
13H X X X X
19H X X
1AH X X X
1BH X X X X
19H X X
1AH X X X
1BH X X X X
291
9. ROM Size (0148H)

Store the code for the program ROM size from the table below.
0148H ROM Size

00H 256 KBit
01H 512 KBit
02H 1 MBit
03H 2 MBit
04H 4 MBit
05H 8 MBit
06H 16 MBit
07H 32 Mbit
08H 64 Mbit
10. External RAM Size (0149H)

Store the code for the size of external RAM installed in the cartridge.
Address 149 RAM Size

00H No RAM or MBC2
01H -------
02H 64 KBit
03H 256 KBit
04H 1 Mbit
11. Destination Code (014AH)

Store the code from the table below which indicates where the product will be marketed.
Address 147 Destination

00H Japan
01H All Others
12. Mask ROM Version N0. (014CH)

The mask ROM version number starts from 00 and increases by 1 for each revised
version sent after starting production.
292
13. Complement Check (014DH)

After all the registration data has been entered (0134H~014CH), add 19H to the sum of
the data stored at addresses 0134H through 014CH and store the complement value of
the resulting sum.
(0134H) + (0135H) +...+ (014CH) + 19H + (014DH) = 00H
14. Check Sum Hi and Lo
The check sum, excluding the value of 014EH and 014FH, is stored here.
Check sum Hi and Lo will be different from the Total Check Sum.
014EH = Upper
014FH = Lower
12. STORING DATA TO THE FLOPPY DISK

1. Use MS-DOS® 3.5 inch, 2HD disk(s).
2. The data must be submitted in binary (ROM) format. Do not compress the data. The
maximum amount of data stored on each floppy should be 8Mbit.
3. The file name should be formatted as described in item #16 of "Instructions for Game Boy
Software Specification Sheet - File Name and Check Sums.”
4. Place a label describing the content of each disk as shown below.
Company name: Nintendo Co., Ltd.

Product name: Mario’s Pikurosu
Product code: DMG-P-APCJ (JPN)
File name: APCJ00-0.GB
Check sum: ABCD
Date: 1998/8/1
293
13. PRODUCTION SOFTWARE SELECTION
ROM SIZE 256K 512K 1M 2M 4M 8M 16 32 64M Comments

M M
MBC SRAM SIZE
None None
64K With or without backup battery

*1 *1
MBC-1 None
*1 *1
MBC-2 None With backup battery only
MBC-3 None With backup battery only
W/RTC 64K With backup battery only
256K With backup battery only
MBC-5 None ( )*2 ( )*2 ( )
64K ( )*2 ( )*2 ( ) With or without backup battery

256K ( )*2 ( )*2 ( )*2 ( ) With or without backup battery
1M ( )*2 ( )*2 ( )*2 ( ) With or without backup battery
MBC-5/ None ( )*2 ( )*2 ( )*2 ( )
Rumble 64K ( )*2 ( )*2 ( )*2 ( ) With or without backup battery
256K ( )*2 ( )*2 ( )*2 ( ) With or without backup battery
: Board Available
If a price quote is necessary, please submit a "Game Boy Price Quote Request Form" to NOA Licensing Dept.
: Board Not Available
If required, please submit a "Game Boy Price Quote Request Form" to NOA Licensing Dept., approximately 5 months
before scheduled software submission.
( ) : At the present time, a mask ROM cannot be prepared. If necessary, please contact NOA Licensing Dept.
[Notes] MBC-1, 2, and 3 do not support Game Boy Color double-speed mode (including H-DMA and General Purpose DMA. Please refer to your Programming Manual.
*1 There are some restrictions in memory mapping when MBC-1 ROM Size is 8M or larger. Please refer to "Memory Controllers" in your Programming Manual.
*2 For MBC-5 with ROM of 1M or less, a mask ROM supporting CGB double-speed mode can not be prepared. Double-speed mode is supported by ROM of 2M or larger.
294
14. DEVELOPMENT SOFTWARE SELECTION

ROM SIZE 256K 512K 1M 2M 4M 8M 16M 32M Comments
MBC SRAM SIZE
None None 1
None 2 3
MBC-1 4 • Built-in 64K SRAM
With or without backup battery
64K/None 5 6
256K/64K/None • Built-in 256K SRAM
7 With or without backup battery
MBC-2 None 8
MBC-3 256K/64K/None • RTC Function
9 • Built-in 256K SRAM
1M/256K/64K/None • Built-in 32M Flash ROM

10 • Built-in 1M SRAM
MBC-5 With or without backup battery
256K/64K/None • Built-in 32M Flash ROM

11 • Rumble Function
• Built-in 256K SRAM
Product Names (*1) Memory Specifications (*2) Comments

Board Name Product Code
1 DMG-256K-EPROM E200225 EPROM : 27C256
2 MBC1-512K-EPROM E200241 EPROM : 27C512
3 MBC1-1M to 2M-EPROM E200233 EPROM : 27C101/27C2001 (Can use 301 type) (*3)
4 MBC1-1M to 2M-EPROM+64K E200530 EPROM : 27C101/27C2001/27C4001

EPROM not included
5 MBC1-Multichecker E200191 EPROM : 27C256/27C512/27C101/27C301
6 MBC1-4M to 16M-EPROM+64K E200654 EPROM : 27C4001
7 MBC1-1M to 4M-EPROM+256K E200605 EPROM : 27C101/27C2001/27C4001
8 MBC2-1M to 2M-EPROM E200258 EPROM : 27C101/27C2001 (Can use 301 type) (*3)
9 MBC3-4M-ROM2-256K E201025 EPROM : 27C101/27C2001/27C4001/27C8001
295
Product Names (*1) Memory Specifications (*2) Comments

Board Name Product Code
10 DMG-MBC5-32M-FLASH E201264 Built-in 32M Flash Memory + 1MRAM Requires DMG Falsh ROM
Gang Writer or CGB
11 DMG-MBC5-32M-R-FLASH E201272 Built-in 32M Flash Memory (with Rumble Pak) +256KRAM Emulator
[Notes] MBC-1, 2, and 3 do not support Game Boy Color double-speed mode (including H-DMA and General Purpose DMA. Please refer to your Programming Manual.
There are some restrictions in memory mapping when MBC-1 ROM size is 1M or larger. Please refer to "Memory Controllers" in your Programming Manual.
*1 : When ordering, please indicate both the board name and product code to NOA Licensing Dept.
*2 : For the EPROM specification, please use the described specification, above, or something with the same pin configuration.
*3 : Can support both types for land switching on the board.
296
15. GAME CONTENT GUIDELINES

The following Game Content Guidelines are presented for assistance in the development of authorized
game paks (i.e., both Nintendo and licensee game paks) by defining the types of themes inconsistent
with Nintendo’s corporate philosophy. Exceptions may be made when an objectional item is necessary
to maintain the integrity of the product or the games’ theme. Nintendo will only approve products (i.e.,
audio-visual work, packaging and instruction manuals) which do not:
• contain sexually explicit content including but not limited to nudity, rape, sexual intercourse and
sexual touching; for instance, Nintendo does not allow bare-breasted women in its games, however,
mild displays of affection such as kissing or hugging are acceptable.
• contain language or depictions which specifically denigrate members of any race, gender, ethnicity,
religion or political group.
• depict gratuitous or excessive blood or violence. Nintendo does not permit depictions of animal
cruelty or torture.
• depict verbal or physical spousal or child abuse.
• permit racial, gender, ethnic, religious or political stereotypes; for example religious symbols such
as crosses will be acceptable when fitting into the theme of the game and not promoting a specific
religious denomination.
• use profanity, obscenity or incorporate language or gestures that are offensive by prevailing public
standard and tastes.
• promote the use of illegal drugs, smoking materials, tobacco and/or alcohol; for example Nintendo
does not allow an unnecessary beer or cigarette advertisement anywhere in a product, however
Sherlock Holmes smoking a pipe would be acceptable as it fits the theme of the game.
297
16. GAME BOY PRICE QUOTE REQUEST FORM

Please FAX this form to Nintendo of America Inc., Attn.: Juana Tingdale, Licensing Department, (206)
861-2173.
298

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PROGRAMMING MANUAL

This document contains confidential and proprietary information of

 1999 Nintendo of America Inc.

TM and  are trademarks of Nintendo

The abbreviations used in this manual represent the following:

Note: Where it is not necessary to distinguish between the different monochrome

SGB: Super Game Boy, introduced on June 14, 1994

THIS PAGE WAS INTENTIONALLY LEFT BLANK.

NINTENDO GAME BOY COLOR SOFTWARE PRE-APPROVAL

◊ Differentiation - If a game is to be considered CGB-compatible, then it must appear significantly

• Game Concept content

• Interim ROM Submissions

• Game Pak Configuration & Game Type

THIS PAGE WAS INTENTIONALLY LEFT BLANK.

CHAPTER 1: SYSTEM ............................................................ 10

Features common to DMG/CGB

Types of Game Pak Supported

Operating Modes (the following modes apply only to CGB)

2 CGB Mode (when using software supported or used exclusively by CGB )

Accessories (as of April 1999)

1.2 GAME BOY BLOCK DIAGRAM

1.3 MEMORY CONFIGURATION

Note Use of the area from 0xE000 to 0xFDFF is prohibited.

0xFE00 to 0xFFFF is allocated for CPU internal RAM.

0xFE00-0xFE9F: OAM-RAM (Holds display data for 40 objects)

1.4 MEMORY MAP

User Program Area

1.5 FEATURE COMPARISON

←: Same as in column at left

1.6 REGISTER COMPARISON

←: Same as in column at left

LCD Controller Functions

2.2 CPU BLOCK DIAGRAM

/RESET D0~D7 VDD GND TEST1,2

CPU Core ROM

OAM RAM Waveform Sound

SIO LCD Controller S

MD0~MD7 MA0~MA12 /MCS /MWR /MRD

Game Boy Color CPU

2.3 DESCRIPTION OF CPU FUNCTIONS

1 Horizontal Blanking DMA Transfer

2.4.1 Controller Data

VDD P14 P15

LD A, ($FF00) ; Register A ← Ports P10-P13

2.4.2 Divider Registers

2.4.3 Timer Registers

The main timer unit. Generates an interrupt when it overflows.

The value of TMA is loaded when TIMA overflows.

The timer consists of TIMA, TMA, and TAC.

LD A, 3 ;Select a count pulse of f/28

2.4.4 Interrupt Flags

Bit reset enabled

Interrupts are controlled by the IE (interrupt enable) flag.

The 5 types of interrupts are as follows.

Serial transfer completion 4 0x0058

P10-P13 input signal goes low 5 0x0060