2012 UKSim 14th International Conference on Computer Modelling and Simulation, 2012
The main objective of this paper is to design a novel threshold voltage detector circuit using ca... more The main objective of this paper is to design a novel threshold voltage detector circuit using carbon nanotube field effect transistor (CNTFET). This circuit is simulated in HSPICE by using HSPICE model of CNTFET. The uniqueness of this proposed circuit is that the threshold voltage of each CNTFET decides each voltage detection level where as in CMOS implementation a complex band-gap reference circuit is needed to produce a reference voltage level for precise detection. MOSFETs with different threshold voltage can also be used to implement this idea but that would add a new Vth mask for each different voltage detection level which will increase the process cost significantly. Therefore this new proposed CNTFET based voltage level detection circuit can produce much improved performance with significant reduction in implementation complexity by both saving number of mask set and reducing the chip area significantly.
This paper proposes a new design technique of a stable, low input impedance, high sensitivity, h... more This paper proposes a new design technique of a stable, low input impedance, high sensitivity, high gain and low-power Potentiostat using carbon nanotube FETs (CNTFETs) at 32 nm level that utilizes different input voltages for verifying voltage follower performance. The fully differential architecture suppresses the common mode interference. Extensive simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based Potentiostat due to variations in the supply voltage and temperature of the CNTFETs. The CNTFET-based Potentiostat demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.
This manuscript reports and analyzes
12-CNTFET and GDI CNTFET based full adder
implementation a... more This manuscript reports and analyzes 12-CNTFET and GDI CNTFET based full adder implementation at 32 nm level. As figures of merit, stability, power dissipation and Power Delay Product (PDP) are considered for the best overall performance. Intensive HSPICE simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based full adders. Both circuit has noticeable reduction in short current power consumption but in terms of comparison GDI CNTFET shows better performance in both power consumption and Power Delay Product (PDP) variations. The CNTFET-based One bit Full Adder cell demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.
2012 UKSim 14th International Conference on Computer Modelling and Simulation, 2012
The main objective of this paper is to design a novel threshold voltage detector circuit using ca... more The main objective of this paper is to design a novel threshold voltage detector circuit using carbon nanotube field effect transistor (CNTFET). This circuit is simulated in HSPICE by using HSPICE model of CNTFET. The uniqueness of this proposed circuit is that the threshold voltage of each CNTFET decides each voltage detection level where as in CMOS implementation a complex band-gap reference circuit is needed to produce a reference voltage level for precise detection. MOSFETs with different threshold voltage can also be used to implement this idea but that would add a new Vth mask for each different voltage detection level which will increase the process cost significantly. Therefore this new proposed CNTFET based voltage level detection circuit can produce much improved performance with significant reduction in implementation complexity by both saving number of mask set and reducing the chip area significantly.
This paper proposes a new design technique of a stable, low input impedance, high sensitivity, h... more This paper proposes a new design technique of a stable, low input impedance, high sensitivity, high gain and low-power Potentiostat using carbon nanotube FETs (CNTFETs) at 32 nm level that utilizes different input voltages for verifying voltage follower performance. The fully differential architecture suppresses the common mode interference. Extensive simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based Potentiostat due to variations in the supply voltage and temperature of the CNTFETs. The CNTFET-based Potentiostat demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.
This manuscript reports and analyzes
12-CNTFET and GDI CNTFET based full adder
implementation a... more This manuscript reports and analyzes 12-CNTFET and GDI CNTFET based full adder implementation at 32 nm level. As figures of merit, stability, power dissipation and Power Delay Product (PDP) are considered for the best overall performance. Intensive HSPICE simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based full adders. Both circuit has noticeable reduction in short current power consumption but in terms of comparison GDI CNTFET shows better performance in both power consumption and Power Delay Product (PDP) variations. The CNTFET-based One bit Full Adder cell demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.
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Papers by Habib Muhammad Nazir Ahmad
32 nm level that utilizes different input voltages for verifying
voltage follower performance. The fully differential architecture
suppresses the common mode interference. Extensive
simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based Potentiostat due to variations in the supply voltage and temperature of the CNTFETs. The CNTFET-based Potentiostat demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.
12-CNTFET and GDI CNTFET based full adder
implementation at 32 nm level. As figures of merit, stability,
power dissipation and Power Delay Product (PDP) are
considered for the best overall performance. Intensive HSPICE
simulations have been performed to investigate the distribution
of the power and delay of the CNTFET-based full adders. Both
circuit has noticeable reduction in short current power
consumption but in terms of comparison GDI CNTFET shows
better performance in both power consumption and Power
Delay Product (PDP) variations. The CNTFET-based One bit
Full Adder cell demonstrates that it tolerates the PVT (Process,
Voltage, and Temperature) variations significantly better than
its CMOS counterpart.
32 nm level that utilizes different input voltages for verifying
voltage follower performance. The fully differential architecture
suppresses the common mode interference. Extensive
simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based Potentiostat due to variations in the supply voltage and temperature of the CNTFETs. The CNTFET-based Potentiostat demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.
12-CNTFET and GDI CNTFET based full adder
implementation at 32 nm level. As figures of merit, stability,
power dissipation and Power Delay Product (PDP) are
considered for the best overall performance. Intensive HSPICE
simulations have been performed to investigate the distribution
of the power and delay of the CNTFET-based full adders. Both
circuit has noticeable reduction in short current power
consumption but in terms of comparison GDI CNTFET shows
better performance in both power consumption and Power
Delay Product (PDP) variations. The CNTFET-based One bit
Full Adder cell demonstrates that it tolerates the PVT (Process,
Voltage, and Temperature) variations significantly better than
its CMOS counterpart.