International Journal of Scientific and Engineering Research
With technological advancement in modern era, sizes of various tools used in various engineering ... more With technological advancement in modern era, sizes of various tools used in various engineering applications has become smaller and smaller. Especially, the field of microengineering has gained a tremendous impetus. Working at microlevel has been a challenging job in the field of engineering for quite some time. This paper proposes the design of a 3- dimensional microelectromechanical system (3-D MEMS) model of a inverse piezo- electrically actuated single pole- double throw switch. Inverse Piezoelectric actuation has the advantage of fast response and reasonable power consumption. This paper also focuses on the optimization of the structure which will yield the best possible switching displacement (more displacement) for a particular voltage applied to the piezo – material. We have used Finite Element Method (FEM) of COMSOL Multiphysics version 4.4 to analyze all the structures. Various models have been tried out, each being subjected to numerous dimensional, structural and materi...
This study proposes a spintronic based compact tunable nano-sized RF oscillator. The proposed des... more This study proposes a spintronic based compact tunable nano-sized RF oscillator. The proposed design provides parametric performance improvement as compared with the designs already reported in literature. This design also offers higher operating frequency up to range of several GHz, which can be tuned by a DC bias current. The proposed magnetic tunnel junction-spin torque oscillators (MTJ-STO) model overcomes the limitation of low output power which is prime issue in spin torque oscillators (STOs). This is achieved by employing multi-stage amplifier with impedance matching stages. In addition to that, mutual phase locking mechanism of STOs is introduced to act as a remedy for broadening of the spectrum linewidth, which is a critical issue in traditional oscillators. The hybrid model presented in this study contains spin torque based MTJ, which is compatible with CMOS technology. The modelling of proposed circuit has been done in Verilog-A and simulation results have been verified using HSPICE.
The development of modeling languages such as Verilog-HDL and Verilog-AMS allows the behavior of ... more The development of modeling languages such as Verilog-HDL and Verilog-AMS allows the behavior of analogue and mixed signal circuits to be described with a more lucid way as compared to the conventional circuit-level simulators. Mixed-signal simulators are thus providing a new platform for more efficient modeling of mixed signal that contains both the analogue and discrete features which was not previously possible. The non-linear characteristics of many circuits are still difficult to be exactly described by the conventional simulators. Hence it is required to explore the simulation behavior of analogue and mixed-signal circuits in a more efficient manner which can be done using mixed signal modeling languages. This paper presents an alternative approach to model the behavior of analogue and mixed-signal circuits based upon piecewise linear waveforms. A triangular waveform generator is modeled using the mixed signal modeling. The proposed model of triangular waveform generator can b...
2014 International Conference on Devices, Circuits and Communications (ICDCCom), 2014
ABSTRACT This paper presents SPICE modeling of Phase-change Random Access Memory (PCRAM). Differe... more ABSTRACT This paper presents SPICE modeling of Phase-change Random Access Memory (PCRAM). Different models of PCRAM have been already proposed but those models still lack capability to exactly model the behavior of PCRAM. In this paper we have introduced various physical parameters in the programming, to accurately model PCRAM behavior. The modeling of PCRAM cell has been done in Verilog-A and simulation results have been extensively verified using SPICE. Further, we have integrated the proposed model with the modified CNFET based read-write circuit. This paper emerges with the successful modeling of R-I characteristics of PCRAM. Read and write operations with proper programming pulses have also been demonstrated in this paper.
ABSTRACT This article presents a new way for designing a more reliable and variability resilient ... more ABSTRACT This article presents a new way for designing a more reliable and variability resilient 9T SRAM cell which is based on DTMOS (dynamic threshold MOS) and CCBB (cell content body bias) technique under subthreshold operation. Critical design metrics of SRAM cells are estimated at subthreshold region and compared with that of conventional 9T SRAM cell. The proposed 9T SRAM cell shows 41.8% (9.5%) lower read access time (write access time) compared to conventional 9T SRAM cell. It also exhibits robustness by achieving narrower spread in read access time (write access time) by 53.01% (8%) compared to its conventional 9T SRAM cell. Moreover, the proposed bitcell offers 9.5% (47.4%) improvement in read static noise margin (write static noise margin) @ 350 mV.
As the MOSFET‘s channel length is scaling down, SRAM stability becomes the major concern for futu... more As the MOSFET‘s channel length is scaling down, SRAM stability becomes the major concern for future technology. In this paper a fully differential 10T (FD10T) cell is proposed and its design metrics are compared with conventional 6T (CON6T) and conventional 10T (CON10T). The proposed cell shows better performance with respect to CON6T and CON10T. The cell depicts a shorter read delay and write delay compared to CON6T and CON10T. It also shows larger read current compared to rest of the cells. FD10T also shows 21.13% (12.3%) and 4.07% (6.01%) narrower spread in read current (read delay) compared to CON6T and CON10T.The proposed cell shows 4.67× and 1.37× higher read static noise margin (RSNM) and write static noise margin (WSNM) respectively than that of conventional 6T cell @ 400 mV.
Prodigious demand for fast performance-ultra low power electronic devices has insinuated the disc... more Prodigious demand for fast performance-ultra low power electronic devices has insinuated the discovery of circuit style that promises reduced propagation delay (tp), as well as low power dissipation (PWR). MOS current mode logic (MCML) style has emerged as a promising logic style that offers high speed of operation at the expense of acceptable power dissipation. This paper proposes a MCML full adder which employs a load controller circuit. It compares MCML full adder with hybrid-CMOS full adder in terms of various design metrics in superthreshold as well as subthreshold regions. MCML topology with load controller offers a high speed of operation and low power dissipation in superthreshold region. Same circuit arrangement, when operated in subthreshold region also delivers higher operating speed with ultralow power dissipation compared to its hybrid-CMOS counterpart. Power dissipation analysis established MCML based full adder more robust compared to its hybrid-CMOS counterpart. In particular, MCML full adder design achieves 3.77× (2.38×) improvement in propagation delay, 10.43× (3.45×) improvement in average power dissipation, 39.43× (8.21×) lower power-delay product (PDP) and 149.07× (19.55×) improvement in energy-delay product (EDP) in superthreshold (subthreshold) regions of operation at 16-nm technology node. The above results are also validated using TSMC’s industry standard 0.18-μm technology model parameters and a similar trend is observed in the design metrics of the MCML and hybrid-CMOS full adder circuits. In addition, noise performance of the above mentioned circuits is also carried out. It is observed that the noise induced by the hybrid-CMOS full adder is about 14× to that of the MCML full adder.
IEEE Transactions on Device and Materials Reliability, 2016
Higher noise tolerance, lower power consumption, and higher reliability are the major design metr... more Higher noise tolerance, lower power consumption, and higher reliability are the major design metrics for designing an SRAM cell. It is difficult to achieve an SRAM cell with stable operation at low voltage for low power consumption due to increasing variations in process, voltage, and temperature. It is proved that conventional 6 T fails to maintain its stability in scaled technology, particularly in deep-subthreshold regime. Furthermore, it does not support column bit-interleaving architecture. Therefore, it is very much prone to multibit soft error. In this paper, a double-ended read-decoupled ultralow-power 9-T SRAM cell (LP9T) is proposed, and the proposed cell supports the column bit-interleaving architecture. Because of read-decoupled technique, its noise tolerance is improved. To show the effectiveness of the proposed cell, it is compared with other recently published SRAM cells, namely, fully differential 8 T (FD8T), single-ended read-disturb-free 9 T (SEDF9T), and ultradynamic voltage scalable 10 T (UDVS10T). The proposed cell provides 1.2×/2.3× higher read current IREAD compared with UDVS10T/SEDF9T. Furthermore, LP9T shows 3.8×/11.6× improvement in read delay compared with FD8T/UDVS10T. The proposed cell achieves 3.9× higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with FD8T. Moreover, LP9T consumes 2.1×/2.1×/4.9× lower hold power HPower during hold mode compared with FD8T/UDVS10T/SEDF9T. The proposed cell also exhibits 1.5×/4.3×/1.25× narrower spread (i.e., more reliable) in IREAD/RSNM/HPower compared with UDVS10T/FD8T/SEDF9T. Furthermore, as the proposed cell supports bit-interleaving architecture, error checking and correction technique can be used to mitigate the issue related to multibit soft error. All these benefits are achieved by the LP9T at a cost of 1.17×/1.17×/1.25× longer write delay compared with FD8T/UDVS10T/SEDF9T.
Advances in Intelligent Systems and Computing, 2016
In this paper, a novel version of Ternary Magnetic-Content-Addressable Memory (TMCAM) is proposed... more In this paper, a novel version of Ternary Magnetic-Content-Addressable Memory (TMCAM) is proposed for a low-delay-write operation. This is attained from the connections of circuit and majorly due to the exceptional operational features of CAM integrated with MTJ. While the previous TMCAM required each one of the MTJ to be written separately, this model attempts to nullify the problem. Consequently, a reduction in delay by almost twice is obtained in comparison to the previous TMCAM with a 22 nm CMOS technology used for simulation purposes. This can be effectively employed in adaptive biomedical signal processing applications where writing is often and hence, delay cannot be compromised.
2015 Online International Conference on Green Engineering and Technologies (IC-GET), 2015
Emerging chip technologies employ power-off mode to reduce the power dissipation of chips. Non-vo... more Emerging chip technologies employ power-off mode to reduce the power dissipation of chips. Non-volatile SRAM (nvSRAM) enables a chip to store the data after power-off mode. This non-volatility can be achieved through memristor memory technology which is a promising emerging technology with unique properties such as high density, low-power and good-scalability. This paper provides a detailed study of memristor and proposes a memristor based 7T2M nvSRAM cell. This cell incorporates two memristors, which store the bit information present in the 6T SRAM cell, and a 1T switch, which helps to restore the previously written bit in situations of power supply failures, thereby making the SRAM non-volatile.
Advances in Intelligent Systems and Computing, 2016
As the technology scales down, the subthreshold leakage increases exponentially which leads to a ... more As the technology scales down, the subthreshold leakage increases exponentially which leads to a dramatic increase in static power consumption especially in nanoscale devices. Consequently, it is very important to understand and estimate this leakage current so that various leakage minimization techniques can be devised. So in this paper we attempt to estimate the subthreshold leakage current in an NMOSFET at 16, 22, 32 and 45 nm technology nodes. Various factors which affect the subthreshold leakage such as temperature, drain induced barrier lowering (DIBL) and other short channel effects have also been explored. All the measurements are carried out using extensive simulation on HSPICE circuit simulator at various technology nodes.
2015 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions), 2015
There is vast variation encountered in present circuits because of aggressive scaling and process... more There is vast variation encountered in present circuits because of aggressive scaling and process imperfections. So this paper deals with various D flip-flop circuits in terms of robustness and propagation delay. This work compares various known D flip-flop circuits and then identifies the circuit which is fastest as compared to others taken into consideration. Further, delay variability exhibited by circuits has been analyzed to test the immunity against PVT variations i.e. process, voltage and temperature. In this paper, we have investigated the output levels of various D flip-flop circuits. Push-pull isolation D flip-flop proves to be more efficient as compared to other circuits in terms of delay variability. The circuits have been simulated using 32-nm technology node on SPICE. The designs offering minimum delay and its variability are reported, to aid the designer in selecting the best design depending on specific requirements.
This paper makes profound investigation of thirteen different programmable and non-programmable d... more This paper makes profound investigation of thirteen different programmable and non-programmable delay elements. These circuits are capable of incorporating a certain amount of delay during signal processing while maintaining the signal integrity. Performance evaluation of these delay circuits is presented in terms of different design metrics to lay down comparison among these circuits. This work will help design engineers to select appropriate delay element based upon their specific requirements. Extensive simulations are carried out on SPICE using predictive technology model @ 16-nm technology node to verify the results.
2015 Fifth International Conference on Communication Systems and Network Technologies, 2015
This paper characterizes a high electron mobility transistor (HEMT) having an undoped AlN spacer ... more This paper characterizes a high electron mobility transistor (HEMT) having an undoped AlN spacer layer in the interface of AlGaN and GaN layers. Two-dimensional (2-D) electron gas layer at the interface plays an important role in defining the mobility of charge carriers and hence drain current of HEMT. Introduction of an AlN spacer layer between the AlGaN and GaN layers further causes an improvement in these characteristics. The output characteristics curve (IDS-VDS) and transconductance curves (IDS-VGS) are analyzed by simulating the structure using Silvaco Atlas. The proposed HEMT offers a sub threshold slope of 80 mV/decade and it is 1.53× lower than that of similar structure already reported in the literature.
At present SRAM cell is under renovation stage. Researchers are trying to propose an SRAM cell th... more At present SRAM cell is under renovation stage. Researchers are trying to propose an SRAM cell that withstands the ever-increasing PVT (process, voltage and temperature) variations and supports low-voltage operation even under subthreshold regime. In this article, a 10T SRAM cell based on DSBB and DTMOS techniques is proposed. This cell is identical to conventional 10T (CON10T) SRAM cell except the body bias connections of the FETs used in the design. This cell is operated in subthreshold region varying from 400 mV to 200 mV. The proposed cell offers 2.64× higher read current and 1.36× tighter spread in read current. It takes 38.04% shorter time to sense a particular data available at the storage nodes with 50.58% improvement in its distribution. The proposed cell benefits 19.48% of write delay and 3.33× tighter spread in write delay compared with its conventional counterpart. It also offers 2× improvement in its write-ability and 2.67× increment in read current to leakage current r...
International Journal of Scientific and Engineering Research
With technological advancement in modern era, sizes of various tools used in various engineering ... more With technological advancement in modern era, sizes of various tools used in various engineering applications has become smaller and smaller. Especially, the field of microengineering has gained a tremendous impetus. Working at microlevel has been a challenging job in the field of engineering for quite some time. This paper proposes the design of a 3- dimensional microelectromechanical system (3-D MEMS) model of a inverse piezo- electrically actuated single pole- double throw switch. Inverse Piezoelectric actuation has the advantage of fast response and reasonable power consumption. This paper also focuses on the optimization of the structure which will yield the best possible switching displacement (more displacement) for a particular voltage applied to the piezo – material. We have used Finite Element Method (FEM) of COMSOL Multiphysics version 4.4 to analyze all the structures. Various models have been tried out, each being subjected to numerous dimensional, structural and materi...
This study proposes a spintronic based compact tunable nano-sized RF oscillator. The proposed des... more This study proposes a spintronic based compact tunable nano-sized RF oscillator. The proposed design provides parametric performance improvement as compared with the designs already reported in literature. This design also offers higher operating frequency up to range of several GHz, which can be tuned by a DC bias current. The proposed magnetic tunnel junction-spin torque oscillators (MTJ-STO) model overcomes the limitation of low output power which is prime issue in spin torque oscillators (STOs). This is achieved by employing multi-stage amplifier with impedance matching stages. In addition to that, mutual phase locking mechanism of STOs is introduced to act as a remedy for broadening of the spectrum linewidth, which is a critical issue in traditional oscillators. The hybrid model presented in this study contains spin torque based MTJ, which is compatible with CMOS technology. The modelling of proposed circuit has been done in Verilog-A and simulation results have been verified using HSPICE.
The development of modeling languages such as Verilog-HDL and Verilog-AMS allows the behavior of ... more The development of modeling languages such as Verilog-HDL and Verilog-AMS allows the behavior of analogue and mixed signal circuits to be described with a more lucid way as compared to the conventional circuit-level simulators. Mixed-signal simulators are thus providing a new platform for more efficient modeling of mixed signal that contains both the analogue and discrete features which was not previously possible. The non-linear characteristics of many circuits are still difficult to be exactly described by the conventional simulators. Hence it is required to explore the simulation behavior of analogue and mixed-signal circuits in a more efficient manner which can be done using mixed signal modeling languages. This paper presents an alternative approach to model the behavior of analogue and mixed-signal circuits based upon piecewise linear waveforms. A triangular waveform generator is modeled using the mixed signal modeling. The proposed model of triangular waveform generator can b...
2014 International Conference on Devices, Circuits and Communications (ICDCCom), 2014
ABSTRACT This paper presents SPICE modeling of Phase-change Random Access Memory (PCRAM). Differe... more ABSTRACT This paper presents SPICE modeling of Phase-change Random Access Memory (PCRAM). Different models of PCRAM have been already proposed but those models still lack capability to exactly model the behavior of PCRAM. In this paper we have introduced various physical parameters in the programming, to accurately model PCRAM behavior. The modeling of PCRAM cell has been done in Verilog-A and simulation results have been extensively verified using SPICE. Further, we have integrated the proposed model with the modified CNFET based read-write circuit. This paper emerges with the successful modeling of R-I characteristics of PCRAM. Read and write operations with proper programming pulses have also been demonstrated in this paper.
ABSTRACT This article presents a new way for designing a more reliable and variability resilient ... more ABSTRACT This article presents a new way for designing a more reliable and variability resilient 9T SRAM cell which is based on DTMOS (dynamic threshold MOS) and CCBB (cell content body bias) technique under subthreshold operation. Critical design metrics of SRAM cells are estimated at subthreshold region and compared with that of conventional 9T SRAM cell. The proposed 9T SRAM cell shows 41.8% (9.5%) lower read access time (write access time) compared to conventional 9T SRAM cell. It also exhibits robustness by achieving narrower spread in read access time (write access time) by 53.01% (8%) compared to its conventional 9T SRAM cell. Moreover, the proposed bitcell offers 9.5% (47.4%) improvement in read static noise margin (write static noise margin) @ 350 mV.
As the MOSFET‘s channel length is scaling down, SRAM stability becomes the major concern for futu... more As the MOSFET‘s channel length is scaling down, SRAM stability becomes the major concern for future technology. In this paper a fully differential 10T (FD10T) cell is proposed and its design metrics are compared with conventional 6T (CON6T) and conventional 10T (CON10T). The proposed cell shows better performance with respect to CON6T and CON10T. The cell depicts a shorter read delay and write delay compared to CON6T and CON10T. It also shows larger read current compared to rest of the cells. FD10T also shows 21.13% (12.3%) and 4.07% (6.01%) narrower spread in read current (read delay) compared to CON6T and CON10T.The proposed cell shows 4.67× and 1.37× higher read static noise margin (RSNM) and write static noise margin (WSNM) respectively than that of conventional 6T cell @ 400 mV.
Prodigious demand for fast performance-ultra low power electronic devices has insinuated the disc... more Prodigious demand for fast performance-ultra low power electronic devices has insinuated the discovery of circuit style that promises reduced propagation delay (tp), as well as low power dissipation (PWR). MOS current mode logic (MCML) style has emerged as a promising logic style that offers high speed of operation at the expense of acceptable power dissipation. This paper proposes a MCML full adder which employs a load controller circuit. It compares MCML full adder with hybrid-CMOS full adder in terms of various design metrics in superthreshold as well as subthreshold regions. MCML topology with load controller offers a high speed of operation and low power dissipation in superthreshold region. Same circuit arrangement, when operated in subthreshold region also delivers higher operating speed with ultralow power dissipation compared to its hybrid-CMOS counterpart. Power dissipation analysis established MCML based full adder more robust compared to its hybrid-CMOS counterpart. In particular, MCML full adder design achieves 3.77× (2.38×) improvement in propagation delay, 10.43× (3.45×) improvement in average power dissipation, 39.43× (8.21×) lower power-delay product (PDP) and 149.07× (19.55×) improvement in energy-delay product (EDP) in superthreshold (subthreshold) regions of operation at 16-nm technology node. The above results are also validated using TSMC’s industry standard 0.18-μm technology model parameters and a similar trend is observed in the design metrics of the MCML and hybrid-CMOS full adder circuits. In addition, noise performance of the above mentioned circuits is also carried out. It is observed that the noise induced by the hybrid-CMOS full adder is about 14× to that of the MCML full adder.
IEEE Transactions on Device and Materials Reliability, 2016
Higher noise tolerance, lower power consumption, and higher reliability are the major design metr... more Higher noise tolerance, lower power consumption, and higher reliability are the major design metrics for designing an SRAM cell. It is difficult to achieve an SRAM cell with stable operation at low voltage for low power consumption due to increasing variations in process, voltage, and temperature. It is proved that conventional 6 T fails to maintain its stability in scaled technology, particularly in deep-subthreshold regime. Furthermore, it does not support column bit-interleaving architecture. Therefore, it is very much prone to multibit soft error. In this paper, a double-ended read-decoupled ultralow-power 9-T SRAM cell (LP9T) is proposed, and the proposed cell supports the column bit-interleaving architecture. Because of read-decoupled technique, its noise tolerance is improved. To show the effectiveness of the proposed cell, it is compared with other recently published SRAM cells, namely, fully differential 8 T (FD8T), single-ended read-disturb-free 9 T (SEDF9T), and ultradynamic voltage scalable 10 T (UDVS10T). The proposed cell provides 1.2×/2.3× higher read current IREAD compared with UDVS10T/SEDF9T. Furthermore, LP9T shows 3.8×/11.6× improvement in read delay compared with FD8T/UDVS10T. The proposed cell achieves 3.9× higher noise tolerance capability (i.e., read static noise margin (RSNM)) during read operation compared with FD8T. Moreover, LP9T consumes 2.1×/2.1×/4.9× lower hold power HPower during hold mode compared with FD8T/UDVS10T/SEDF9T. The proposed cell also exhibits 1.5×/4.3×/1.25× narrower spread (i.e., more reliable) in IREAD/RSNM/HPower compared with UDVS10T/FD8T/SEDF9T. Furthermore, as the proposed cell supports bit-interleaving architecture, error checking and correction technique can be used to mitigate the issue related to multibit soft error. All these benefits are achieved by the LP9T at a cost of 1.17×/1.17×/1.25× longer write delay compared with FD8T/UDVS10T/SEDF9T.
Advances in Intelligent Systems and Computing, 2016
In this paper, a novel version of Ternary Magnetic-Content-Addressable Memory (TMCAM) is proposed... more In this paper, a novel version of Ternary Magnetic-Content-Addressable Memory (TMCAM) is proposed for a low-delay-write operation. This is attained from the connections of circuit and majorly due to the exceptional operational features of CAM integrated with MTJ. While the previous TMCAM required each one of the MTJ to be written separately, this model attempts to nullify the problem. Consequently, a reduction in delay by almost twice is obtained in comparison to the previous TMCAM with a 22 nm CMOS technology used for simulation purposes. This can be effectively employed in adaptive biomedical signal processing applications where writing is often and hence, delay cannot be compromised.
2015 Online International Conference on Green Engineering and Technologies (IC-GET), 2015
Emerging chip technologies employ power-off mode to reduce the power dissipation of chips. Non-vo... more Emerging chip technologies employ power-off mode to reduce the power dissipation of chips. Non-volatile SRAM (nvSRAM) enables a chip to store the data after power-off mode. This non-volatility can be achieved through memristor memory technology which is a promising emerging technology with unique properties such as high density, low-power and good-scalability. This paper provides a detailed study of memristor and proposes a memristor based 7T2M nvSRAM cell. This cell incorporates two memristors, which store the bit information present in the 6T SRAM cell, and a 1T switch, which helps to restore the previously written bit in situations of power supply failures, thereby making the SRAM non-volatile.
Advances in Intelligent Systems and Computing, 2016
As the technology scales down, the subthreshold leakage increases exponentially which leads to a ... more As the technology scales down, the subthreshold leakage increases exponentially which leads to a dramatic increase in static power consumption especially in nanoscale devices. Consequently, it is very important to understand and estimate this leakage current so that various leakage minimization techniques can be devised. So in this paper we attempt to estimate the subthreshold leakage current in an NMOSFET at 16, 22, 32 and 45 nm technology nodes. Various factors which affect the subthreshold leakage such as temperature, drain induced barrier lowering (DIBL) and other short channel effects have also been explored. All the measurements are carried out using extensive simulation on HSPICE circuit simulator at various technology nodes.
2015 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) (Trends and Future Directions), 2015
There is vast variation encountered in present circuits because of aggressive scaling and process... more There is vast variation encountered in present circuits because of aggressive scaling and process imperfections. So this paper deals with various D flip-flop circuits in terms of robustness and propagation delay. This work compares various known D flip-flop circuits and then identifies the circuit which is fastest as compared to others taken into consideration. Further, delay variability exhibited by circuits has been analyzed to test the immunity against PVT variations i.e. process, voltage and temperature. In this paper, we have investigated the output levels of various D flip-flop circuits. Push-pull isolation D flip-flop proves to be more efficient as compared to other circuits in terms of delay variability. The circuits have been simulated using 32-nm technology node on SPICE. The designs offering minimum delay and its variability are reported, to aid the designer in selecting the best design depending on specific requirements.
This paper makes profound investigation of thirteen different programmable and non-programmable d... more This paper makes profound investigation of thirteen different programmable and non-programmable delay elements. These circuits are capable of incorporating a certain amount of delay during signal processing while maintaining the signal integrity. Performance evaluation of these delay circuits is presented in terms of different design metrics to lay down comparison among these circuits. This work will help design engineers to select appropriate delay element based upon their specific requirements. Extensive simulations are carried out on SPICE using predictive technology model @ 16-nm technology node to verify the results.
2015 Fifth International Conference on Communication Systems and Network Technologies, 2015
This paper characterizes a high electron mobility transistor (HEMT) having an undoped AlN spacer ... more This paper characterizes a high electron mobility transistor (HEMT) having an undoped AlN spacer layer in the interface of AlGaN and GaN layers. Two-dimensional (2-D) electron gas layer at the interface plays an important role in defining the mobility of charge carriers and hence drain current of HEMT. Introduction of an AlN spacer layer between the AlGaN and GaN layers further causes an improvement in these characteristics. The output characteristics curve (IDS-VDS) and transconductance curves (IDS-VGS) are analyzed by simulating the structure using Silvaco Atlas. The proposed HEMT offers a sub threshold slope of 80 mV/decade and it is 1.53× lower than that of similar structure already reported in the literature.
At present SRAM cell is under renovation stage. Researchers are trying to propose an SRAM cell th... more At present SRAM cell is under renovation stage. Researchers are trying to propose an SRAM cell that withstands the ever-increasing PVT (process, voltage and temperature) variations and supports low-voltage operation even under subthreshold regime. In this article, a 10T SRAM cell based on DSBB and DTMOS techniques is proposed. This cell is identical to conventional 10T (CON10T) SRAM cell except the body bias connections of the FETs used in the design. This cell is operated in subthreshold region varying from 400 mV to 200 mV. The proposed cell offers 2.64× higher read current and 1.36× tighter spread in read current. It takes 38.04% shorter time to sense a particular data available at the storage nodes with 50.58% improvement in its distribution. The proposed cell benefits 19.48% of write delay and 3.33× tighter spread in write delay compared with its conventional counterpart. It also offers 2× improvement in its write-ability and 2.67× increment in read current to leakage current r...
As the technology scales down, the subthreshold leakage increases
exponentially which leads to a ... more As the technology scales down, the subthreshold leakage increases exponentially which leads to a dramatic increase in static power consumption especially in nanoscale devices. Consequently, it is very important to understand and estimate this leakage current so that various leakage minimization techniques can be devised. So in this paper we attempt to estimate the subthreshold leakage current in an NMOSFET at 16, 22, 32 and 45 nm technology nodes. Various factors which affect the subthreshold leakage such as temperature, drain induced barrier lowering (DIBL) and other short channel effects have also been explored. All the measurements are carried out using extensive simulation on HSPICE circuit simulator at various technology nodes.
In this paper, a novel version of Ternary Magnetic-Content-Addressable
Memory (TMCAM) is proposed... more In this paper, a novel version of Ternary Magnetic-Content-Addressable Memory (TMCAM) is proposed for a low-delay-write operation. This is attained from the connections of circuit and majorly due to the exceptional operational features of CAM integrated with MTJ. While the previous TMCAM required each one of the MTJ to be written separately, this model attempts to nullify the problem. Consequently, a reduction in delay by almost twice is obtained in comparison to the previous TMCAM with a 22 nm CMOS technology used for simulation purposes. This can be effectively employed in adaptive biomedical signal processing applications where writing is often and hence, delay cannot be compromised.
The impact of process, voltage and temperature
(PVT) variations on the open circuit voltage gain ... more The impact of process, voltage and temperature (PVT) variations on the open circuit voltage gain of CS amplifier is investigated and appropriate aspect ratios are calculated so as to minimize the effect of threshold voltage modulation in short channel devices. The dependence of transconductance (gm) on the variations and its nature in both saturation as well as triode region is also determined. Finally, the influence of gate bias on the equivalent output resistance of the amplifying transistor is modeled and corresponding expressions for gain are derived. All simulation results have been extensively verified using CADENCE Virtuoso Analog Design Environment @ 45-nm technology node.
This paper examines device sizing of CMOS inverter circuit at 22-nm Technology node using predict... more This paper examines device sizing of CMOS inverter circuit at 22-nm Technology node using predictive technology model in deep subthreshold region. Channel length (L) of the device is resolved to obtain optimized threshold voltage @ supply voltage of 150 mV. Aspect ratio of Inverter logic gate is determined for the same supply voltage. Symmetrical transient response analysis is performed. It is found that the inverter logic gate is symmetric when aspect ratio (β) is equal to 3.71. Minimum propagation delay is found and observed that high performance circuit design is achievable for higher β ratios. At L= 66 nm, optimum threshold voltage is obtained. Minimum energy point (MEP) is also obtained at β ratio of 3.71 at 122 mV.
This article presents a low power and highly stable
source feedback SE7T (single-ended 7T) SRAM c... more This article presents a low power and highly stable source feedback SE7T (single-ended 7T) SRAM cell. Using Monte-Carlo simulations critical design metrics of proposed SE7T SRAM cell are estimated and the estimated results are compared with that of conventional 6T SRAM cell. The proposed source feedback (SE7T) SRAM cell provides 2 times improvements in Read Access Time (TRA) and 40 times and 1.17 × lower write power and hold power at 800 mv respectively. The proposed bit cell also provides 1.67 times higher RSNM (read static noise margin) as compared to CON6T SRAM Cell. This proves its higher stability.
This paper proposes an ultra-low voltage charge
pump circuit working at an input voltage as low a... more This paper proposes an ultra-low voltage charge pump circuit working at an input voltage as low as 100 mV. Most of the micro energy sources work typically in the voltage range of 100 mV. The proposed circuit provides an output voltage of 1 V which is sufficient enough to power low energy-consuming portable devices, biomedical applications such as body sensor networks and remote area monitoring wireless sensing networks.
Emerging chip technologies employ power-off
mode to reduce the power dissipation of chips. Non-vo... more Emerging chip technologies employ power-off mode to reduce the power dissipation of chips. Non-volatile SRAM (nvSRAM) enables a chip to store the data after power–off mode. This non-volatility can be achieved through memristor memory technology which is a promising emerging technology with unique properties such as high density, low-power and good-scalability. This paper provides a detailed study of memristor and proposes a memristor based 7T2M nvSRAM cell. This cell incorporates two memristors, which store the bit information present in the 6T SRAM cell, and a 1T switch, which helps to restore the previously written bit in situations of power supply failures, thereby making the SRAM non-volatile.
Gecko foots have inspired researchers to develop designs that can help robots to tread vertically... more Gecko foots have inspired researchers to develop designs that can help robots to tread vertically oriented surface. These nanobots find many applications as they can perform a lot of operations more efficiently and also lower the cost of such operations. These can be employed in various fields: medical, industrial etc. Gecko lizards use dry adhesion van der Waals forces to climb walls produced by their spatular stalks attached on setae. The design of a 3D MEMS model of an electrothermally actuated gecko foot is presented in this paper. The working of a single microhair (with nanohairs attached to it) is discussed and the two designs, one with actuation and one without are compared.
There is vast variation encountered in present circuits
because of aggressive scaling and process... more There is vast variation encountered in present circuits because of aggressive scaling and process imperfections. So this paper deals with various D flip-flop circuits in terms of robustness and propagation delay. This work compares various known D flip-flop circuits and then identifies the circuit which is fastest as compared to others taken into consideration. Further, delay variability exhibited by circuits has been analyzed to test the immunity against PVT variations i.e. process, voltage and temperature. In this paper, we have investigated the output levels of various D flip-flop circuits. Push-pull isolation D flip-flop proves to be more efficient as compared to other circuits in terms of delay variability. The circuits have been simulated using 32-nm technology node on SPICE. The designs offering minimum delay and its variability are reported, to aid the designer in selecting the best design depending on specific requirements.
This paper analyzes the delay and delay variability by
realizing the inverter circuit in differen... more This paper analyzes the delay and delay variability by realizing the inverter circuit in different logic families. Speed plays a major role in today’s VLSI circuits and even a fraction of delay affects the circuits by a large factor. Variability, just like other factors such as delay, area and power has emerged to be a key factor in designing circuits. CMOS families comprises of both single-ended and differential type logic circuits. The outputs of the inverters are investigated at 32-nm technology node in HSPICE model. The logic family with least variability and delay are reported to aid the designer in selecting the best logic family as per the requirement.
This paper characterizes a high electron mobility
transistor (HEMT) having an undoped AlN spacer ... more This paper characterizes a high electron mobility transistor (HEMT) having an undoped AlN spacer layer in the interface of AlGaN and GaN layers. Two-dimensional (2-D) electron gas layer at the interface plays an important role in defining the mobility of charge carriers and hence drain current of HEMT. Introduction of an AlN spacer layer between the AlGaN and GaN layers further causes an improvement in these characteristics. The output characteristics curve (IDS-VDS) and transconductance curves (IDS-VGS) are analyzed by simulating the structure using Silvaco Atlas. The proposed HEMT offers a subthreshold slope of 80 mV/decade and it is 1.53× lower than that of similar structure already reported in the literature.
This paper proposes a compact, low power high
frequency trigger pulse generator circuit. Delay-in... more This paper proposes a compact, low power high frequency trigger pulse generator circuit. Delay-introducing circuit that can incorporate a certain amount of delay during signal processing while maintaining the signal integrity is utilized in the proposed design. This paper evaluates performance of various delay-introducing circuits in terms ofdifferent design matrices. Further, this paper exploits the low power consuming delay element to implement the proposed trigger pulse generator. The proposed design generates very high frequency pulses at the cost of negligible power consumption. The effectiveness of the proposed circuit is presented by producing ultra-thin pulses of pulse duration 92.35 ps while consuming power of only 1.502 w. Extensive simulations are carried out on SPICE @ 16-nm predictive technology model to verify the proposed design.
This paper makes profound investigation of thirteen
different programmable and non-programmable d... more This paper makes profound investigation of thirteen different programmable and non-programmable delay elements. These circuits are capable of incorporating a certain amount of delay during signal processing while maintaining the signal integrity. Performance evaluation of these delay circuits is presented in terms of different design metrics to lay down comparison among these circuits. This work will help design engineers to select appropriate delay element based upon their specific requirements. Extensive simulations are carried out on SPICE using predictive technology model @ 16-nm technology node to verify the results.
This paper presents a compact design of a voltage
controlled tunable resistor (VCTR) with precise... more This paper presents a compact design of a voltage controlled tunable resistor (VCTR) with precise control over itsresistance value. Proposed VCTR requires only six transistors(6T) to implement the design, which reduces the transistor countas compared to 7T or 10T designs already available in the literature. The proposed VCTR design operates in the saturation region with a single control voltage without requirement of any additional bias current or voltage circuitry. Apart from these, the proposed VCTR design is suitable for high frequency operations.This paper also validates the proposed VCTR design by employing it in high-pass filter circuit. The simulations results have been extensively verified using Virtuoso Analog DesignEnvironment of Cadence Design System @ 45-nm technology node.
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exponentially which leads to a dramatic increase in static power consumption
especially in nanoscale devices. Consequently, it is very important to understand
and estimate this leakage current so that various leakage minimization techniques
can be devised. So in this paper we attempt to estimate the subthreshold leakage
current in an NMOSFET at 16, 22, 32 and 45 nm technology nodes. Various factors
which affect the subthreshold leakage such as temperature, drain induced barrier
lowering (DIBL) and other short channel effects have also been explored. All the
measurements are carried out using extensive simulation on HSPICE circuit simulator
at various technology nodes.
Memory (TMCAM) is proposed for a low-delay-write operation. This is attained
from the connections of circuit and majorly due to the exceptional operational
features of CAM integrated with MTJ. While the previous TMCAM required each
one of the MTJ to be written separately, this model attempts to nullify the problem.
Consequently, a reduction in delay by almost twice is obtained in comparison to the
previous TMCAM with a 22 nm CMOS technology used for simulation purposes.
This can be effectively employed in adaptive biomedical signal processing applications
where writing is often and hence, delay cannot be compromised.
(PVT) variations on the open circuit voltage gain of CS amplifier is investigated and appropriate aspect ratios are calculated so as to minimize the effect of threshold voltage modulation in short channel devices. The dependence of transconductance (gm) on the
variations and its nature in both saturation as well as triode region is also determined. Finally, the influence of gate bias on the equivalent output resistance of the amplifying transistor is modeled and corresponding expressions for gain are derived. All simulation results have been extensively verified using CADENCE Virtuoso Analog Design Environment @ 45-nm technology node.
that high performance circuit design is achievable for higher β ratios. At L= 66 nm, optimum threshold voltage is obtained. Minimum energy point (MEP) is also obtained at β ratio of 3.71 at 122 mV.
source feedback SE7T (single-ended 7T) SRAM cell. Using
Monte-Carlo simulations critical design metrics of proposed
SE7T SRAM cell are estimated and the estimated results are
compared with that of conventional 6T SRAM cell. The
proposed source feedback (SE7T) SRAM cell provides 2 times
improvements in Read Access Time (TRA) and 40 times and
1.17 × lower write power and hold power at 800 mv
respectively. The proposed bit cell also provides 1.67 times
higher RSNM (read static noise margin) as compared to
CON6T SRAM Cell. This proves its higher stability.
pump circuit working at an input voltage as low as 100 mV. Most of the micro energy sources work typically in the voltage range of 100 mV. The proposed circuit provides an output voltage of 1 V which is sufficient enough to power low energy-consuming portable devices, biomedical applications such as body sensor networks and remote area monitoring wireless sensing networks.
mode to reduce the power dissipation of chips. Non-volatile SRAM (nvSRAM) enables a chip to store the data after power–off mode. This non-volatility can be achieved through memristor memory technology which is a promising emerging technology with unique properties such as high density, low-power and good-scalability. This paper provides a detailed study of memristor and proposes a memristor based 7T2M nvSRAM cell. This cell incorporates two memristors, which store the bit information present in the 6T SRAM cell, and a 1T switch, which helps to restore the previously written bit in situations of power supply failures, thereby making the SRAM non-volatile.
because of aggressive scaling and process imperfections. So this paper deals with various D flip-flop circuits in terms of robustness and propagation delay. This work compares various known D flip-flop circuits and then identifies the circuit which is fastest as compared to others taken into consideration. Further,
delay variability exhibited by circuits has been analyzed to test the immunity against PVT variations i.e. process, voltage and temperature. In this paper, we have investigated the output levels of various D flip-flop circuits. Push-pull isolation D flip-flop proves to be more efficient as compared to other circuits in terms
of delay variability. The circuits have been simulated using 32-nm technology node on SPICE. The designs offering minimum delay and its variability are reported, to aid the designer in selecting the best design depending on specific requirements.
realizing the inverter circuit in different logic families. Speed plays a major role in today’s VLSI circuits and even a fraction of delay affects the circuits by a large factor. Variability, just like other factors such as delay, area and power has emerged to be a key factor in designing circuits. CMOS families comprises of both
single-ended and differential type logic circuits. The outputs of the inverters are investigated at 32-nm technology node in HSPICE model. The logic family with least variability and delay are reported to aid the designer in selecting the best logic family as per the requirement.
transistor (HEMT) having an undoped AlN spacer layer in the interface of AlGaN and GaN layers. Two-dimensional (2-D) electron gas layer at the interface plays an important role in defining the mobility of charge carriers and hence drain current of HEMT. Introduction of an AlN spacer layer between the AlGaN and GaN layers further causes an improvement in these characteristics. The output characteristics curve (IDS-VDS) and transconductance curves (IDS-VGS) are analyzed by simulating the structure using Silvaco Atlas. The proposed HEMT offers a subthreshold slope of 80 mV/decade and it is 1.53× lower than that of similar structure already reported in the literature.
frequency trigger pulse generator circuit. Delay-introducing circuit that can incorporate a certain amount of delay during signal processing while maintaining the signal integrity is utilized in the proposed design. This paper evaluates performance of various delay-introducing circuits in terms ofdifferent design matrices. Further, this paper exploits the low power consuming delay element to implement the proposed trigger pulse generator. The proposed design generates very
high frequency pulses at the cost of negligible power
consumption. The effectiveness of the proposed circuit is presented by producing ultra-thin pulses of pulse duration 92.35 ps while consuming power of only 1.502 w. Extensive simulations are carried out on SPICE @ 16-nm predictive technology model to verify the proposed design.
different programmable and non-programmable delay
elements. These circuits are capable of incorporating a certain amount of delay during signal processing while maintaining the signal integrity. Performance evaluation of these delay circuits is presented in terms of different design metrics to lay down comparison among these circuits. This work will help design engineers to select appropriate delay element based upon their specific requirements. Extensive simulations are carried out on SPICE using predictive technology model @ 16-nm technology node to verify the results.
controlled tunable resistor (VCTR) with precise control over itsresistance value. Proposed VCTR requires only six transistors(6T) to implement the design, which reduces the transistor countas compared to 7T or 10T designs already available in the literature. The proposed VCTR design operates in the saturation region with a single control voltage without requirement of any additional bias current or voltage circuitry. Apart from these, the
proposed VCTR design is suitable for high frequency operations.This paper also validates the proposed VCTR design by employing it in high-pass filter circuit. The simulations results have been extensively verified using Virtuoso Analog DesignEnvironment of Cadence Design System @ 45-nm technology node.