We present VerSecTis – a new experimental tool for the verification of timed security protocols’ ... more We present VerSecTis – a new experimental tool for the verification of timed security protocols’ (TSP) modelled by Timed Interpreted Systems (TIS). In addition to the TSP’s time-independent properties, our tool can also examine the time dependencies of the TSP’s executions on which their security depends. The verification method consists of a new TSPs’ modelling method and a translation of the reachability problem for TIS to the Satisfiability Modulo Theories problem. We also deliver nineteen TSPs to verify, and we plan to expand the tool with further protocols.
In the paper, we show a formal model for a dialogue game in which players can perform actions rep... more In the paper, we show a formal model for a dialogue game in which players can perform actions representing locutions like claim, question, concede as well as locutions which have a greater emotional charge like scold or nod. We define a protocol for dialogues in which participants have emotional skills and then give an interpreted system for them. Finally, we propose an extension of CTL logic with commitment, emotion and goal modalities. All of this is a formal basis, which we use to perform semantic verification of properties of dialogue systems with emotional reasoning.
In this paper, we present a Satisfiability Modulo Theory based (SMT-based) bounded model checking... more In this paper, we present a Satisfiability Modulo Theory based (SMT-based) bounded model checking (BMC) method for Timed Real-Weighted Interpreted Systems and for the existential fragment of the Weighted Epistemic Computation Tree Logic. SMT-based bounded model checking consists in translating the existential model checking problem for a modal logic and for a model to the satisfiability problem of a quantifier-free first-order formula. We have implemented the SMT-BMC method and performed the BMC algorithm on Timed Weighted Generic Pipeline Paradigm benchmark. The preliminary experimental results demonstrate the feasibility of the method. To perform the experiments, we used the state of the art SMT-solver Z3.
We investigate a new SMT-based bounded model checking (BMC) method for the existential part of Me... more We investigate a new SMT-based bounded model checking (BMC) method for the existential part of Metric Temporal Logic (MTL). The MTL logic is interpreted over linear dense infinite time models generated by timed automata with dense time. We implemented the new SMT-based bounded model checking technique for MTL and as a case study we applied the technique to the analysis of the Timed Generic Pipeline Paradigm and Timed Train Controller System, both modelled by a network of timed automata.
We present a new translation of Metric Temporal Logic with knowledge operators (MTLK) to the Line... more We present a new translation of Metric Temporal Logic with knowledge operators (MTLK) to the Linear Temporal Logic with knowledge operators and with a new set of the atomic propositions (\({\mathrm{{\mathrm{{LTL}}}}_\mathrm{q}\mathrm {K}}\)). We investigate a SAT-based bounded model checking (BMC) method for MTLK. The semantics of MTLK is defined over timed interpreted systems (TIS). We show how to implement the bounded model checking technique for \({\mathrm{{\mathrm{{LTL}}}}_\mathrm{q}\mathrm {K}}\) and timed interpreted systems, and as a case study, we apply the technique in the analysis of the Timed Generic Pipeline Paradigm modelled by TIS. We also present the differences between the old translation of MTLK and the new one. The theoretical description is supported by the experimental results that demonstrate the efficiency of the method.
For many years various types of devices equipped with sensors have guaranteed proper work in a hu... more For many years various types of devices equipped with sensors have guaranteed proper work in a huge amount of machines and systems. For the proper operation of sensors, devices, and complex systems, we need secure communication. Security protocols (SP) in this case, guarantee the achievement of security goals. However, the design of SP is not an easy process. Sometimes SP cannot realise their security goals because of errors in their constructions and need to be investigated and verified in the case of their correctness. Now SP uses often time primitives due to the necessity of security dependence on the passing of time. In this work, we propose and investigate the SAT-and SMT-based formal verification methods of SP used in communication between devices equipped with sensors. For this, we use a formal model based on networks of communicating timed automata. Using this, we show how the security property of SP dedicated to the sensors world can be verified. In our work, we investigate...
We present a satisfiability modulo theories based bounded model checking (SMT-based BMC) method f... more We present a satisfiability modulo theories based bounded model checking (SMT-based BMC) method for timed interpreted systems (\(\mathrm{\mathbb {TIS}}\)) and for properties expressible in the existential fragment of a Real-Time Computation Tree Logic with epistemic components (RTECTLK). We implemented the standard BMC algorithm and evaluated it for two multi-agent systems: a timed train controller system and a timed generic pipeline paradigm. We used the Z3 solver.
In this paper we define Satisfiability Modulo Theory based (SMT-based) and SAT-based bounded mode... more In this paper we define Satisfiability Modulo Theory based (SMT-based) and SAT-based bounded model checking (BMC) methods for the existential fragment of Weighted Epistemic Linear Time Logic (WLTLK) interpreted on Timed Weighted Interpreted Systems (TWISs). We provide an implementation based on Z3 and PicoSAT solvers and we present a comparison of the two methods on common instances that can be scaled up to for performance evaluation. A detailed analysis of results shows that in many instances the SMT-based approach can be significantly faster than the SAT-based approach.
Automating the composition of web services is an object of a growing interest. In a previous pape... more Automating the composition of web services is an object of a growing interest. In a previous paper we proposed a method for converting the problem of the composition to the problem of building a graph of worlds consisting of formally defined objects, and presented the first phase of this composition aimed at building a graph of types of services (an abstract graph). In this work we propose a method of replacing abstract flows of this graph by sequences of concrete services able to satisfy the user’s request. The method is based on SAT-based reachability checking for (timed) automata with discrete data and parametric assignments.
We report on a SAT-based bounded model checking (BMC) method for simply-timed systems (i.e., Krip... more We report on a SAT-based bounded model checking (BMC) method for simply-timed systems (i.e., Kripke models where transitions carry a duration, which is an arbitrary natural number) generated by simply-timed automata with discrete data, and properties expressed in the existential fragment of a soft real-time temporal logic (RTECTL). In particular, since in BMC both the system model and the checked property are translated into a Boolean formula to be analysed by a SAT-solver, we introduce a new Boolean encoding of the RTECTL formulae that is particularly optimized for managing quantitative metric temporal operators, typically found in properties of soft real-time systems (simply-timed systems). The proposed BMC algorithm is implemented as a new module of VerICS, and evaluated by means of two scalable scenarios.
We present VerSecTis – a new experimental tool for the verification of timed security protocols’ ... more We present VerSecTis – a new experimental tool for the verification of timed security protocols’ (TSP) modelled by Timed Interpreted Systems (TIS). In addition to the TSP’s time-independent properties, our tool can also examine the time dependencies of the TSP’s executions on which their security depends. The verification method consists of a new TSPs’ modelling method and a translation of the reachability problem for TIS to the Satisfiability Modulo Theories problem. We also deliver nineteen TSPs to verify, and we plan to expand the tool with further protocols.
In the paper, we show a formal model for a dialogue game in which players can perform actions rep... more In the paper, we show a formal model for a dialogue game in which players can perform actions representing locutions like claim, question, concede as well as locutions which have a greater emotional charge like scold or nod. We define a protocol for dialogues in which participants have emotional skills and then give an interpreted system for them. Finally, we propose an extension of CTL logic with commitment, emotion and goal modalities. All of this is a formal basis, which we use to perform semantic verification of properties of dialogue systems with emotional reasoning.
In this paper, we present a Satisfiability Modulo Theory based (SMT-based) bounded model checking... more In this paper, we present a Satisfiability Modulo Theory based (SMT-based) bounded model checking (BMC) method for Timed Real-Weighted Interpreted Systems and for the existential fragment of the Weighted Epistemic Computation Tree Logic. SMT-based bounded model checking consists in translating the existential model checking problem for a modal logic and for a model to the satisfiability problem of a quantifier-free first-order formula. We have implemented the SMT-BMC method and performed the BMC algorithm on Timed Weighted Generic Pipeline Paradigm benchmark. The preliminary experimental results demonstrate the feasibility of the method. To perform the experiments, we used the state of the art SMT-solver Z3.
We investigate a new SMT-based bounded model checking (BMC) method for the existential part of Me... more We investigate a new SMT-based bounded model checking (BMC) method for the existential part of Metric Temporal Logic (MTL). The MTL logic is interpreted over linear dense infinite time models generated by timed automata with dense time. We implemented the new SMT-based bounded model checking technique for MTL and as a case study we applied the technique to the analysis of the Timed Generic Pipeline Paradigm and Timed Train Controller System, both modelled by a network of timed automata.
We present a new translation of Metric Temporal Logic with knowledge operators (MTLK) to the Line... more We present a new translation of Metric Temporal Logic with knowledge operators (MTLK) to the Linear Temporal Logic with knowledge operators and with a new set of the atomic propositions (\({\mathrm{{\mathrm{{LTL}}}}_\mathrm{q}\mathrm {K}}\)). We investigate a SAT-based bounded model checking (BMC) method for MTLK. The semantics of MTLK is defined over timed interpreted systems (TIS). We show how to implement the bounded model checking technique for \({\mathrm{{\mathrm{{LTL}}}}_\mathrm{q}\mathrm {K}}\) and timed interpreted systems, and as a case study, we apply the technique in the analysis of the Timed Generic Pipeline Paradigm modelled by TIS. We also present the differences between the old translation of MTLK and the new one. The theoretical description is supported by the experimental results that demonstrate the efficiency of the method.
For many years various types of devices equipped with sensors have guaranteed proper work in a hu... more For many years various types of devices equipped with sensors have guaranteed proper work in a huge amount of machines and systems. For the proper operation of sensors, devices, and complex systems, we need secure communication. Security protocols (SP) in this case, guarantee the achievement of security goals. However, the design of SP is not an easy process. Sometimes SP cannot realise their security goals because of errors in their constructions and need to be investigated and verified in the case of their correctness. Now SP uses often time primitives due to the necessity of security dependence on the passing of time. In this work, we propose and investigate the SAT-and SMT-based formal verification methods of SP used in communication between devices equipped with sensors. For this, we use a formal model based on networks of communicating timed automata. Using this, we show how the security property of SP dedicated to the sensors world can be verified. In our work, we investigate...
We present a satisfiability modulo theories based bounded model checking (SMT-based BMC) method f... more We present a satisfiability modulo theories based bounded model checking (SMT-based BMC) method for timed interpreted systems (\(\mathrm{\mathbb {TIS}}\)) and for properties expressible in the existential fragment of a Real-Time Computation Tree Logic with epistemic components (RTECTLK). We implemented the standard BMC algorithm and evaluated it for two multi-agent systems: a timed train controller system and a timed generic pipeline paradigm. We used the Z3 solver.
In this paper we define Satisfiability Modulo Theory based (SMT-based) and SAT-based bounded mode... more In this paper we define Satisfiability Modulo Theory based (SMT-based) and SAT-based bounded model checking (BMC) methods for the existential fragment of Weighted Epistemic Linear Time Logic (WLTLK) interpreted on Timed Weighted Interpreted Systems (TWISs). We provide an implementation based on Z3 and PicoSAT solvers and we present a comparison of the two methods on common instances that can be scaled up to for performance evaluation. A detailed analysis of results shows that in many instances the SMT-based approach can be significantly faster than the SAT-based approach.
Automating the composition of web services is an object of a growing interest. In a previous pape... more Automating the composition of web services is an object of a growing interest. In a previous paper we proposed a method for converting the problem of the composition to the problem of building a graph of worlds consisting of formally defined objects, and presented the first phase of this composition aimed at building a graph of types of services (an abstract graph). In this work we propose a method of replacing abstract flows of this graph by sequences of concrete services able to satisfy the user’s request. The method is based on SAT-based reachability checking for (timed) automata with discrete data and parametric assignments.
We report on a SAT-based bounded model checking (BMC) method for simply-timed systems (i.e., Krip... more We report on a SAT-based bounded model checking (BMC) method for simply-timed systems (i.e., Kripke models where transitions carry a duration, which is an arbitrary natural number) generated by simply-timed automata with discrete data, and properties expressed in the existential fragment of a soft real-time temporal logic (RTECTL). In particular, since in BMC both the system model and the checked property are translated into a Boolean formula to be analysed by a SAT-solver, we introduce a new Boolean encoding of the RTECTL formulae that is particularly optimized for managing quantitative metric temporal operators, typically found in properties of soft real-time systems (simply-timed systems). The proposed BMC algorithm is implemented as a new module of VerICS, and evaluated by means of two scalable scenarios.
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