default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID32nd VLSI-SoC 2024: Tanger, Morocco
- 32nd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2024, Tanger, Morocco, October 6-9, 2024. IEEE 2024, ISBN 979-8-3315-3967-2
- Sumanth Kolluru, Kenneth S. Stevens:
Behavioral Simulation of Relative Timed Asynchronous Circuits. 1-6 - Gokulnath Rajendran, Debajit Basak, Suman Deb, Siyi Wang, Anupam Chattopadhyay:
A Novel Current Comparator Enabling Large RRAM Crossbars for BNNs and PUFs. 1-6 - Lucas Rhetat, Jean-Philippe Noel, Bastien Giraud, Laurent Grenouillet, Julie Laguerre, Cédric Marchand, Ian O'Connor:
A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM. 1-6 - Ashton Snelgrove, Skylar Stockham, Pierre-Emmanuel Gaillardon:
Benchmarking Microfluidic Design Automation Flows. 1-6 - Anis Fellah-Touta, Lilian Bossuet, Vincent Grosso, Carlos Andres Lara-Nino:
Lightweight Active Fences for FPGAs. 1-4 - Muhammad Kashif Minhas, Haroon Waris, Sajid Baloch:
FVDCLS: Functional Verification of RISCV Based Dual-Core Lockstep Feature Using Fault Injection Mechanism. 1-4 - Asmae El Arrassi, Mohammad Amin Yaldagard, Xingjian Tao, Taha Shahroodi, Fouwad Jamil Mir, Yashvardhan Biyani, Manil Dev Gomony, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui:
AFSRAM-CIM: Adder Free SRAM-Based Digital Computation-in-Memory for BNN. 1-6 - Sami El Amraoui, Régis Leveugle, Paolo Maistri:
Capture the Pulse: Impact of FPGA Resource Utilization on EM Fault Injection Attacks Detection. 1-6 - Venkata K. V. V. Bathalapalli, Aakarshan Kumar, Saraju P. Mohanty, Elias Kougianos, Venkata P. Yanambaka:
BlockShield: A TPM-Integrated Blockchain-Based Framework for Shielding Against Deepfakes. 1-6 - Thomas Makryniotis, Georgi Gaydadjiev, Said Hamdioui, Mottaqiallah Taouil:
Multi-Level FeFET-Based CAM Address Decoder. 1-6 - Mohammad Ismael, Ayman Hroub, Nasib Naser:
SystemVerilog-SystemC TestBench Architecture for VLSI Chip Design Verification. 1-4 - Jaimini Nagar, Thorsten Dworzak, Sebastian Simon, Ulrich Heinkel, Djones Lettnin:
Exploring the Role of the Portable Stimulus Standard in Enhancing Security Property Verification. 1-4 - Lilas Alrahis, Mohammed Thari Nabeel, Johann Knechtel, Ozgur Sinanoglu:
The Impact of Logic Synthesis and Technology Mapping on Logic Locking Security. 1-6 - Mujahid Bilal, M. Kamran Bhatti, Muhammad Kahsif Minhas, Haroon Waris:
Design Co-Processor Based on Partially Homomorphic Encryption Execution Using Open-Source Tool. 1-4 - Saleh Mulhem, Christian Ewert, Andrija Neskovic, Amrit Sharma Poudel:
Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip. 1-6 - Uxua Esteban-Eraso, Carlos Sánchez-Azqueta, Francisco Aznar, Concepción Aldea, Santiago Celma:
Compensating the Load Effect in Quadrature All-Pass Filters. 1-4 - Jiteshri Dasari, Cunxi Yu, Maciej J. Ciesielski:
Linear Algebra Approach to Verification of Modular $(2^{n}-1)$ Multipliers. 1-6 - Nitish Satya Murthy, Nathan Laubeuf, Debjyoti Bhattacharjee, Francky Catthoor, Marian Verhelst:
Adaptive Block-Scaled GeMMs on Vector Processors for DNN Training at the Edge. 1-6 - Laavanya Rachakonda, Samuel Stasiewicz:
SanaSolo 2.0: Edge-Based Monitoring and Management of Soil Fertility Using IoT. 1-6 - Junchao Chen, Giuseppe Esposito, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Angeliki Kritikakou, Milos Krstic, Robert Limas Sierra, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Marcello Traiola, Alessandro Veronesi:
Reliability Assessment of Large DNN Models: Trading Off Performance and Accuracy. 1-10 - Emilien Taly, Roberto Guizzetti, Pascal Urard, Elena-Ioana Vatajelu:
GemIMC: A Configurable HW Architecture for Technology Agnostic IMC Based NN Inference. 1-6 - Arturo Prieto, Joachim Rodrigues:
High-Density Standard Cell Library for Sequential 3D Integrated Circuits. 1-4 - Mahdi Shamsa, Laavanya Rachakonda, Saraju P. Mohanty, Elias Kougianos:
qCrop: An IoT Based Framework to Enhance Crop Productivity in Smart Agriculture. 1-6 - Seyed Hossein Hashemi Shadmehri, Supriya Chakraborty, Thiago Santos Copetti, Fabian Luis Vargas, Letícia Maria Bolzani Poehls:
Understanding Transistor Aging Impact on the Behavior of RRAM Cells. 1-6 - Rishabh Mahanta, Hemangee K. Kapoor:
DynaCache: A Checkpoint Aware Reconfigurable Cache for Intermittently Powered Computing Systems. 1-6 - Abhiroop Bhowmik, Subin Babukutty, Mottaqiallah Taouil, Moritz Fieback:
A Unified Functional Safety EDA Framework for Accurate Diagnostic Coverage Estimation. 1-6 - Mohammed Nabeel, Homer Gamil, Johann Knechtel, Michail Maniatakos:
MCS-NTT: Multi-Chip System Design for NTT Acceleration. 1-4 - Ayushi Agarwal, Radhika Dharwadkar, Isaar Ahmad, Krishna Kumar, P. J. Joseph, Sourav Roy, Prokash Ghosh, Preeti Ranjan Panda:
APPAMM: Memory Management for IPsec Application on Heterogeneous SoCs. 1-6 - Gian Singh, Ayushi Dube, Sarma B. K. Vrudhula:
A High Throughput, Energy-Efficient Architecture for Variable Precision Computing in DRAM. 1-6 - Bram Van Bolderik, Vlado Menkovski, Sonia Heemstra, Manil Dev Gomony:
MEAN: Mixture-of-Experts Based Neural Receiver. 1-4 - Bulbul Ahmed, Sujan Kumar Saha, Jingbo Zhou, Sohrab Aftabjahani, Mark M. Tehranipoor, Farimah Farahmandi:
Continuity in Security: Leveraging LLM for Translating Security Properties Across Hardware Designs. 1-6 - Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. 1-6 - Sara Mannaa, Cédric Marchand, Damien Deleruyelle, Bastien Deveautour, Alberto Bosio, Christoph Lenz, Oskar Baumgartner, Ian O'Connor:
3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic Synthesis. 1-4 - Esrat Khan, Shahzad Muzaffar, Lamees M. Al Qassem, Ibrahim M. Elfadel:
OSHDA: A Containerized CAD Tool for the Design and Analysis of Behavioral FSM Logic Locking. 1-6 - Natalia Cherezova, Salvatore Pappalardo, Mahdi Taheri, Mohammad Hasan Ahmadilivani, Bastien Deveautour, Alberto Bosio, Jaan Raik, Maksim Jenihhin:
Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability. 1-4 - Siyi Wang, Eugene Lim, Xiufan Li, Jerrie Feng, Anupam Chattopadhyay:
Minimum Depth Quantum Modular Addition Through Carry-Save Architecture. 1-6 - Harideep Nair, Prabhu Vellaisamy, Tsung-Han Lin, Perry H. Wang, Ronald Shawn Blanton, John Paul Shen:
Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference. 1-4 - Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn:
A Low-Power Linear Phase Interpolation-Based Delay Line in 12nm FinFET Technology. 1-5 - Hasan Moussa, Estelle Lauga-Larroze, Laurent Fesquet:
A New Control Law for N-Path Mixer Switches Enhancing Harmonic Rejection. 1-4 - Yicheng Zhang, Manil Dev Gomony, Henk Corporaal, Federico Corradi:
A Scalable Hardware Architecture for Efficient Learning of Recurrent Neural Networks at the Edge. 1-4 - Tejas Musale, Arun Ganti, Ankur Gogoi, Kanchan Manna:
Low Power Network-on-Chip Architecture Design Technique. 1-6 - Assia El-Hadbi, Oussama Elissati, Laurent Fesquet:
Time-to-Digital Converter Based Self-Timed Ring Oscillator: An FPGA Implementation. 1-4 - Laavanya Rachakonda:
Transforming Agriculture: A Mini-Review of IoT Innovations and their Impact. 1-6 - Seema G. Aarella, Venkata P. Yanambaka, Saraju P. Mohanty, Elias Kougianos:
Fortified-Edge 5.0: Federated Learning for Secure and Reliable PUF in Authentication Systems. 1-6 - Mouadh Ayache, Enkele Rama, Saleh Mulhem, Mladen Berekovic, Matthias Korb:
Holistic Framework for Evaluating the Trustworthiness of Integrated Circuits. 1-4 - Paulette Iskandar, Bryan Olmos, Wolfgang Kunz, Djones Lettnin:
Adaptable FWHW Formal Co-Verification of SoC RISC-V Components. 1-6 - Luis Enrique Murillo Vizcardo, Ricardo Reis:
NEATRouter: A New Method for 2D Global Routing. 1-6 - Istvan Andras Gergely, Sebastian Rausch, Nahla A. El-Araby, Axel Jantsch:
Resource Management of Automotive Engine Control Units. 1-4 - Sajeed Mohammad, Farimah Farahmandi:
FortBoot: Fortifying Rooted-in-Device-Specific Security Through Secure Booting. 1-4 - Mario Barbareschi, Salvatore Barone, Antonio Emmanuele, Nicola Mazzocca:
Exploiting Functional Approximation on Decision-Tree Based Multiple Classifier Systems. 1-4 - Ali Shisha, Balajiraja Ravinarayanan, Knut Mellenthin:
Enhanced Diagnosis of Failing Bits in Memory Built-in Self-Test. 1-4 - Akshay Nagpal, Vivekananda Jayaram, Manjunatha Sughaturu Krishnappa, Nikhil Jagdish Bangad, Darshan Mohan Bidkar, Manoj Jayantilal Kathiriya, Seema G. Aarella:
Performance Analysis of Greedy and Auction-Based Resource Allocation Algorithms in Ubiquitous Computing Environments. 1-6 - Rafaella Elia, Theocharis Theocharides:
Embedded and Real-Time Anomalous Command Classification in Unmanned Ground Vehicle Operations. 1-6 - Ernesto Cristopher Villegas Castillo, Felipe Augusto da Silva, Michael Glaß:
Diagnostic Coverage Estimation for Automotive SoCs Based on Colored Stochastic Petri Nets. 1-6
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-13 00:36 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
