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ORCIDIEEE Design & Test of Computers, Volume 25
Volume 25, Number 1, January/February 2008
- Kwang-Ting (Tim) Cheng
:
From the EIC. 4 - Bruce C. Kim, Craig Force:
Guest Editors' Introduction: The Evolution of RFIC Design and Test. 6-8 - Vasanth Kakani, Fa Foster Dai:
Design and Analysis of a Transversal Filter RFIC in SiGe Technology. 10-16 - Changwook Yoon, Junwoo Lee, Young-Jin Park, Hyunjeong Park, Jaemin Kim, Junso Pak, Joungho Kim:
Design of a Low-Noise UWB Transceiver SiP. 18-28 - Yves Joannon, Vincent Beroulle, Chantal Robach, Smail Tedjini, Jean-Louis Carbonéro:
Decreasing Test Qualification Time in AMS and RF Systems. 29-37 - Joe Kelly, Dean Nicholson, Edwin Lowery, Victor Grothen:
Light-Enhanced FET Switch Improves ATE RF Power Settling. 38-43 - John Mark Nolen, Rabi N. Mahapatra:
Time-Division-Multiplexed Test Delivery for NoC Systems. 44-51 - Jorgen Peddersen, Sri Parameswaran:
Low-Impact Processor for Dynamic Runtime Power Management. 52-62 - Nektarios Kranitis, Andreas Merentitis, George Theodorou, Antonis M. Paschalis, Dimitris Gizopoulos:
Hybrid-SBST Methodology for Efficient Testing of Processor Cores. 64-75 - Daniele Rossi, André K. Nieuwland, Cecilia Metra:
Simultaneous Switching Noise: The Relation between Bus Layout and Coding. 76-86 - Scott Davidson:
How to make your own processor architecture. 96-98 - Joe Damore:
DATC Newsletter. 102 - Bruce C. Kim:
TTTC Newsletter. 103 - William Krenik:
Changing times in the RF world. 104
Volume 25, Number 2, March/April 2008
- Kwang-Ting (Tim) Cheng:
Test compression saves bits, cycles, and money. 105 - Scott Davidson, Nur A. Touba:
Guest Editors' Introduction: Progress in Test Compression. 112-113 - Rohit Kapur, Subhasish Mitra, Thomas W. Williams:
Historical Perspective on Scan Compression. 114-120 - Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Zhigang Wang, Zhigang Jiang, Boryau Sheu, Xinli Gu:
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG. 122-130 - Chao-Wen Tzeng, Shi-Yu Huang:
UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting. 132-140 - Kee Sup Kim, Ming Zhang:
Hierarchical Test Compression for SoC Designs. 142-148 - Ganesh Srinivasan, Friedrich Taenzler, Abhijit Chatterjee:
Loopback DFT for Low-Cost Test of Single-VCO-Based Wireless Transceivers. 150-159 - Qizhang Yin, William R. Eisenstadt, Tian Xia:
Wireless System for Microwave Test Signal Generation. 160-166 - Melvin A. Breuer, Haiyang (Henry) Zhu:
An Illustrated Methodology for Analysis of Error Tolerance. 168-177 - Hamidreza Hashempour, Fabrizio Lombardi:
Device Model for Ballistic CNFETs Using the First Conducting Band. 178-186 - Joe Damore:
DATC Newsletter. 187 - Victor Berman:
Standards update from IP 07. 192-193 - Sachin S. Sapatnekar:
Building your yield of dreams. 194-195 - Bruce C. Kim:
TTTC Newsletter. 198-199 - Scott Davidson:
The commonality of vector generation techniques. 200
Volume 25, Number 3, May/June 2008
- Kwang-Ting (Tim) Cheng:
Effective silicon debug is key for time to money. 204 - Rob Aitken, Erik Jan Marinissen:
Guest Editors' Introduction: Addressing the Challenges of Debug and Diagnosis. 206-207 - Bart Vermeulen:
Functional Debug Techniques for Embedded Systems. 208-215 - Miron Abramovici:
In-System Silicon Validation and Debug. 216-223 - Kip Killpack, Suriyaprakash Natarajan, Arun Krishnamachary, Pouria Bastani:
Case Study on Speed Failure Causes in a Microprocessor. 224-230 - Pouria Bastani, Li-C. Wang, Magdy S. Abadir:
Linking Statistical Learning to Diagnosis. 232-239 - Yu Huang, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li:
Survey of Scan Chain Diagnosis. 240-248 - Christian Boit, Rudolf Schlangen, Uwe Kerst, Ted R. Lundquist:
Physical Techniques for Chip-Backside IC Debug in Nanotechnologies. 250-257 - Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick:
Overview of Debug Standardization Activities. 258-267 - David Yeh, Li-Shiuan Peh, Shekhar Borkar, John A. Darringer, Anant Agarwal, Wen-mei W. Hwu:
Thousand-Core Chips [Roundtable]. 272-278 - Grant Martin:
Learning to assert yourself [review of Creating Assertion-Based IP (H.D. Foster and A.C. Krolnik; 2008)]. 284-285 - Erik Jan Marinissen:
Bugs, moths, grasshoppers, and whales. 288
Volume 25, Number 4, July/August 2008
- Kwang-Ting (Tim) Cheng:
Not just research as usual. 292 - William H. Joyner Jr., David C. Yeh:
Guest Editors' Introduction: System IC Design Challenges beyond 32 nm. 294-295 - Jan M. Rabaey, Sharad Malik:
Challenges and Solutions for Late- and Post-Silicon Design. 296-302 - Wen-mei W. Hwu, Kurt Keutzer, Timothy G. Mattson:
The Concurrency Challenge. 312-320 - Richard Oehler:
The GSRC: Bridging Academia and Industry. 321 - Todd M. Austin, Valeria Bertacco, Scott A. Mahlke, Yu Cao:
Reliable Systems on Unreliable Fabrics. 322-332 - Ajith Amerasekera:
The Changing Design Landscape. 333 - Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet S. Roychowdhury, Douglas L. Jones, Jan M. Rabaey:
The Search for Alternative Computational Paradigms. 334-343 - Leon Stok:
Variability and New Design Paradigms. 344 - Alberto L. Sangiovanni-Vincentelli:
Is a Unified Methodology for System-Level Design Possible? 346-357 - Jan M. Rabaey, Daniel Burke, Ken Lutz, John Wawrzynek:
Workloads of the Future. 358-365 - John C. Zolper:
The GSRC's Role in Meeting Tomorrow's Design Challenges. 366-367 - Philip Y. Paik, Vamsee K. Pamula, Krishnendu Chakrabarty:
A Digital-Microfluidic Approach to Chip Cooling. 372-381 - Scott Davidson:
With pick and shovel through our data. 382-383 - Joe Damore:
DATC Newsletter. 384 - Betsy Weitzman:
Who knew this "experiment" would be so successful? 392
Volume 25, Number 5, September/October 2008
- Nur A. Touba:
ITC 2008 Highlights. 398-399 - Yatin Vasant Hoskote, Radu Marculescu, Li-Shiuan Peh:
Guest Editors' Introduction: Tackling Key Problems in NoCs. 400-401 - Alessandro Pinto, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
COSI: A Framework for the Design of Interconnection Networks. 402-415 - Stephan Bourduas, Jean-Samuel Chenard, Zeljko Zilic:
A Quality-Driven Design Approach for NoCs. 416-428 - Byungsub Kim, Vladimir Stojanovic:
Characterization of Equalized and Repeated Interconnects for NoC Applications. 430-439 - Matthias Kühnle, Michael Hübner, Jürgen Becker, Antonio Deledda, Claudio Mucci, Florian Ries, Marcello Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Tommaso DeMarco, Fabio Campi:
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC. 442-451 - Jorge Semião, Marcial Jesús Rodríguez-Irago, Juan J. Rodríguez-Andina, Leonardo Bisch Piccoli, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel Maria Cacho Teixeira, João Paulo Teixeira:
Signal Integrity Enhancement in Digital Circuits. 452-461 - Chung-Fu Kao, Hsin-Ming Chen, Ing-Jer Huang:
Hardware-Software Approaches to In-Circuit Emulation for Embedded Processors. 462-477 - Geeng-Wei Lee, Juinn-Dar Huang, Chun-Yao Wang, Jing-Yang Jou:
Verification of Pin-Accurate Port Connections. 478-486 - Giovanni De Micheli:
Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow. 488-494 - Sachin S. Sapatnekar:
Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)]. 496-497 - Ian R. Mackintosh:
OCP-IP NoC Benchmarking WG activities. 504
Volume 25, Number 6, November/December 2008
- Kwang-Ting (Tim) Cheng:
Design and test for reliability and efficiency. 508 - Reinaldo A. Bergamaschi, Luca Benini, Krisztián Flautner, Wido Kruijtzer, Alberto L. Sangiovanni-Vincentelli, Kazutoshi Wakabayashi:
The State of ESL Design [Roundtable]. 510-519 - Rajesh Gupta, Arvind, Gérard Berry, Forrest Brewer:
Advances in ESL Design. 520-526 - William R. Mann:
Wafer Test Methods to Improve Semiconductor Die Reliability. 528-537 - Dimitrios Simos, Ioannis Papaefstathiou, Manolis Katevenis:
Building an FoC Using Large, Buffered Crossbar Cores. 538-548 - Mohammad Tehranipoor, Reza M. Rad:
Defect Tolerance for Nanoscale Crossbar-Based Devices. 549-559 - Jen-Chieh Yeh, Chao-Hsun Chen, Cheng-Wen Wu, Shuo-Fen Kuo:
A Systematic Approach to Memory Test Time Reduction. 560-570 - Abbas Sheibanyrad, Alain Greiner, Ivan Miro Panades:
Multisynchronous and Fully Asynchronous NoCs for GALS Architectures. 572-580 - Stefan Valentin Gheorghita, Twan Basten, Henk Corporaal:
Application Scenarios in Streaming-Oriented Embedded-System Design. 581-589 - Ted Huffmire, Brett Brotherton, Timothy Sherwood, Ryan Kastner, Timothy E. Levin, Thuy D. Nguyen, Cynthia E. Irvine:
Managing Security in FPGA-Based Embedded Systems. 590-598 - Grant Martin:
The two faces of high-level synthesis [review of High-Level Synthesis: From Algorithm to Digital Circuit (Coussy, P. and Morawiec, A., Eds., 2008)]. 600-601 - Melvin A. Breuer:
Clarifying the record on testability cost functions. 608-609
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