default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDKiamal Z. Pekmestzi
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2023
[i2]Vasileios Leon, Muhammad Abdullah Hanif, Giorgos Armeniakos, Xun Jiao, Muhammad Shafique, Kiamal Z. Pekmestzi, Dimitrios Soudris:
Approximate Computing Survey, Part I: Terminology and Software & Hardware Approximation Techniques. CoRR abs/2307.11124 (2023)- [i1]Vasileios Leon, Muhammad Abdullah Hanif, Giorgos Armeniakos, Xun Jiao, Muhammad Shafique, Kiamal Z. Pekmestzi, Dimitrios Soudris:
Approximate Computing Survey, Part II: Application-Specific & Architectural Approximation Techniques and Applications. CoRR abs/2307.11128 (2023) - 2022
- [c67]Vasileios Leon, Georgios Makris, Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris
:
MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators. LASCAS 2022: 1-4 - [c66]Vasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris:
Systematic Embedded Development and Implementation Techniques on Intel Myriad VPUs. VLSI-SoC 2022: 1-2 - 2021
- [j30]Vasileios Leon, Theodora Paparouni, Evangelos Petrongonas, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers. ACM Trans. Embed. Comput. Syst. 20(5): 39:1-39:21 (2021) - [c65]Vasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris:
Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators. FPL 2021: 263-264 - 2020
- [j29]Fotios Ntouskas, Constantinos Efstathiou, Kiamal Z. Pekmestzi:
Efficient design of magnitude and 2's complement comparators. Integr. 71: 164-169 (2020) - [j28]Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nikolaos Moschopoulos:
On the Diminished-1 Modulo 2n+1 Addition and Subtraction. J. Circuits Syst. Comput. 29(5): 2030005:1-2030005:14 (2020) - [c64]George Lentaris, George Chatzitsompanis, Vasileios Leon, Kiamal Z. Pekmestzi, Dimitrios Soudris:
Combining Arithmetic Approximation Techniques for Improved CNN Circuit Design. ICECS 2020: 1-4
2010 – 2019
- 2019
- [j27]Vasileios Leon, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Energy-efficient VLSI implementation of multipliers with double LSB operands. IET Circuits Devices Syst. 13(6): 816-821 (2019) - [j26]Georgios Zervakis, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints. IEEE Trans. Circuits Syst. II Express Briefs 66-II(4): 607-611 (2019) - [c63]Vasileios Leon, Konstantinos Asimakopoulos, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers. DAC 2019: 160 - [c62]Spyridon Mouselinos, Vasileios Leon, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
TF2FPGA: A Framework for Projecting and Accelerating Tensorflow CNNs on FPGA Platforms. MOCAST 2019: 1-4 - 2018
- [j25]Vasileios Leon, Georgios Zervakis, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Walking through the Energy-Error Pareto Frontier of Approximate Multipliers. IEEE Micro 38(4): 40-49 (2018) - [j24]Vasileios Leon, Georgios Zervakis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 421-430 (2018) - [j23]Georgios Zervakis, Fotios Ntouskas, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(6): 1204-1208 (2018) - [c61]Charalampos Marantos, Nikolaos Karavalakis, Vasileios Leon, Vasileios Tsoutsouras, Kiamal Z. Pekmestzi, Dimitrios Soudris:
Efficient support vector machines implementation on Intel/Movidius Myriad 2. MOCAST 2018: 1-4 - 2017
- [j22]Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi:
DIRT latch: A novel low cost double node upset tolerant latch. Microelectron. Reliab. 68: 57-68 (2017) - [c60]Fotis Douskas, Kiamal Z. Pekmestzi:
On the design of the FFT Butterfly Units. MOCAST 2017: 1-4 - 2016
- [j21]Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi:
Low latency radiation tolerant self-repair reconfigurable SRAM architecture. Microelectron. Reliab. 56: 202-211 (2016) - [j20]Kostas Tsoumanis, Nicholas Axelos, Nikolaos Moschopoulos, Georgios Zervakis, Kiamal Z. Pekmestzi:
Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding. IEEE Trans. Computers 65(2): 670-676 (2016) - [j19]Kostas Tsoumanis, Sotirios Xydis, Georgios Zervakis, Kiamal Z. Pekmestzi:
Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 368-372 (2016) - [j18]Georgios Zervakis, Kostas Tsoumanis, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3105-3117 (2016) - [c59]Kiamal Z. Pekmestzi, Constantinos Efstathiou:
Design of Efficient 1's Complement Modified Booth Multiplier. DSD 2016: 238-243 - [c58]Kiamal Z. Pekmestzi, Kostas Tsoumanis, Constantinos Efstathiou:
Fused modulo 2n + 1 add-multiply unit for weighted operands. DTIS 2016: 1-6 - 2015
- [c57]Georgios Zervakis, Kostas Tsoumanis, Sotirios Xydis, Nicholas Axelos, Kiamal Z. Pekmestzi:
Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis. ACM Great Lakes Symposium on VLSI 2015: 229-232 - [c56]Nikolaos Eftaxiopoulos-Sarris, Nicholas Axelos, Kiamal Z. Pekmestzi:
Low leakage radiation tolerant CAM/TCAM cell. IOLTS 2015: 206-211 - [c55]Georgios Zervakis, Sotirios Xydis, Kostas Tsoumanis, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Hybrid approximate multiplier architectures for improved power-accuracy trade-offs. ISLPED 2015: 79-84 - [c54]Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis:
Modulo 2n ± 1 Fused Add-Multiply Units. ISVLSI 2015: 91-96 - [c53]Nikolaos Eftaxiopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi:
DONUT: A Double Node Upset Tolerant Latch. ISVLSI 2015: 509-514 - [c52]Nikolaos Eftaxiopoulos, Nicholas Axelos, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi:
Delta DICE: A Double Node Upset resilient latch. MWSCAS 2015: 1-4 - 2014
- [j17]Constantinos Efstathiou, Nikos K. Moshopoulos, Nicholas Axelos, Kiamal Z. Pekmestzi:
Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding. Integr. 47(1): 140-147 (2014) - [j16]Kostas Tsoumanis, Sotirios Xydis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi:
An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(4): 1133-1143 (2014) - [c51]Georgios Zervakis, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, Nicholas Axelos, Kiamal Z. Pekmestzi:
A segmentation-based BISR scheme. ASP-DAC 2014: 652-657 - [c50]Constantinos Efstathiou, Kostas Tsoumanis, Kiamal Z. Pekmestzi, Ioannis Voyiatzis:
On the design of efficient modulo 2n+1 multiply-add-add units. DTIS 2014: 1-4 - [c49]Kostas Tsoumanis, Kiamal Z. Pekmestzi, Constantinos Efstathiou:
Fused modulo 2n - 1 add-multiply unit. ICECS 2014: 40-43 - [c48]Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kiamal Z. Pekmestzi, Costas Efstathiou:
High performance MAC designs. IDT 2014: 30-35 - [c47]Nikolaos Eftaxiopoulos-Sarris, Nicholas Axelos, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi:
An independent dual gate SOI FinFET soft-error resilient memory cell. IDT 2014: 39-44 - [c46]Georgios Zervakis, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, Nicholas Axelos, Kiamal Z. Pekmestzi:
A high radix montgomery multiplier with concurrent error detection. IDT 2014: 199-204 - [c45]Kostas Tsoumanis, Constantinos Efstathiou, Kiamal Z. Pekmestzi:
Modulo 2n+1 addition and multiplication for redundant operands. IDT 2014: 205-210 - [c44]Nicholas Axelos, Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi:
FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs. IOLTS 2014: 200-201 - 2013
- [j15]Costas Efstathiou, Nikolaos Moschopoulos, Ioannis Voyiatzis, Kiamal Z. Pekmestzi:
On the design of modulo 2n + 1 dot product and generalized multiply-add units. Comput. Electr. Eng. 39(2): 410-419 (2013) - [j14]Isidoros Sideris, Kiamal Z. Pekmestzi:
A column parity based fault detection mechanism for FIFO buffers. Integr. 46(3): 265-279 (2013) - [c43]Kiamal Z. Pekmestzi, Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis:
Efficient modulo 2n+1 multiplication for the idea block cipher. ACM Great Lakes Symposium on VLSI 2013: 263-268 - [c42]Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis, Kostas Tsoumanis, Kiamal Z. Pekmestzi:
A radiation tolerant and self-repair memory cell. IOLTS 2013: 210-215 - [c41]Kostas Tsoumanis, Constantinos Efstathiou, Nikolaos Moschopoulos, Kiamal Z. Pekmestzi:
On the design of modulo 2n±1 residue generators. VLSI-SoC 2013: 33-38 - 2012
- [j13]Isidoros Sideris, Kiamal Z. Pekmestzi:
Cost Effective Protection Techniques for TCAM Memory Arrays. IEEE Trans. Computers 61(12): 1778-1788 (2012) - [j12]Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos:
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs. ACM Trans. Design Autom. Electr. Syst. 18(1): 11:1-11:35 (2012) - [j11]Nicholas Axelos, Kiamal Z. Pekmestzi, Dimitris Gizopoulos:
Efficient Memory Repair Using Cache-Based Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2278-2288 (2012) - [c40]Constantinos Efstathiou, Nikolaos Moschopoulos, Kostas Tsoumanis, Kiamal Z. Pekmestzi:
On the Design of Configurable Modulo 2n±1 Residue Generators. DSD 2012: 50-56 - 2011
- [j10]Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi:
High Performance and Area Efficient Flexible DSP Datapath Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 19(3): 429-442 (2011) - [c39]Constantinos Efstathiou, Kiamal Z. Pekmestzi, Nicholas Axelos:
On the Design of Modulo 2^n+1 Multipliers. DSD 2011: 453-459 - 2010
- [c38]Nicholas Axelos, Kiamal Z. Pekmestzi:
A bit level area aware cache-based architecture for memory repairs. IOLTS 2010: 154-158 - [c37]Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos:
Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology. ISCAS 2010: 2598-2601 - [c36]Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos:
Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching. ISVLSI 2010: 104-109 - [c35]Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos:
A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning. ISVLSI (Selected papers) 2010: 117-131 - [c34]Nicholas Axelos, Kiamal Z. Pekmestzi, Nikolaos Moschopoulos:
A New Low-Power Soft-Error Tolerant SRAM Cell. ISVLSI 2010: 399-404 - [c33]Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos:
High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. ISVLSI 2010: 486-487 - [c32]Dimitris Bekiaris, Antonis Papanikolaou, Christos Papameletis, Dimitrios Soudris, George Economakos, Kiamal Z. Pekmestzi:
A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework. PATMOS 2010: 73-83 - [c31]Nikos Anastasiadis, Isidoros Sideris, Kiamal Z. Pekmestzi:
A fast multiplier-less edge detection accelerator for FPGAs. SAC 2010: 510-515 - [c30]Isidoros Sideris, Nikos K. Moshopoulos, Kiamal Z. Pekmestzi:
A hardware peripheral for Java bytecodes translation acceleration. SAC 2010: 552-553 - [c29]Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms. ICSAMOS 2010: 102-109
2000 – 2009
- 2009
- [j9]Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi:
Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths. Integr. 42(4): 486-503 (2009) - [j8]Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos:
Extending an embedded RISC microprocessor for efficient translation based Java execution. Microprocess. Microsystems 33(7-8): 415-429 (2009) - [c28]Sotirios Xydis, Ioannis Triantafyllou, George Economakos, Kiamal Z. Pekmestzi:
Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining. AHS 2009: 407-414 - [c27]Dimitris Bekiaris, Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi:
A design methodology for high-performance and low-leakage fixed-point transpose FIR filters. ICECS 2009: 415-418 - 2008
- [j7]Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos:
A predecoding technique for ILP exploitation in Java processors. J. Syst. Archit. 54(7): 707-728 (2008) - [c26]Sotirios Xydis, George Economakos, Dimitrios Soudris, Kiamal Z. Pekmestzi:
Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility. AHS 2008: 346-353 - [c25]Dimitris Bekiaris, George Economakos, Kiamal Z. Pekmestzi:
Efficient serial and parallel implementation of programmable fir filters based on the merging technique. EUSIPCO 2008: 1-5 - [c24]Sotirios Xydis, Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi:
A flexible architecture for DSP applications combining high performance arithmetic with small scale configurability. EUSIPCO 2008: 1-5 - [c23]Dimitris Bekiaris, Kiamal Z. Pekmestzi, Christos A. Papachristou:
A high-speed radix-4 multiplexer-based array multiplier. ACM Great Lakes Symposium on VLSI 2008: 115-118 - [c22]Kiamal Z. Pekmestzi, Nicholas Axelos, Isidoros Sideris, Nikos K. Moshopoulos:
A BISR Architecture for Embedded Memories. IOLTS 2008: 149-154 - [c21]Isidoros Sideris, Kiamal Z. Pekmestzi, George Economakos:
An instruction set extension for java bytecodes translation acceleration. ICSAMOS 2008: 116-123 - 2007
- [c20]Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi:
A Reconfigurable Arithmetic Data-path Based On Regular Interconnection. AHS 2007: 342-349 - [c19]Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi:
A regular interconnection scheme for efficient mapping of DSP kernels into reconfigurable hardware. EUSIPCO 2007: 1004-1008 - [c18]Isidoros Sideris, Dimitris Pilitsos, George Economakos, Kiamal Z. Pekmestzi:
Building embedded DSP applications in a Java modeling framework. EUSIPCO 2007: 1009-1013 - [c17]Dimitris Bekiaris, Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi:
Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic. ICECS 2007: 1027-1030 - [c16]Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi:
An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding. IOLTS 2007: 71-78 - [c15]Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi:
Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme. ICSAMOS 2007: 137-144 - 2006
- [c14]Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi:
A Large Scale Adaptable Multiplier for Cryptographic Applications. AHS 2006: 477-484 - [c13]Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi:
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems. ICCD 2006: 314-319 - [c12]Paul Bougas, Andreas Tsirikos, Kostas Anagnostopoulos, Isidoros Sideris, Kiamal Z. Pekmestzi:
Segmentation based design of serial parallel multipliers. ISCAS 2006 - [c11]Isidoros Sideris, George Economakos, Kiamal Z. Pekmestzi:
A cache based stack folding technique for high performance Java processors. JTRES 2006: 48-57 - 2005
- [j6]Paul Bougas, Paraskevas Kalivas, Andreas Tsirikos, Kiamal Z. Pekmestzi:
Pipelined array-based FIR filter folding. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(1): 108-118 (2005) - [j5]Paraskevas Kalivas, Vassilis Vassilakis, Chris Meletis, Kiamal Z. Pekmestzi:
A New Low Latency Parallel FIR Filter Scheme. J. VLSI Signal Process. 39(3): 313-322 (2005) - [c10]E. Chaniotakis, Paraskevas Kalivas, Kiamal Z. Pekmestzi:
Long Number Bit-Serial Squarers. IEEE Symposium on Computer Arithmetic 2005: 29-36 - [c9]Paraskevas Kalivas, Andreas Tsirikos, Paul Bougas, Kiamal Z. Pekmestzi:
100% operational efficient bit-serial programmable FIR digital filters. EUSIPCO 2005: 1-4 - [c8]Isidoros Sideris, Kostas Anagnostopoulos, Paraskevas Kalivas, Kiamal Z. Pekmestzi:
Novel systolic schemes for serial-parallel multiplication. EUSIPCO 2005: 1-4 - 2004
- [c7]Paraskevas Kalivas, Paul Bougas, Vassilis Vassilakis, Christos Meletis, Kiamal Z. Pekmestzi:
Pipeline array implementation of FIR filters. EUSIPCO 2004: 957-960 - [c6]Paraskevas Kalivas, Kiamal Z. Pekmestzi, Paul Bougas, Andreas Tsirikos, Kostas Gotsis:
Low-latency and high-efficiency bit serial-serial multipliers. EUSIPCO 2004: 1345-1348 - 2002
- [j4]Kiamal Z. Pekmestzi, Nikos K. Moshopoulos:
A Systolic, High Speed Architecture for an RSA Cryptosystem. J. VLSI Signal Process. 32(3): 223-235 (2002) - 2001
- [j3]Kiamal Z. Pekmestzi, Nikos K. Moshopoulos:
A bit-interleaved systolic architecture for a high-speed RSA system. Integr. 30(2): 169-175 (2001) - [c5]Kostas Marinis, Nikos K. Moshopoulos, Fotis Karoubalis, Kiamal Z. Pekmestzi:
On the Hardware Implementation of the 3GPP Confidentiality and Integrity Algorithms. ISC 2001: 248-265 - [c4]Nikos K. Moshopoulos, Kiamal Z. Pekmestzi:
A Novel Systolic Architecture for Efficient RSA Implementation. Public Key Cryptography 2001: 416-421 - 2000
- [j2]Kiamal Z. Pekmestzi, Paraskevas Kalivas:
Constant Number Serial Pipeline Multipliers. J. VLSI Signal Process. 26(3): 361-368 (2000) - [c3]Kiamal Z. Pekmestzi, Nikolaos Moshopoulos, Paraskevas Kalivas:
A systolic serial squarer of continuous operation. EUSIPCO 2000: 1-4
1990 – 1999
- 1998
- [c2]Christos Gr. Caraiscos, Kiamal Z. Pekmestzi:
A scheme for the VLSI implementation of FIR digital filters with reduced latency. EUSIPCO 1998: 1-4 - 1997
- [c1]George Economakos, George K. Papakonstantinou, Kiamal Z. Pekmestzi, Panayotis Tsanakas:
Hardware compilation using attribute grammars. CHARME 1997: 273-290 - 1996
- [j1]Christos Gr. Caraiscos, Kiamal Z. Pekmestzi:
Systolic digital filters with reduced latency - serial implementation. Int. J. Circuit Theory Appl. 24(4): 453-466 (1996)
Coauthor Index
Costas Efstathiou
aka: Constantinos Efstathiou
aka: Constantinos Efstathiou
Nikolaos Eftaxiopoulos-Sarris
aka: Nikolaos Eftaxiopoulos
aka: Nikolaos Eftaxiopoulos
Nikolaos Moschopoulos
aka: Nikos K. Moshopoulos
aka: Nikos K. Moshopoulos
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-07 21:21 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
