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2020 – today
- 2024
[j26]Gino A. Chacon
, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz, Vassos Soteriou:
Coherence Attacks and Countermeasures in Interposer-based Chiplet Systems. ACM Trans. Archit. Code Optim. 21(2): 23 (2024)- [c63]Luke McHale, Paul V. Gratz, Alex Sprintson:
Flow Correlator: A Flow Table Cache Management Strategy. ICCCN 2024: 1-9 - [c62]Erick Carvajal Barboza, Mahesh Ketkar, Paul Gratz, Jiang Hu:
Aiding Microprocessor Performance Validation with Machine Learning. ISPASS 2024: 1-9 - [i11]Bhargav Reddy Godala, Sankara Prasad Ramesh, Krishnam Tibrewala, Chrysanthos Pepi, Gino Chacon, Svilen Kanev, Gilles A. Pokam, Daniel A. Jiménez, Paul V. Gratz, David I. August:
Correct Wrong Path. CoRR abs/2408.05912 (2024) - [i10]Chrysanthos Pepi, Bhargav Reddy Godala, Krishnam Tibrewala, Gino Chacon, Paul V. Gratz, Daniel A. Jiménez, Gilles A. Pokam, David I. August:
Exposing Shadow Branches. CoRR abs/2408.12592 (2024) - 2023
- [j25]Daniel A. Jiménez, Elvira Teran, Paul V. Gratz:
Last-Level Cache Insertion and Promotion Policy in the Presence of Aggressive Prefetching. IEEE Comput. Archit. Lett. 22(1): 17-20 (2023) - [j24]Mian Qin, Qing Zheng, Jason Lee, Bradley W. Settlemyer, Fei Wen, A. L. Narasimha Reddy, Paul Gratz:
KVRangeDB: Range Queries for a Hash-based Key-Value Device. ACM Trans. Storage 19(3): 24:1-24:21 (2023) - [c61]Gino Chacon, Nathan Gober, Krishnendra Nathella, Paul V. Gratz, Daniel A. Jiménez:
A Characterization of the Effects of Software Instruction Prefetching on an Aggressive Front-end. ISPASS 2023: 61-70 - [i9]Erick Carvajal Barboza, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu:
Machine Learning for Microprocessor Performance Bug Localization. CoRR abs/2303.15280 (2023) - [i8]Luke McHale, Paul V. Gratz, Alex Sprintson:
Flow Correlator: A Flow Table Cache Management Strategy. CoRR abs/2305.02918 (2023) - 2022
- [j23]Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz:
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. IEEE Comput. Archit. Lett. 21(2): 133-136 (2022) - [j22]Ping Wang, Fei Wen, Paul V. Gratz, Alex Sprintson:
SIMD-Matcher: A SIMD-based Arbitrary Matching Framework. ACM Trans. Archit. Code Optim. 19(3): 30:1-30:20 (2022) - [j21]Chandrahas Tirumalasetty, Chih-Chieh Chou, A. L. Narasimha Reddy, Paul Gratz, Ayman Abouelwafa:
Reducing Minor Page Fault Overheads through Enhanced Page Walker. ACM Trans. Archit. Code Optim. 19(4): 57:1-57:26 (2022) - [j20]Fei Wen, Mian Qin, Paul Gratz, A. L. Narasimha Reddy:
Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems. ACM Trans. Embed. Comput. Syst. 21(1): 8:1-8:18 (2022) - [c60]Hossein Farrokhbakht, Paul V. Gratz, Tushar Krishna, Joshua San Miguel, Natalie D. Enright Jerger:
Stay in your Lane: A NoC with Low-overhead Multi-packet Bypassing. HPCA 2022: 957-970 - [c59]Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez:
SLAP-CC: Set-Level Adaptive Prefetching for Compressed Caches. ICCD 2022: 50-58 - [c58]Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul V. Gratz, Daniel A. Jiménez, Samira Mirbagher Ajorpaz:
Composite Instruction Prefetching. ICCD 2022: 471-478 - [c57]Georgios Vavouliotis, Gino Chacon, Lluc Alvarez, Paul V. Gratz, Daniel A. Jiménez, Marc Casas:
Page Size Aware Cache Prefetching. MICRO 2022: 956-974 - [i7]Gino A. Chacon, Charles Williams, Johann Knechtel, Ozgur Sinanoglu, Paul V. Gratz:
Hardware Trojan Threats to Cache Coherence in Modern 2.5D Chiplet Systems. CoRR abs/2210.00058 (2022) - [i6]Nathan Gober, Gino Chacon, Lei Wang, Paul V. Gratz, Daniel A. Jiménez, Elvira Teran, Seth H. Pugsley, Jinchun Kim:
The Championship Simulator: Architectural Simulation for Education and Competition. CoRR abs/2210.14324 (2022) - 2021
- [c56]Fei Wen, Mian Qin, Paul Gratz, A. L. Narasimha Reddy:
OpenMem: Hardware/Software Cooperative Management for Mobile Memory System. DAC 2021: 109-114 - [c55]Ahmad M. Radaideh, Paul V. Gratz:
CMRC: Comprehensive Microarchitectural Register Coalescing for GPGPUs. DATE 2021: 1803-1808 - [c54]Fei Wen, Mian Qin, Paul Gratz, A. L. Narasimha Reddy:
An FPGA-based Hybrid Memory Emulation System. FPL 2021: 190-196 - [c53]Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu:
Automatic Microprocessor Performance Bug Detection. HPCA 2021: 545-556 - [c52]Hossein Farrokhbakht, Henry Kao, Kamran Hasan, Paul V. Gratz, Tushar Krishna, Joshua San Miguel, Natalie D. Enright Jerger:
Pitstop: Enabling a Virtual Network Free Network-on-Chip. HPCA 2021: 682-695 - [c51]Mayank Parasar, Natalie D. Enright Jerger, Paul V. Gratz, Joshua San Miguel, Tushar Krishna:
SEEC: stochastic escape express channel. SC 2021: 34 - [c50]Mian Qin, A. L. Narasimha Reddy, Paul V. Gratz, Rekha Pitchumani, Yang-Seok Ki:
KVRAID: high performance, write efficient, update friendly erasure coding scheme for KV-SSDs. SYSTOR 2021: 3:1-3:12 - [i5]Tapojyoti Mandal, Gino Chacon, Johann Knechtel, Ozgur Sinanoglu, Paul Gratz, Vassos Soteriou:
Interposer-Based Root of Trust. CoRR abs/2105.02917 (2021) - [i4]Chandrahas Tirumalasetty, Chih-Chieh Chou, A. L. Narasimha Reddy, Paul Gratz, Ayman Abouelwafa:
Reducing Minor Page Fault Overheads through Enhanced Page Walker. CoRR abs/2112.14013 (2021) - 2020
- [j19]Chih-Chieh Chou, Jaemin Jung, A. L. Narasimha Reddy, Paul V. Gratz, Doug Voigt:
Virtualize and share non-volatile memories in user space. CCF Trans. High Perform. Comput. 2(1): 16-35 (2020) - [j18]Fei Wen, Mian Qin, Paul V. Gratz, A. L. Narasimha Reddy:
Hardware Memory Management for Future Mobile Hybrid Memory Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(11): 3627-3637 (2020) - [c49]Mian Qin, Joo Hwan Lee, Rekha Pitchumani, Yang-Seok Ki, A. L. Narasimha Reddy, Paul V. Gratz:
A Generic FPGA Accelerator for Minimum Storage Regenerating Codes. ASP-DAC 2020: 271-276 - [c48]Ahmad M. Radaideh, Paul V. Gratz:
Exploiting Zero Data to Reduce Register File and Execution Unit Dynamic Power Consumption in GPGPUs. DAC 2020: 1-6 - [c47]Mayank Parasar, Hossein Farrokhbakht, Natalie D. Enright Jerger, Paul V. Gratz, Tushar Krishna, Joshua San Miguel:
DRAIN: Deadlock Removal for Arbitrary Irregular Networks. HPCA 2020: 447-460 - [c46]Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez:
SB-Fetch: synchronization aware hardware prefetching for chip multiprocessors. ICS 2020: 15:1-15:12 - [i3]Fei Wen, Mian Qin, Paul Gratz, A. L. Narasimha Reddy:
Hardware Memory Management for Future Mobile Hybrid Memory Systems. CoRR abs/2004.05518 (2020) - [i2]Fei Wen, Mian Qin, Paul V. Gratz, A. L. Narasimha Reddy:
FPGA-based Hyrbid Memory Emulation System. CoRR abs/2011.04567 (2020) - [i1]Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu:
Automatic Microprocessor Performance Bug Detection. CoRR abs/2011.08781 (2020)
2010 – 2019
- 2019
- [j17]Aniruddh Ramrakhyani, Paul V. Gratz, Tushar Krishna:
Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom. IEEE Micro 39(3): 110-117 (2019) - [j16]Ping Wang, Luke McHale, Paul V. Gratz, Alex Sprintson:
GenMatcher: A Generic Clustering-Based Arbitrary Matching Framework. ACM Trans. Archit. Code Optim. 15(4): 51:1-51:22 (2019) - [c45]Paul Gratz:
The Best of IEEE Computer Architecture Letters in 2018. HPCA 2019: 491 - [c44]Pooria M. Yaghini, George Michelogiannakis, Paul V. Gratz:
SpecLock: Speculative Lock Forwarding. ICCD 2019: 273-282 - [c43]Eshan Bhatia, Gino Chacon, Seth H. Pugsley, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez:
Perceptron-based prefetch filtering. ISCA 2019: 1-13 - [c42]Mayank Parasar, Natalie D. Enright Jerger, Paul V. Gratz, Joshua San Miguel, Tushar Krishna:
SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution. MICRO 2019: 873-885 - [c41]Chih-Chieh Chou, Jaemin Jung, A. L. Narasimha Reddy, Paul V. Gratz, Doug Voigt:
vNVML: An Efficient User Space Library for Virtualizing and Sharing Non-Volatile Memories. MSST 2019: 103-115 - [c40]Chih-Chieh Chou, Yuan Chen, Dejan S. Milojicic, A. L. Narasimha Reddy, Paul Gratz:
Optimizing Post-Copy Live Migration with System-Level Checkpoint Using Fabric-Attached Memory. MCHPC@SC 2019: 16-24 - 2018
- [j15]Laith M. AlBarakat, Paul V. Gratz, Daniel A. Jiménez:
MTB-Fetch: Multithreading Aware Hardware Prefetching for Chip Multiprocessors. IEEE Comput. Archit. Lett. 17(2): 175-178 (2018) - [j14]Yoon Seok Yang, Hrishikesh Deshpande, Gwan Choi, Paul V. Gratz:
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 545-558 (2018) - [j13]Sébastien Le Beux, Paul V. Gratz, Ian O'Connor:
Guest Editorial: Emerging Technologies and Architectures for Manycore Computing Part 1: Hardware Techniques. IEEE Trans. Multi Scale Comput. Syst. 4(2): 97-98 (2018) - [c39]Aniruddh Ramrakhyani, Paul V. Gratz, Tushar Krishna:
Synchronized Progress in Interconnection Networks (SPIN): A New Theory for Deadlock Freedom. ISCA 2018: 699-711 - 2017
- [c38]Jinchun Kim, Elvira Teran, Paul V. Gratz, Daniel A. Jiménez, Seth H. Pugsley, Chris Wilkerson:
Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy. ASPLOS 2017: 737-749 - [c37]P. Madhukar Reddy, Stavros Hadjitheophanous, Vassos Soteriou, Paul V. Gratz, Maria K. Michael:
Minimal exercise vector generation for reliability improvement. IOLTS 2017: 113-119 - [c36]Viacheslav V. Fedorov, Jinchun Kim, Mian Qin, Paul V. Gratz, A. L. Narasimha Reddy:
Speculative paging for future NVM storage. MEMSYS 2017: 399-410 - 2016
- [j12]Jae-Yeon Won, Paul V. Gratz, Srinivas Shakkottai, Jiang Hu:
Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory. ACM Trans. Design Autom. Electr. Syst. 21(4): 69:1-69:25 (2016) - [j11]Mukund Ramakrishna, Vamsi Krishna Kodati, Paul V. Gratz, Alexander Sprintson:
GCA: Global Congestion Awareness for Load Balance in Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. 27(7): 2022-2035 (2016) - [c35]Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, Zeshan Chishti:
Path confidence based lookahead prefetching. MICRO 2016: 60:1-60:12 - 2015
- [j10]Hyungjun Kim, Siva Bhanu Krishna Boga, Arseniy Vitkovskiy, Stavros Hadjitheophanous, Paul V. Gratz, Vassos Soteriou, Maria K. Michael:
Use It or Lose It: Proactive, Deterministic Longevity in Future Chip Multiprocessors. ACM Trans. Design Autom. Electr. Syst. 20(4): 65:1-65:26 (2015) - [c34]Hyunjun Jang, Jinchun Kim, Paul Gratz, Ki Hwan Yum, Eun Jung Kim:
Bandwidth-efficient on-chip interconnect designs for GPGPUs. DAC 2015: 9:1-9:6 - [c33]David Kadjo, Raid Ayoub, Michael Kishinevsky, Paul V. Gratz:
A control-theoretic approach for energy efficient CPU-GPU subsystem in mobile platforms. DAC 2015: 62:1-62:6 - [c32]Arseniy Vitkovskiy, Vassos Soteriou, Paul V. Gratz:
Clotho: Proactive wearout deceleration in Chip-Multiprocessor interconnects. ICCD 2015: 117-124 - [c31]Andrew D. Targhetta, Donald E. Owen, Francis L. Israel, Paul V. Gratz:
Energy-efficient implementations of GF (p) and GF(2m) elliptic curve cryptography. ICCD 2015: 704-711 - [c30]Jae-Yeon Won, Paul Gratz, Srinivas Shakkottai, Jiang Hu:
Having your cake and eating it too: Energy savings without performance loss through resource sharing driven power management. ISLPED 2015: 255-260 - [c29]Jinchun Kim, Viacheslav V. Fedorov, Paul V. Gratz, A. L. Narasimha Reddy:
Dynamic Memory Pressure Aware Ballooning. MEMSYS 2015: 103-112 - [c28]Viacheslav V. Fedorov, A. L. Narasimha Reddy, Paul V. Gratz:
Shared Last-Level Caches and The Case for Longer Timeslices. MEMSYS 2015: 113-120 - [c27]Arseni Vitkovski, Vassos Soteriou, Paul V. Gratz:
Wear-Aware Adaptive Routing for Networks-on-Chips. NOCS 2015: 28:1-28:2 - 2014
- [j9]Hyungjun Kim, Boris Grot, Paul V. Gratz, Daniel A. Jiménez:
Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip. IEEE Trans. Computers 63(3): 543-556 (2014) - [j8]Cheng Li, Mark Browning, Paul V. Gratz, Samuel Palermo:
LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 826-838 (2014) - [j7]Yoon Seok Yang, Reeshav Kumar, Gwan S. Choi, Paul V. Gratz:
WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture. ACM Trans. Design Autom. Electr. Syst. 19(4): 34:1-34:22 (2014) - [c26]Ehsan Fatehi, Paul Gratz:
ILP and TLP in shared memory applications: a limit study. PACT 2014: 113-126 - [c25]Jae-Yeon Won, Xi Chen, Paul Gratz, Jiang Hu, Vassos Soteriou:
Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management. HPCA 2014: 308-319 - [c24]Luke McHale, C. Jasson Casey, Paul V. Gratz, Alex Sprintson:
Stochastic Pre-classification for SDN Data Plane Matching. ICNP 2014: 596-602 - [c23]Andrew D. Targhetta, Donald E. Owen, Paul V. Gratz:
The design space of ultra-low energy asymmetric cryptography. ISPASS 2014: 55-65 - [c22]David Kadjo, Jinchun Kim, Prabal Sharma, Reena Panda, Paul Gratz, Daniel A. Jiménez:
B-Fetch: Branch Prediction Directed Prefetching for Chip-Multiprocessors. MICRO 2014: 623-634 - [c21]Shalimar Rasheed, Paul V. Gratz, Srinivas Shakkottai, Jiang Hu:
STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip. NOCS 2014: 176-177 - [c20]David Kadjo, Ümit Y. Ogras, Raid Ayoub, Michael Kishinevsky, Paul Gratz:
Towards platform level power management in mobile systems. SoCC 2014: 146-151 - 2013
- [j6]Viacheslav V. Fedorov, Sheng Qiu, A. L. Narasimha Reddy, Paul V. Gratz:
ARI: Adaptive LLC-memory traffic management. ACM Trans. Archit. Code Optim. 10(4): 46:1-46:19 (2013) - [j5]Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras:
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches. ACM Trans. Design Autom. Electr. Syst. 18(4): 47:1-47:21 (2013) - [c19]Xi Chen, Zheng Xu, Hyungjun Kim, Paul V. Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras, Raid Zuhair Ayoub:
Dynamic voltage and frequency scaling for shared resources in multicore processor designs. DAC 2013: 114:1-114:7 - [c18]Pritha Ghoshal, C. Jasson Casey, Paul V. Gratz, Alex Sprintson:
Stochastic Pre-Classification for Software Defined Firewalls. ICCCN 2013: 1-8 - [c17]David Kadjo, Hyungjun Kim, Paul Gratz, Jiang Hu, Raid Ayoub:
Power gating with block migration in chip-multiprocessor last-level caches. ICCD 2013: 93-99 - [c16]Reeshav Kumar, Hrishikesh Deshpande, Gwan S. Choi, Alexander Sprintson, Paul Gratz:
Bidirectional interconnect design for low latency high bandwidth NoC. ICICDT 2013: 215-218 - [c15]Hyungjun Kim, Arseniy Vitkovskiy, Paul V. Gratz, Vassos Soteriou:
Use it or lose it: wear-out and lifetime in future chip multiprocessors. MICRO 2013: 136-147 - [c14]Mukund Ramakrishna, Paul V. Gratz, Alexander Sprintson:
GCA: Global congestion awareness for load balance in Networks-on-Chip. NOCS 2013: 1-8 - [c13]Mark Browning, Cheng Li, Paul V. Gratz, Samuel Palermo:
LumiNOC: A low-latency, high-bandwidth per Watt, photonic Network-on-Chip. SLIP 2013: 1-4 - 2012
- [j4]Reena Panda, Paul V. Gratz, Daniel A. Jiménez:
B-Fetch: Branch Prediction Directed Prefetching for In-Order Processors. IEEE Comput. Archit. Lett. 11(2): 41-44 (2012) - [c12]Cheng Li, Mark Browning, Paul V. Gratz, Samuel Palermo:
LumiNOC: a power-efficient, high-performance, photonic network-on-chip for future parallel architectures. PACT 2012: 421-422 - [c11]Yoon Seok Yang, Reeshav Kumar, Gwan Choi, Paul Gratz:
WaveSync: A low-latency source synchronous bypass network-on-chip architecture. ICCD 2012: 241-248 - [c10]Yoon Seok Yang, Hrishikesh Deshpande, Gwan S. Choi, Paul Gratz:
Exploiting path diversity for low-latency and high-bandwidth with the dual-path NoC router. ISCAS 2012: 2433-2436 - [c9]Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz, Jiang Hu, Michael Kishinevsky, Ümit Y. Ogras:
In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches. NOCS 2012: 43-50 - 2011
- [j3]Tushar N. K. Jain, Mukund Ramakrishna, Paul V. Gratz, Alexander Sprintson, Gwan Choi:
Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(11): 1663-1676 (2011) - [c8]Hyungjun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz, Daniel A. Jiménez:
Reducing network-on-chip energy consumption through spatial locality speculation. NOCS 2011: 233-240 - [c7]Swapnil Lotlikar, Vinayak Pai, Paul V. Gratz:
AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation. VLSI Design 2011: 147-152 - 2010
- [j2]Hyungjun Kim, Paul V. Gratz:
Leveraging Unused Cache Block Words to Reduce Power in CMP Interconnect. IEEE Comput. Archit. Lett. 9(1): 33-36 (2010) - [c6]Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi:
Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs. NOCS 2010: 51-58
2000 – 2009
- 2009
- [c5]Mark Gebhart, Bertrand A. Maher, Katherine E. Coons, Jeffrey R. Diamond, Paul Gratz, Mario Marino, Nitya Ranganathan, Behnam Robatmili, Aaron Smith, James H. Burrill, Stephen W. Keckler, Doug Burger, Kathryn S. McKinley:
An evaluation of the TRIPS computer system. ASPLOS 2009: 1-12 - 2008
- [c4]Paul Gratz, Boris Grot, Stephen W. Keckler:
Regional congestion awareness for load balance in networks-on-chip. HPCA 2008: 203-214 - 2007
- [j1]Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger:
On-Chip Interconnection Networks of the TRIPS Chip. IEEE Micro 27(5): 41-50 (2007) - [c3]Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger:
Implementation and Evaluation of a Dynamically Routed Processor Operand Network. NOCS 2007: 7-17 - 2006
- [c2]Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger:
Implementation and Evaluation of On-Chip Network Architectures. ICCD 2006: 477-484 - [c1]Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger:
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. MICRO 2006: 480-491
Coauthor Index
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