extended-abstract

Wear-Aware Adaptive Routing for Networks-on-Chips

Authors:

Arseniy Vitkovski,

Vassos Soteriou,

Paul V. GratzAuthors Info & Claims

NOCS '15: Proceedings of the 9th International Symposium on Networks-on-Chip

Article No.: 28, Pages 1 - 2

https://doi.org/10.1145/2786572.2786573

Published: 28 September 2015 Publication History

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Abstract

Chip-multiprocessors are facing worsening reliability due to prolonged operational stresses, with their tile-interconnecting Network-on-Chip (NoC) being especially vulnerable to wearout-induced failure. To tackle this ominous threat we present a novel wear-aware routing algorithm that continuously considers the stresses the NoC experiences at runtime, along with temperature and fabrication process variation metrics, steering traffic away from locations that are most prone to Electromigration (EM)- and Hot-Carrier Injection (HCI)-induced wear. Under realistic applications our wear-aware algorithm yields 66% and 8% average increases in mean-time-to-failure for EM and HCI, respectively.

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Index Terms

Wear-Aware Adaptive Routing for Networks-on-Chips
1. Hardware

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Published In

NOCS '15: Proceedings of the 9th International Symposium on Networks-on-Chip

September 2015

233 pages

ISBN:9781450333962

DOI:10.1145/2786572

General Chairs:
Andre Ivanov
University of British Columbia, Canada
,
Diana Marculescu
Carnegie Mellon University, USA
,
Program Chairs:
Partha Pratim Pande
Washington State University, USA
,
José Flich
Universitat Politècnica de València, Spain
,
Publications Chair:
Karthik Pattabiraman
University of British Columbia, Canada

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 28 September 2015

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Extended-abstract
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Refereed limited

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NOCS '15

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NOCS '15: International Symposium on Networks-on-Chip

September 28 - 30, 2015

BC, Vancouver, Canada

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Overall Acceptance Rate 14 of 44 submissions, 32%

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