research-article

Methods for fault tolerance in networks-on-chip

Authors:

Martin Radetzki,

Axel JantschAuthors Info & Claims

ACM Computing Surveys (CSUR), Volume 46, Issue 1

Article No.: 8, Pages 1 - 38

https://doi.org/10.1145/2522968.2522976

Published: 11 July 2013 Publication History

Abstract

Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. The most important results are summarized and open research problems and challenges are highlighted to guide future research on this topic.

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Index Terms

Methods for fault tolerance in networks-on-chip
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Multiple instruction, multiple data
2. General and reference
  1. Document types
    1. Surveys and overviews

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cover image ACM Computing Surveys

ACM Computing Surveys Volume 46, Issue 1

October 2013

551 pages

ISSN:0360-0300

EISSN:1557-7341

DOI:10.1145/2522968

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Published: 11 July 2013

Accepted: 01 January 2013

Revised: 01 September 2012

Received: 01 February 2012

Published in CSUR Volume 46, Issue 1

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