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ORCIDHideyuki Ichihara
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2020 – today
- 2024
[c42]Jun-Tsung Wu, Hideyuki Ichihara, Tomoo Inoue, Tong-Yu Hsieh:
On Accuracy Enhancement of No-Reference Error-Tolerability Testing for Images in Object Detection Applications Based on RGB Channel Characteristics. ITC-Asia 2024: 1-6- 2023
- [c41]Tamaki Kozuma, Qilin Wang, Hideyuki Ichihara, Tomoo Inoue:
Reliability Analysis of Approximate Multipliers with Recovery Schemes. ATS 2023: 1-6 - [c40]Naoki Okuda, Kaori Maeda, Chisa Takano, Hideyuki Ichihara:
A Resource Estimation Method in Multi-Cloud Environment with a Model Based on a Repairable-Item Inventory System. COMPSAC 2023: 1113-1120 - 2022
- [c39]Hideyuki Ichihara, Naruki Itoh, Tomoo Inoue:
An Improvement of the No-Reference Test Scheme Based on False Edge Detection for Image Processing Application. ITC-Asia 2022: 90-95 - 2021
- [c38]Hideyuki Ichihara, Kazunori Yukihiro, Tomoo Inoue:
A Design of Approximate Voting Schemes for Fail-Operational Systems. ATS 2021: 121-126 - [c37]Hideyuki Ichihara, Takayuki Fukuda, Tomoo Inoue:
A Design of Reliable Linear FSMs with Equivalent States in Stochastic Computing. DFT 2021: 1-6 - 2020
- [j14]Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue:
Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(12): 1464-1471 (2020)
2010 – 2019
- 2019
- [j13]Hideyuki Ichihara
, Tatsuyoshi Sugino, Shota Ishii, Tsuyoshi Iwagaki, Tomoo Inoue:
Compact and Accurate Digital Filters Based on Stochastic Computing. IEEE Trans. Emerg. Top. Comput. 7(1): 31-43 (2019) - [c36]Hideyuki Ichihara, Yuki Maeda, Tsuyoshi Iwagaki, Tomoo Inoue:
State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines. DFT 2019: 1-6 - [c35]Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue:
An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis. ITC-Asia 2019: 55-60 - 2017
- [c34]Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue:
State assignment for fault tolerant stochastic computing with linear finite state machines. ITC-Asia 2017: 156-161 - 2015
- [c33]Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue:
A fault tolerant response analyzer with self-error-correction capability. ETS 2015: 1-2 - [c32]Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue:
A practical approach for logic simplification based on fault acceptability for error tolerant application. ETS 2015: 1-2 - [c31]Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue:
Designing area-efficient controllers for multi-cycle transient fault tolerant systems. ETS 2015: 1-2 - [c30]Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue:
Logic simplification by minterm complement for error tolerant application. ICCD 2015: 94-100 - 2014
- [c29]Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue:
Scheduling algorithm in datapath synthesis for long duration transient fault tolerance. DFT 2014: 128-133 - [c28]Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue:
Compact and accurate stochastic circuits with shared random number sources. ICCD 2014: 361-366 - 2013
- [c27]Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue:
A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test. Asian Test Symposium 2013: 85-90 - 2012
- [c26]Tsuyoshi Iwagaki, Takehiro Mikami, Hideyuki Ichihara, Tomoo Inoue:
Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool. APCCAS 2012: 615-618 - [c25]Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue:
Modeling economics of LSI design and manufacturing for test design selection. ICCD 2012: 516-517 - 2011
- [j12]Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue:
Hybrid Test Application in Partial Skewed-Load Scan Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2571-2578 (2011) - [c24]Hideyuki Ichihara, Yuka Iwamoto, Yuki Yoshikawa, Tomoo Inoue:
Test Compression Based on Lossy Image Encoding. Asian Test Symposium 2011: 273-278 - [c23]Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara:
High-level synthesis for multi-cycle transient fault tolerant datapaths. IOLTS 2011: 13-18 - 2010
- [j11]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara:
Design and Optimization of Transparency-Based TAM for SoC Test. IEICE Trans. Inf. Syst. 93-D(6): 1549-1559 (2010) - [j10]Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue:
A Practical Threshold Test Generation for Error Tolerant Application. IEICE Trans. Inf. Syst. 93-D(10): 2776-2782 (2010) - [c22]Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara:
A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic. DELTA 2010: 345-349 - [c21]Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue:
Hybrid test application in hybrid delay scan design. ETS 2010: 247 - [c20]Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue:
An FPGA-based fail-soft system with adaptive reconfiguration. IOLTS 2010: 127-132
2000 – 2009
- 2009
- [c19]Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue:
A Practical Approach to Threshold Test Generation for Error Tolerant Circuits. Asian Test Symposium 2009: 171-176 - [c18]Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue:
Reliability and Performance Analysis of FPGA-Based Fault Tolerant System. DFT 2009: 245-253 - 2008
- [j9]Hideyuki Ichihara, Tomoyuki Saiki, Tomoo Inoue:
An Architecture of Embedded Decompressor with Reconfigurability for Test Compression. IEICE Trans. Inf. Syst. 91-D(3): 713-719 (2008) - [j8]Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara:
A Self-Test of Dynamically Reconfigurable Processors with Test Frames. IEICE Trans. Inf. Syst. 91-D(3): 756-762 (2008) - 2007
- [j7]Hideyuki Ichihara, Toshihiro Ohara, Michihiro Shintani, Tomoo Inoue:
A Variable-Length Coding Adjustable for Compressed Test Application. IEICE Trans. Inf. Syst. 90-D(8): 1235-1242 (2007) - [j6]Hideyuki Ichihara, Toshimasa Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita:
A statistical error model for image sensors and its testing. Syst. Comput. Jpn. 38(11): 1-11 (2007) - [c17]Hideyuki Ichihara, Yukinori Setohara, Yusuke Nakashima, Tomoo Inoue:
Test Compression / Decompression Based on JPEG VLC Algorithm. ATS 2007: 87-90 - [c16]Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara:
Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors. ETS 2007: 117-124 - [c15]Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara:
TAM Design and Optimization for Transparency-Based SoC Test. VTS 2007: 381-388 - 2006
- [j5]Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue:
An Adaptive Decompressor for Test Application with Variable-Length Coding. Inf. Media Technol. 1(2): 909-917 (2006) - [c14]Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue:
A Reconfigurable Embedded Decompressor for Test Compression. DELTA 2006: 301-308 - 2005
- [j4]Hideyuki Ichihara, Michihiro Shintani, Tomoo Inoue:
Huffman-Based Test Response Coding. IEICE Trans. Inf. Syst. 88-D(1): 158-161 (2005) - [j3]Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu:
Test cost reduction for logic circuits: Reduction of test data volume and test application time. Syst. Comput. Jpn. 36(6): 69-83 (2005) - [c13]Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue:
A Huffman-based coding with efficient test application. ASP-DAC 2005: 75-78 - [c12]Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara:
An Effective Design for Hierarchical Test Generation Based on Strong Testability. Asian Test Symposium 2005: 288-293 - 2004
- [c11]Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue:
A Test Decompression Scheme for Variable-Length Coding. Asian Test Symposium 2004: 426-431 - 2003
- [j2]Hideyuki Ichihara, Tomoo Inoue:
A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3072-3078 (2003) - [c10]Hideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, Tomoo Inoue:
Test Response Compression Based on Huffman Coding. Asian Test Symposium 2003: 446-451 - [c9]Hideyuki Ichihara, Tomoo Inoue:
Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG. DATE 2003: 11180-11181 - [c8]Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa:
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. VLSI Design 2003: 329-334 - 2002
- [c7]Hideyuki Ichihara, Tomoo Inoue:
Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding. DELTA 2002: 396-402 - 2001
- [c6]Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura:
Dynamic Test Compression Using Statistical Coding. Asian Test Symposium 2001: 143- - 2000
- [c5]Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy:
Test Transformation to Improve Compaction by Statistical Encoding. VLSI Design 2000: 294-299
1990 – 1999
- 1999
- [c4]Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium 1999: 147-152 - [c3]Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On Test Generation with A Limited Number of Tests. Great Lakes Symposium on VLSI 1999: 12-15 - 1998
- [c2]Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita:
An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. Asian Test Symposium 1998: 58-63 - 1997
- [j1]Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
On invariant implication relations for removing partial circuits. Syst. Comput. Jpn. 28(7): 39-47 (1997) - [c1]Hideyuki Ichihara, Kozo Kinoshita:
On Acceleration of Logic Circuits Optimization Using Implication Relations. Asian Test Symposium 1997: 222-227
Coauthor Index
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last updated on 2024-10-15 20:46 CEST by the dblp team
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