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ORCIDSreedhar Natarajan
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2010 – 2019
- 2014
[c16]Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang:
13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. ISSCC 2014: 238-239- [c15]Meng-Fan Chang, Jui-Jen Wu, Tun-Fei Chien, Yen-Chen Liu, Ting-Chin Yang, Wen-Chao Shen, Ya-Chin King, Chorng-Jung Lin, Ku-Feng Lin, Yu-Der Chih, Sreedhar Natarajan, Tsung-Yung Jonathan Chang:
19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme. ISSCC 2014: 332-333 - 2013
- [c14]Hung-Chang Yu, Kai-Chun Lin, Ku-Feng Lin, Chin-Yi Huang, Yu-Der Chih, Tong-Chern Ong, Tsung-Yung Jonathan Chang, Sreedhar Natarajan, Luan C. Tran:
Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology. ISSCC 2013: 224-225 - [c13]Jonathan Chang, Yen-Huei Chen, Hank Cheng, Wei-Min Chan, Hung-Jen Liao, Quincy Li, Stanley Chang, Sreedhar Natarajan, Robin Lee, Ping-Wei Wang, Shyue-Shyh Lin, Chung-Cheng Wu, Kuan-Lun Cheng, Min Cao, George H. Chang:
A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications. ISSCC 2013: 316-317 - [c12]Caleb Y.-S. Cho, J. C. Wang, Lion Huang, Milo Weng, Yu-Fan Lin, Chia-Fu Lee, C. W. Lien, H. C. Feng, Tassa Yang, S. P. Liao, J. J. Wu, Yu-Der Chih, Sreedhar Natarajan:
A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash. VLSI-DAT 2013: 1-4 - [c11]Hung-Chang Yu, Ku-Feng Lin, Kai-Chun Lin, Yu-Der Chih, Sreedhar Natarajan:
A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V. VLSI-DAT 2013: 1-4 - 2012
- [c10]Qunzhi Zhou, Sreedhar Natarajan, Yogesh Simmhan
, Viktor K. Prasanna:
Semantic Information Modeling for Emerging Applications in Smart Grid. ITNG 2012: 775-782 - 2011
- [c9]Yogesh L. Simmhan, Viktor K. Prasanna, Saima Aman, Sreedhar Natarajan, Wei Yin, Qunzhi Zhou:
Toward data-driven demand-response optimization in a campus microgrid. BuildSys@SenSys 2011: 41-42
2000 – 2009
- 2008
- [j7]David Money Harris, Sreedhar Natarajan, Ram K. Krishnamurthy, Siva G. Narendra:
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 43(1): 3-5 (2008) - [c8]Sreedhar Natarajan, Nicky Lu:
Private Equity: Fight them or Invite them. ISSCC 2008: 156-157 - [c7]Sergey Romanovsky, Atul Katoch, Arun Achyuthan, C. O'Connell, Sreedhar Natarajan, C. Huang, Chuan-Yu Wu, Min-Jer Wang, C. J. Wang, P. Chen, R. Hsieh:
A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS. ISSCC 2008: 270-271 - 2007
- [c6]Nicky Lu, C. K. Wang, Philip Wong, Sreedhar Natarajan:
E1 Ultimate Limits of Integrated Electronics. ISSCC 2007: 146-147 - 2006
- [j6]Jan Van der Spiegel, Ram K. Krishnamurthy, Sreedhar Natarajan, Chih-Kong Ken Yang:
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 41(1): 3-6 (2006) - 2005
- [j5]Georgios K. Konstadinidis, Anantha P. Chandrakasan, Sreedhar Natarajan, Thucydides Xanthopoulos:
Introduction to the Special Issue on the ISSCC2004. IEEE J. Solid State Circuits 40(1): 3-6 (2005) - [j4]Albert Z. H. Wang, Sreedhar Natarajan, Jafar Savoj:
Introduction to the Special Issue on the IEEE 2004 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 40(9): 1775-1777 (2005) - [j3]Vijay Reddy, Anand T. Krishnan, Andrew Marshall, John Rodriguez, Sreedhar Natarajan, Tim Rost, Srikanth Krishnan:
Impact of negative bias temperature instability on digital circuit reliability. Microelectron. Reliab. 45(1): 31-38 (2005) - 2004
- [j2]Hugh P. McAdams, Randy Acklin, Terry Blake, Xiao-Hong Du, Jarrod Eliason, John Y. Fong, William F. Kraus, David Liu, Sudhir Madan, Ted Moise, Sreedhar Natarajan, Ning Qian, Yunchen Qiu, Keith Remack, J. Rodriguez, John Roscher, Anand Seshadri, Scott R. Summerfelt:
A 64-Mb embedded FRAM utilizing a 130-nm 5LM Cu/FSG logic process. IEEE J. Solid State Circuits 39(4): 667-677 (2004) - [j1]Edoardo Charbon, Albert Z. H. Wang, Sreedhar Natarajan:
Introduction to the Special Issue on the IEEE 2003 Custom Integrated Circuits Conference. IEEE J. Solid State Circuits 39(9): 1391-1393 (2004) - [c5]Ingvar Carlson, Stefan Anderson, Sreedhar Natarajan, Atila Alvandpour:
A high density, low leakage, 5T SRAM for embedded caches. ESSCIRC 2004: 215-218 - [c4]Sergey Romanovsky, Arun Achyuthan, Sreedhar Natarajan, Wing Leung:
Leakage Reduction techniques in a 0.13um SRAM Cell. VLSI Design 2004: 215-221 - 2002
- [c3]Andrew Marshall, Sreedhar Natarajan:
PD-SOI and FD-SOI: a comparison of circuit performance. ICECS 2002: 25-28 - [c2]Sreedhar Natarajan, Andrew Marshall:
SOI SRAM design advances & considerations. ICECS 2002: 835-838 - [c1]Sreedhar Natarajan, Andrew Marshall:
Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI. ASP-DAC/VLSI Design 2002: 297-298
Coauthor Index
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