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2020 – today
- 2024
[j48]Jin-O. Seo
, Mingoo Seok, SeongHwan Cho:
A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit. IEEE J. Solid State Circuits 59(5): 1603-1611 (2024)- [j47]Yongjo Kim, Taekwang Jang, SeongHwan Cho:
A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor. IEEE J. Solid State Circuits 59(10): 3253-3262 (2024) - [j46]Hangil Choi, SeongHwan Cho:
A 7.5-GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120× Multiplying Factor and 92.3-fs RMS Jitter Including Reference Spur. IEEE J. Solid State Circuits 59(12): 3928-3937 (2024) - [j45]Pangi Park, Junghyup Lee, SeongHwan Cho:
A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4-ppm/ ° C From -20 °C to 125 °C. IEEE J. Solid State Circuits 59(12): 4057-4067 (2024) - [c48]Pangi Park, Junghyup Lee, SeongHwan Cho:
3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C from -20°C to 125°C. ISSCC 2024: 54-56 - [c47]Hangil Choi, SeongHwan Cho:
19.1 A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference Spur. ISSCC 2024: 348-350 - 2023
- [j44]Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho:
A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM. IEEE J. Solid State Circuits 58(1): 270-278 (2023) - [j43]Nahmil Koo, Hyojun Kim, SeongHwan Cho:
A 43.3-μW Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 Vpp and T-CMRR of 105 dB in 180-nm CMOS. IEEE J. Solid State Circuits 58(2): 508-519 (2023) - [j42]Sujin Park, Hyungil Chae, SeongHwan Cho:
A 3.68 aFrms Resolution Continuous-Time Bandpass Δ Σ Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 μm CMOS. IEEE J. Solid State Circuits 58(6): 1657-1666 (2023) - [j41]SeongHwan Cho, Joo-Young Kim, Minoru Fujishima, Jun Zhou:
Introduction to the Special Section on the 2022 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 58(10): 2671-2674 (2023) - [j40]Pangi Park, Woobean Lee, SeongHwan Cho:
An Adaptive Filter Based Motion Artifact Cancellation Technique Using Multi-Wavelength PPG for Accurate HR Estimation. IEEE Trans. Biomed. Circuits Syst. 17(5): 1074-1083 (2023) - [j39]Myungjun Kim, SeongHwan Cho:
An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 642-654 (2023) - [c46]Yongjo Kim, Taekwang Jang, SeongHwan Cho:
A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter Monitor. A-SSCC 2023: 1-3 - [c45]Woojun Choi, Yiyang Chen, Donghwan Kim, Sean Weaver, Tilman Schlotter, Can Livanelioglu, Jiawei Liao, Rosario M. Incandela, Parham Davami, Gabriele Atzeni, Sina Arjmandpour, SeongHwan Cho, Taekwang Jang:
A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j38]Siwon Huh, SeongHwan Cho, Jinho Choi, Seungwon Shin, Hojoon Lee:
A Comprehensive Analysis of Today's Malware and Its Distribution Network: Common Adversary Strategies and Implications. IEEE Access 10: 49566-49584 (2022) - [j37]Han-Gil Choi, Sang Heung Lee, SeongHwan Cho:
Technique for fast triangular chirp modulation in FMCW PLL. IEICE Electron. Express 19(14): 20220214 (2022) - [j36]Sujin Park, Ji-Hwan Seol, Li Xu, SeongHwan Cho, Dennis Sylvester, David T. Blaauw:
A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance. IEEE J. Solid State Circuits 57(4): 1175-1186 (2022) - [c44]Woobean Lee, Pangi Park, SeongHwan Cho:
Reduction of Motion Artifact in PPG signal with CDS-LMS Filter. APCCAS 2022: 60-64 - [c43]Yeonwook Jung, Seongseop Lee, Hyojun Kim, SeongHwan Cho:
A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter. ISSCC 2022: 1-3 - [c42]Jin-O. Seo, Mingoo Seok, SeongHwan Cho:
ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory. ISSCC 2022: 258-260 - [c41]Seungyeob Baik, Taeryoung Seol, Sehwan Lee, Geunha Kim, SeongHwan Cho, Arup K. George, Junghyup Lee:
A 2.54μJ∙ppm2-FOMS Supply- and Temperature-Independent Time-Locked ΔΣ Capacitance-to-Digital Converter in 0.18-μm CMOS. VLSI Technology and Circuits 2022: 114-115 - 2021
- [j35]Nahmil Koo, SeongHwan Cho:
A 24.8-μW Biopotential Amplifier Tolerant to 15-VPP Common-Mode Interference for Two-Electrode ECG Recording in 180-nm CMOS. IEEE J. Solid State Circuits 56(2): 591-600 (2021) - [j34]Myungjun Kim, SeongHwan Cho:
A Single BJT Bandgap Reference With Frequency Compensation Exploiting Mirror Pole. IEEE J. Solid State Circuits 56(10): 2902-2912 (2021) - [c40]Dongin Kim, SeongHwan Cho:
An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS. A-SSCC 2021: 1-3 - [c39]Donghyeok Cho, Nahmil Koo, Taekwang Jang, SeongHwan Cho:
An Offset Charge Compensating Biphasic Neuro - stimulation for Faradaic DC-Current Reduction. ISCAS 2021: 1-5 - [c38]Nahmil Koo, Hyojun Kim, SeongHwan Cho:
28.6 A 22.6µ W Biopotential Amplifier with Adaptive Common-Mode Interference Cancelation Achieving Total-CMRR of 104dB and CMI Tolerance of 15Vpp in 0.18µm CMOS. ISSCC 2021: 396-398 - [c37]Hyunsik Jeong, SeongHwan Cho:
An Energy-Efficient Voltage Step-up System for 3D NAND Flash using Charge-Compensating Regulator. VLSI Circuits 2021: 1-2 - [c36]Sujin Park, Hyungil Chae, SeongHwan Cho:
A 3.68aFrms Resolution 183dB FoMs 4th-order Continuous-Time Bandpass ∆Σ Capacitance-to-Digital Converter in 0.18µm CMOS. VLSI Circuits 2021: 1-2 - 2020
- [c35]Sujin Park, Geon-Hwi Lee, Seungmin Oh, SeongHwan Cho:
A Capacitance-to-Digital Converter with Differential Bondwire Accelerometer, On-chip Air Pressure and Humidity Sensor in 0.18 μm CMOS. ASP-DAC 2020: 3-4
2010 – 2019
- 2019
- [j33]Sujin Park, Geon-Hwi Lee, SeongHwan Cho:
A 2.92-µW Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-µm CMOS. IEEE J. Solid State Circuits 54(10): 2845-2856 (2019) - [j32]Dongin Kim, SeongHwan Cho:
A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise. IEEE Trans. Circuits Syst. II Express Briefs 66-II(2): 232-236 (2019) - [j31]Dong-Kyun Jung, Jin-O. Seo, SeongHwan Cho:
An On-Chip Thermal Monitoring System With a Temperature Sensing Area of 52 µm2 in 180-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1638-1642 (2019) - [j30]Dongin Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho:
A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits. IEEE Trans. Circuits Syst. II Express Briefs 66-II(10): 1643-1647 (2019) - [c34]Eunseok Lee, Sujin Park, SeongHwan Cho:
An On-Off Keying LC Oscillator-Based Acoustic Transmitter with Fast Turn-On and Turn-Off Time. APCCAS 2019: 369-372 - [c33]Eunseok Lee, Sujin Park, Nahmil Koo, SeongHwan Cho:
A Low-Power Piezoelectric Speaker Driver Using LC Oscillator for Acoustic Communication. ISOCC 2019: 85-86 - [c32]Nahmil Koo, SeongHwan Cho:
A 27.8μW Biopotential Amplifier Tolerant to 30Vpp Common-Mode Interference for Two-Electrode ECG Recording in 0.18μm CMOS. ISSCC 2019: 366-368 - 2018
- [j29]JinSeok Lee, Geon-Hwi Lee, Hyojun Kim, SeongHwan Cho:
An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback. IEEE J. Solid State Circuits 53(8): 2252-2262 (2018) - [j28]JinSeok Lee, Do-Hun Jang, Sujin Park, SeongHwan Cho:
A Low-Power Photoplethysmogram-Based Heart Rate Sensor Using Heartbeat Locked Loop. IEEE Trans. Biomed. Circuits Syst. 12(6): 1220-1229 (2018) - [j27]Youngwoo Jo, Hyojun Kim, SeongHwan Cho:
A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 2170-2174 (2018) - [c31]Dongin Kim, SeongHwan Cho:
A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop. ASP-DAC 2018: 283-284 - [c30]Do-Hun Jang, SeongHwan Cho:
A 43.4μW photoplethysmogram-based heart-rate sensor using heart-beat-locked loop. ISSCC 2018: 474-476 - [c29]Sujin Park, Geon-Hwi Lee, SeongHwan Cho:
A 2.69UW Dual Quantization-Based Capacitance-to-Digital Converter for Pressure, Humidity, and Acceleration Sensing in 0.18UM CMOS. VLSI Circuits 2018: 163-164 - 2017
- [j26]Hyunik Kim, Yongjo Kim, Taeik Kim, Hyung Jong Ko, SeongHwan Cho:
A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique. IEEE J. Solid State Circuits 52(11): 2934-2946 (2017) - [j25]Yongjo Kim, Keunsoo Song, Dongkyun Kim, SeongHwan Cho:
A 2.3-mW 0.01-mm2 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 64-II(4): 397-401 (2017) - [c28]JinSeok Lee, Hyojun Kim, SeongHwan Cho:
A 255nW ultra-high input impedance analog front-end for non-contact ECG monitoring. CICC 2017: 1-4 - [c27]SeongHwan Cho, Denis Daly:
EE1: Student Research Preview. ISSCC 2017: 518-520 - 2016
- [j24]Michael P. Flynn, Pietro Andreani, SeongHwan Cho:
New Associate Editors. IEEE J. Solid State Circuits 51(5): 1063 (2016) - [j23]Young-Hwa Kim, SeongHwan Cho:
A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source. IEEE Trans. Very Large Scale Integr. Syst. 24(7): 2570-2579 (2016) - [c26]Hyunik Kim, Yongjo Kim, Taeik Kim, Hojin Park, SeongHwan Cho:
19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS. ISSCC 2016: 328-329 - [c25]Jan Van der Spiegel, SeongHwan Cho, Denis Daly:
ES1: Student research preview. ISSCC 2016: 514-516 - 2015
- [j22]Woojae Lee, SeongHwan Cho:
Integrated All Electrical Pulse Wave Velocity and Respiration Sensors Using Bio-Impedance. IEEE J. Solid State Circuits 50(3): 776-785 (2015) - [j21]Wonsik Yu, KwangSeok Kim, SeongHwan Cho:
A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter. IEEE J. Solid State Circuits 50(5): 1251-1262 (2015) - [j20]Jungho Kim, Young-Hwa Kim, KwangSeok Kim, Wonsik Yu, SeongHwan Cho:
A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC. IEEE Trans. Circuits Syst. II Express Briefs 62-II(7): 631-635 (2015) - [c24]Hyojun Kim, Jinwoo Sang, Hyunik Kim, Youngwoo Jo, Taeik Kim, Hojin Park, SeongHwan Cho:
14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. ISSCC 2015: 1-3 - [c23]Junghyup Lee, Pyoungwon Park, SeongHwan Cho, Minkyu Je:
5.10 A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs. ISSCC 2015: 1-3 - 2014
- [j19]KwangSeok Kim, Wonsik Yu, SeongHwan Cho:
A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register. IEEE J. Solid State Circuits 49(4): 1007-1016 (2014) - [j18]Wonsik Yu, KwangSeok Kim, SeongHwan Cho:
A 148fsrms Integrated Noise 4 MHz Bandwidth Second-Order ΔΣ Time-to-Digital Converter With Gated Switched-Ring Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(8): 2281-2289 (2014) - 2013
- [j17]KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho:
A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier. IEEE J. Solid State Circuits 48(4): 1009-1017 (2013) - [j16]Wonsik Yu, Jaewook Kim, KwangSeok Kim, SeongHwan Cho:
A Time-Domain High-Order MASH ΔΣ ADC Using Voltage-Controlled Gated-Ring Oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 856-866 (2013) - [c22]Wonsik Yu, KwangSeok Kim, SeongHwan Cho:
A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator. CICC 2013: 1-4 - [c21]Antonio Liscidini, SeongHwan Cho, Tony Chan Carusone, Tanay Karnik, Mike Keaveney, Brian Otis, Aaron Partridge, Christoph Sandner:
F5: Frequency generation and clock distribution. ISSCC 2013: 508-509 - 2012
- [j15]Jaewon Lee, Woojae Lee, SeongHwan Cho:
A High-Frequency Compensated Crosstalk and ISI Equalizer for Multi-Channel On-Chip Interconnect in 130-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 314-321 (2012) - [j14]Pyoungwon Park, Dongmin Park, SeongHwan Cho:
A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL. IEEE J. Solid State Circuits 47(10): 2433-2443 (2012) - [j13]Junghyup Lee, SeongHwan Cho:
A 1.4-µW 24.9-ppm/°C Current Reference With Process-Insensitive Temperature Compensation in 0.18-µm CMOS. IEEE J. Solid State Circuits 47(10): 2527-2533 (2012) - [j12]Dongmin Park, SeongHwan Cho:
A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 μ m CMOS. IEEE J. Solid State Circuits 47(12): 2989-2998 (2012) - [j11]Jaewon Lee, Woojae Lee, SeongHwan Cho:
A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 124-136 (2012) - [j10]Tae-Kwang Jang, Jaewook Kim, Young-Gyu Yoon, SeongHwan Cho:
A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1368-1372 (2012) - [c20]Ken Chang, SeongHwan Cho:
Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommittee. ISSCC 2012: 322-323 - [c19]Pyoungwon Park, Jaejin Park, Hojin Park, SeongHwan Cho:
An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. ISSCC 2012: 336-337 - [c18]Dongmin Park, SeongHwan Cho:
A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS. ISSCC 2012: 344-346 - [c17]Ichiro Fujimori, SeongHwan Cho, Joshua Friedrich, John T. Stonick:
Optical PCB interconnects, Niche or mainstream? ISSCC 2012: 516 - [c16]KwangSeok Kim, Young-Hwa Kim, Wonsik Yu, SeongHwan Cho:
A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. VLSIC 2012: 192-193 - 2011
- [j9]Joonhee Lee, Sunghyun Park, SeongHwan Cho:
A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 61-70 (2011) - [c15]Young-Hwa Kim, SeongHwan Cho:
A time-domain flash ADC immune to voltage controlled delay line non-linearity. ASICON 2011: 469-471 - [c14]Pyoungwon Park, Dongmin Park, SeongHwan Cho:
A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL. CICC 2011: 1-4 - [c13]Jaewook Kim, Wonsik Yu, Hyun-Kyu Yu, SeongHwan Cho:
A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. ISSCC 2011: 176-178 - 2010
- [j8]Sung-Jin Kim, Min-Chang Cho, SeongHwan Cho:
An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder. IEICE Trans. Electron. 93-C(6): 785-795 (2010) - [j7]Jaewook Kim, Tae-Kwang Jang, Young-Gyu Yoon, SeongHwan Cho:
Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 18-30 (2010) - [c12]Woojae Lee, Min-Chang Cho, SeongHwan Cho:
CMRR enhancement technique for IA using three IAs for bio-medical sensor applications. APCCAS 2010: 248-251 - [c11]Woojae Lee, SeongHwan Cho:
A 2.4-GHz reference doubled fractional-N PLL with dual phase detector in 0.13-μm CMOS. ISCAS 2010: 1328-1331 - [c10]Sung-Pah Lee, SeongHwan Cho:
A background KDCO compensation technique for constant bandwidth in all-digital phase-locked loop. ISCAS 2010: 3401-3404 - [c9]Young-Hwa Kim, Jaewon Lee, SeongHwan Cho:
A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages. ISCAS 2010: 4041-4044
2000 – 2009
- 2009
- [j6]Joonhee Lee, Sungjun Kim, Sehyung Jeon, Woojae Lee, SeongHwan Cho:
A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS. IEICE Trans. Electron. 92-C(4): 589-591 (2009) - [j5]Hoi-Jun Yoo, SeongHwan Cho:
Introduction to the Special Section on the 2008 Asian Solid-State Circuits Conference (A-SSCC'08). IEEE J. Solid State Circuits 44(11): 2871-2872 (2009) - [c8]Sunghyun Park, Changwook Min, SeongHwan Cho:
A 95nW Ring Oscillator-based Temperature Sensor for RFID Tags in 0.13µm CMOS. ISCAS 2009: 1153-1156 - [c7]Min-Chang Cho, Jee-Yeon Kim, SeongHwan Cho:
A Bio-impedance Measurement System for Portable Monitoring of Heart Rate and Pulse Wave Velocity using Small Body Area. ISCAS 2009: 3106-3109 - 2008
- [j4]Young-Gyu Yoon, Jaewook Kim, Tae-Kwang Jang, SeongHwan Cho:
A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(11): 3571-3581 (2008) - [c6]Sung-Jin Kim, Min-Chang Cho, Joonhyun Park, Kisuk Song, Yul Kim, SeongHwan Cho:
An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder. ISCAS 2008: 660-663 - 2007
- [j3]Jaewon Lee, SeongHwan Cho:
A Quadrature Modulation Transmitter Using Two Frequency Synthesizers. IEEE Trans. Circuits Syst. II Express Briefs 54-II(10): 907-911 (2007) - 2006
- [c5]Jaewook Kim, SeongHwan Cho:
A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator. ISCAS 2006 - [c4]Dongmin Park, SeongHwan Cho:
A power-optimized CMOS LC VCO with wide tuning range in 0.5-V supply. ISCAS 2006 - [c3]Jaewon Lee, SeongHwan Cho:
A Low Power Transmitter for Phase-Shift Keying Modulation Schemes. PIMRC 2006: 1-5 - 2005
- [c2]SeongHwan Cho, Kee-Eung Kim:
Variable bandwidth allocation scheme for energy efficient wireless sensor network. ICC 2005: 3314-3318 - [c1]SeongHwan Cho, Sungmin Ock, Sang-Hoon Lee, Joonsuk Lee:
A low power pipelined analog-to-digital converter using series sampling capacitors. ISCAS (6) 2005: 6178-6181 - 2004
- [j2]SeongHwan Cho, Anantha P. Chadrakasan:
A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications. IEEE J. Solid State Circuits 39(5): 731-739 (2004) - 2003
- [j1]Gabriele Manganaro, Sung-Ung Kwak, SeongHwan Cho, Anurag Pulincherry:
A behavioral modeling approach to the design of a low jitter clock source. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 804-814 (2003) - 2002
- [b1]SeongHwan Cho:
Energy efficient radio frequency communication systems for wireless microsensors. Massachusetts Institute of Technology, Cambridge, MA, USA, 2002
Coauthor Index
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