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2000 – 2009
- 2005
[c7]David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose:
The Stratix II logic and routing architecture. FPGA 2005: 14-20- 2004
- [c6]Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini:
Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144 - 2003
- [c5]David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose:
The StratixTM routing and logic architecture. FPGA 2003: 12-20 - 2002
- [c4]Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev:
Interconnect enhancements for a high-speed PLD architecture. FPGA 2002: 3-10
1990 – 1999
- 1999
- [c3]Richard Cliff, Srinivas Reddy, Cameron McClintock, David Jefferslon, Christopher Lane, Ketan Zaveri, Manuel Mejia, Andy Lee, Ninh Ngo, Risa Altaf, Bruce Pedersen, Frank Heile, Jay Schleicher, John Turner:
A next generation architecture optimized for high density system level integration. CICC 1999: 175-178 - 1998
- [c2]Chiakang Sung, Richard Cliff, Joseph Huang, Bonnie Wang, Khai Nguyen, Xtaobao Wang, Kerry Veenstra, Bruce Pedersen, John Turner:
A silicon efficient FLEX 6000 programmable logic architecture. CICC 1998: 273-276 - [c1]Kerry Veenstra, Bruce Pedersen, Jay Schleicher, Chiakang Sung:
Optimizations for a Highly Cost-Efficient Programmable Logic Architecture. FPGA 1998: 20-24
Coauthor Index
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