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ORCIDToshio Kondo
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2010 – 2019
- 2018
[j10]BaoKang Wang
, Yuki Fukazawa, Toshio Kondo, Takahiro Sasaki:
Tile/line access cache memory based on a multi-level Z-order tiling data layout. Concurr. Comput. Pract. Exp. 30(9) (2018)- 2016
- [c20]BaoKang Wang, Yuki Fukazawa, Toshio Kondo, Takahiro Sasaki:
A cache memory with unit tile and line accessibility. ICIS 2016: 1-6 - [c19]Kouki Kayamuro, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo:
A Rapid Verification Framework for Developing Multi-core Processor. CANDAR 2016: 388-394 - [c18]Yuki Fukazawa, Keita Watanabe, Yuki Minoura, Toshio Kondo, Takahiro Sasaki:
SIMD-based datapath with efficient operation structure for motion estimation. ICASSP 2016: 1031-1035 - [c17]BaoKang Wang, Yuki Fukazawa, Toshio Kondo, Takahiro Sasaki:
A cache memory with unit tile and line accessibility. HPCS 2016: 866-874 - 2015
- [c16]Hiroaki Kawashima, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo:
Register Port Prediction for a Banked Register File. CANDAR 2015: 551-555 - [c15]Seiji Miyoshi, Takahiro Sasaki, Yuki Fukazawa, Toshio Kondo:
An Architectural Framework of Snoopy Interconnection for Heterogeneous Cache Systems. CANDAR 2015: 561-565 - 2014
- [c14]Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo:
Co-simulation framework for streamlining microprocessor development on standard ASIC design flow. ASP-DAC 2014: 400-405 - [c13]Takaki Okamoto, Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo:
Detail Design and Evaluation of Fab Cache. CANDAR 2014: 591-595 - 2013
- [j9]Takahiro Sasaki, Tomoyuki Nakabayashi, Kazumasa Nomura, Kazuhiko Ohno, Toshio Kondo:
Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor. IET Comput. Digit. Tech. 7(1): 41-47 (2013) - [j8]Tomoyuki Nakabayashi, Takahiro Sasaki, Hitoshi Nakamura, Kazuhiko Ohno, Toshio Kondo:
Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip. Int. J. Netw. Comput. 3(2): 192-204 (2013) - [c12]Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo:
Dynamic BTB Resizing for Variable Stages Superscalar Architecture. CANDAR 2013: 352-358 - [c11]Takaki Okamoto, Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo:
FabCache: Cache Design Automation for Heterogeneous Multi-core Processors. CANDAR 2013: 602-606 - 2012
- [j7]Tomoyuki Nakabayashi, Takahiro Sasaki, I. K. Ohno, Toshio Kondo:
Design and evaluation of variable stages pipeline processor with low-energy techniques. IET Comput. Digit. Tech. 6(1): 43-49 (2012) - [c10]Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture. ICNC 2012: 293-297 - 2011
- [c9]Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Design and evaluation of variable stages pipeline processor chip. ASP-DAC 2011: 95-96 - [c8]Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Low power semi-static TSPC D-FFs using split-output latch. ISOCC 2011: 167-170 - 2010
- [c7]Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Design and Evaluation of Variable Stages Pipeline Processor Chip. ISIA 2010: 220-226 - [c6]Nobuyuki Matsubara, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo:
Evaluation of Variable Level Cache. ISIA 2010: 227-233
2000 – 2009
- 2008
- [j6]Takahiro Sasaki, Yuji Ichikawa, Tetsuo Hironaka, Toshiaki Kitamura, Toshio Kondo:
Evaluation of low-energy and high-performance processor using variable stages pipeline technique. IET Comput. Digit. Tech. 2(3): 230-238 (2008) - 2001
- [c5]Wujian Zhang, Runde Zhou, Toshio Kondo:
Low-power motion-estimation architecture based on a novel early-jump-out technique. ISCAS (5) 2001: 187-190
1990 – 1999
- 1999
- [j5]Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Hiroe Iwasaki, Katsuyuki Ochiai, Jiro Naganuma, Makoto Endo, Yutaka Tashiro, Hiroshi Watanabe, Naoki Kobayashi, Tsuneo Okubo, Ryota Kasai:
SuperENC: MPEG-2 video encoder chip. IEEE Micro 19(4): 56-65 (1999) - [j4]Tsuneo Okubo, Mitsuo Ikeda, Yutaka Tashiro, Toshio Kondo, Ryota Kasai, Hiroshi Kotera, Tetsuma Sakurai:
Concurrent and collaborative methodologies in short TAT LSI design and manufacturing. Syst. Comput. Jpn. 30(7): 79-91 (1999) - [c4]Mitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura:
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture. DATE 1999: 44- - 1996
- [j3]Kazuhito Suguri, Toshihiro Minami, Hiroaki Matsuda, Ritsu Kusaba, Toshio Kondo, Ryota Kasai, Takumi Watanabe, Hidenuri Sato, Nobutarou Shibata, Yutaka Tashiro, Takaaki Izuoka, Atsushi Shimizu, Hiroshi Kotera:
A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding. IEEE J. Solid State Circuits 31(11): 1733-1741 (1996) - [j2]Toshio Kondo, Kazuhito Suguri, Mitsuo Ikeda, Tetsuya Abe, Hiroaki Matsuda, Tsuneo Okubo, Kenji Ogura, Yutaka Tashiro, Naoki Ono, Toshihiro Minami, Ritsu Kusaba, Takeshi Ikenaga, Nobutaro Shibata, Ryota Kasai, Koji Otsu, Fumiaki Nakagawa, Yasuhiko Sato:
Two-chip MPEG-2 video encoder. IEEE Micro 16(2): 51-58 (1996)
1980 – 1989
- 1989
- [j1]Toshio Kondo, Yoshi Sugiyama, Takayoshi Nakashima:
Two-Dimensional Array Processor AAP2 and Its Programming Language. Syst. Comput. Jpn. 20(12): 14-22 (1989) - 1986
- [c3]Kenichi Nishide, Moritomo Hanawa, Toshio Kondo:
Automatic position findings of vehicle by means of laser. ICRA 1986: 1343-1348 - [c2]Toshio Kondo, Toshio Tsuchiya, Yoshihiro Kitamura, Yoshi Sugiyama, Takashi Kimura, Takayoshi Nakashima:
Pseudo MIMD Array Processor - AAP2. ISCA 1986: 330-337 - 1985
- [c1]Toshio Kondo, Tayoshi Nakashima, Toshio Tsuchiya, Yoshi Sugiyama, Tsuneta Sudo:
A large scale cellular array processor: AAP-1. ACM Conference on Computer Science 1985: 100-111
Coauthor Index
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