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Pseudo MIMD array processor—AAP2

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T. KimuraAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 14, Issue 2

Pages 330 - 337

https://doi.org/10.1145/17356.17395

Published: 01 May 1986 Publication History

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Abstract

A highly integrated array processor (AAP2)-LSI has been developed. After the past 3 years study on the adaptive array processor 1 (AAP1), a challenging improvements on the SIMD's restraints are achieved by using the AAP2-LSI. The AAP2 array system makes it possible to carry out wideband modifiable operation (pseudo MIMD). Furthermore, each PE is capable of supporting a large amount of memory. The AAP2 potential for massively, parallel and pipelined processing is discussed in the field of image processing and CAD applications.

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Cited By

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Lin MHsieh SChen C(2023)Reconfigurable Hardware Accelerator of Morphological Image Processor2023 IEEE 3rd International Conference on Electronic Communications, Internet of Things and Big Data (ICEIB)10.1109/ICEIB57887.2023.10170636(348-351)Online publication date: 14-Apr-2023
https://doi.org/10.1109/ICEIB57887.2023.10170636
Kondo TSugiyama YNakashima T(2007)Two‐Dimensional Array Processor AAP2 and Its Programming LanguageSystems and Computers in Japan10.1002/scj.469020120220:12(14-22)Online publication date: 6-Sep-2007
https://doi.org/10.1002/scj.4690201202
Ikenaga TOgura T(2005)CAM2: A highly-parallel 2D cellular automata architecture for real-time and palm-top pixel-level image processingEuro-Par'96 Parallel Processing10.1007/BFb0024703(203-212)Online publication date: 10-Jun-2005
https://doi.org/10.1007/BFb0024703
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Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 14, Issue 2

Special Issue: Proceedings of the 13th annual international symposium on Computer architecture (ISCA '86)

May 1986

429 pages

ISSN:0163-5964

DOI:10.1145/17356

Editor:
Hideo Aiso

Issue’s Table of Contents

ISCA '86: Proceedings of the 13th annual international symposium on Computer architecture
June 1986
454 pages
ISBN:081860719X
Chairman:
Hideo Aiso

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 May 1986

Published in SIGARCH Volume 14, Issue 2

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Lin MHsieh SChen C(2023)Reconfigurable Hardware Accelerator of Morphological Image Processor2023 IEEE 3rd International Conference on Electronic Communications, Internet of Things and Big Data (ICEIB)10.1109/ICEIB57887.2023.10170636(348-351)Online publication date: 14-Apr-2023
https://doi.org/10.1109/ICEIB57887.2023.10170636
Kondo TSugiyama YNakashima T(2007)Two‐Dimensional Array Processor AAP2 and Its Programming LanguageSystems and Computers in Japan10.1002/scj.469020120220:12(14-22)Online publication date: 6-Sep-2007
https://doi.org/10.1002/scj.4690201202
Ikenaga TOgura T(2005)CAM2: A highly-parallel 2D cellular automata architecture for real-time and palm-top pixel-level image processingEuro-Par'96 Parallel Processing10.1007/BFb0024703(203-212)Online publication date: 10-Jun-2005
https://doi.org/10.1007/BFb0024703
Ikenaga TOgura T(2000)Real-time morphology processing using highly parallel 2-D cellular automata CAM2IEEE Transactions on Image Processing10.1109/83.8879709:12(2018-2026)Online publication date: 1-Dec-2000
https://dl.acm.org/doi/10.1109/83.887970
Ikenaga TOgura T(1998)CAM2IEEE Transactions on Computers10.1109/12.70937947:7(788-801)Online publication date: 1-Jul-1998
https://dl.acm.org/doi/10.1109/12.709379
Yagi NFukui KEnami KYajima RSasaki NHoshino KHarukawa KKogure M(1991)A Programmable Real-Time Video Signal-Processing SystemSMPTE Journal10.5594/J02405100:11(860-868)Online publication date: Nov-1991
https://doi.org/10.5594/J02405
Deb ANam Ling (1991)A massively parallel and versatile architecture for computer vision[1991] Proceedings. First Great Lakes Symposium on VLSI10.1109/GLSV.1991.143945(74-79)Online publication date: 1991
https://doi.org/10.1109/GLSV.1991.143945
Fukushima T(1990)A survey of image processing LSIs in Japan[1990] Proceedings. 10th International Conference on Pattern Recognition10.1109/ICPR.1990.119389(394-401)Online publication date: 1990
https://doi.org/10.1109/ICPR.1990.119389
Ikenaga TOgura T(1998)CAM2IEEE Transactions on Computers10.1109/12.70937947:7(788-801)Online publication date: 1-Jul-1998
https://dl.acm.org/doi/10.1109/12.709379
Rockoff TSnyder LLeiserson C(1994)SIMD instruction cacheProceedings of the sixth annual ACM symposium on Parallel algorithms and architectures10.1145/181014.181034(67-75)Online publication date: 1-Aug-1994
https://dl.acm.org/doi/10.1145/181014.181034

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