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2020 – today
- 2024
[j32]Dongyoung Kim
, Young Woong Ko, Dong-Kyu Kim, Jeong-Gun Lee:
Analysis of Transformer's Attention Behavior in Sleep Stage Classification and Limiting It to Improve Performance. IEEE Access 12: 95914-95925 (2024)- [j31]Taki Hasan Rafi, Ratul Mahjabin, Emon Ghosh, Young Woong Ko, Jeong-Gun Lee:
Domain generalization for semantic segmentation: a survey. Artif. Intell. Rev. 57(9): 247 (2024) - [c31]Dongyoung Kim, Dong-Kyu Kim, Jeong-Gun Lee:
Improved Generalization from Limiting Attention in a Transformer for Sleep Stage Classification. ICEIC 2024: 1-4 - [c30]Jeong-Gun Lee, Dongyoung Kim:
Error-Resilient Inference with an Error-Aware Activation Function in a Deep Neural Network. ICEIC 2024: 1-4 - 2023
- [j30]Yunhee Woo, Dongyoung Kim, Jaemin Jeong, Won-Sook Lee, Jeong-Gun Lee, Dong-Kyu Kim:
Automatic Sleep Stage Classification Using Deep Learning Algorithm for Multi-Institutional Database. IEEE Access 11: 46297-46307 (2023) - 2022
- [c29]Dongyoung Kim, Younghoon Na, Yunhee Woo, Dong-Kyu Kim, Jeong-Gun Lee:
Entropy-Based Model Generalization for Sleep Stage Classification. ICTC 2022: 2213-2216 - 2021
- [j29]Jaemin Jeong, Ji-Ho Cho, Jeong-Gun Lee:
Filter combination learning for CNN model compression. ICT Express 7(1): 5-9 (2021) - [c28]Yunhee Woo, Dongyoung Kim, Jaemin Jeong, Dong-Kyu Kim, Jeong-Gun Lee:
Image-based Sleep Stage Classification Model for Multi-Institutional Dataset. ICTC 2021: 1061-1064 - [c27]Dongyoung Kim, Yunhee Woo, Jaemin Jeong, Dong-Kyu Kim, Jeong-Gun Lee:
Sleep Stage Classification for Inter-institutional Transfer Learning. ICTC 2021: 1797-1800 - 2020
- [j28]Nguyen Van Toan, Jeong-Gun Lee:
FPGA-Based Multi-Level Approximate Multipliers for High-Performance Error-Resilient Applications. IEEE Access 8: 25481-25497 (2020) - [j27]Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee:
In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA. J. Circuits Syst. Comput. 29(6): 2050098:1-2050098:22 (2020) - [c26]Jae Min Jeong, Dongyoung Kim, Yunhee Woo, Jeong-Gun Lee:
Filter Combination Learning for Convolutional Neural Network. ICTC 2020: 1171-1176 - [c25]Yunhee Woo, Dongyoung Kim, Jaemin Jeong, Young Woong Ko, Jeong-Gun Lee:
Zero-Keep Filter Pruning for Energy Efficient Deep Neural Network. ICTC 2020: 1288-1292
2010 – 2019
- 2019
- [j26]Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee:
A high-resolution and glitch-free all-digital variable length ring oscillator design on an FPGA. Comput. Electr. Eng. 74: 149-163 (2019) - [j25]Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
A GALS design based on multi-frequency clocking for digital switching noise reduction. Integr. 69: 210-224 (2019) - [j24]Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee:
A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation. J. Circuits Syst. Comput. 28(1): 1950018:1-1950018:23 (2019) - [j23]Ayinebyona Eliab, Yonghwi Kim, Joosang Lee, Jeong-Gun Lee, Jungmin So:
G-DCF: Improving System Spectral Efficiency through Concurrent Transmissions in Wireless LANs. Wirel. Commun. Mob. Comput. 2019: 5427573:1-5427573:16 (2019) - [c24]Nguyen Van Toan, Jeong-Gun Lee:
Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on FPGAs. SoCC 2019: 336-341 - 2018
- [j22]Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
Measurements of metastability in MUTEX on an FPGA. IEICE Electron. Express 15(1): 20171165 (2018) - [j21]Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise Suppressions. IEEE Trans. Very Large Scale Integr. Syst. 26(9): 1685-1698 (2018) - [c23]Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
A GALS Design with Opposite-Phase Local Clock Assignment for Power Supply Noise Reduction. APCCAS 2018: 287-290 - 2017
- [j20]Thi Yen Phuong, Deok-Young Lee, Jeong-Gun Lee:
A performance, power, and energy analysis of ultrasound B-mode imaging on a GPU with VFS. Concurr. Comput. Pract. Exp. 29(5) (2017) - [j19]Ziho Shin, Myeong-Hoon Oh, Jeong-Gun Lee, Hag-Young Kim, Young Woo Kim:
Design of a clockless MSP430 core using mixed asynchronous design flow. IEICE Electron. Express 14(8): 20170162 (2017) - [c22]Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee:
Exploring the current consumption of an Intel Edison module for IoT applications. I2MTC 2017: 1-6 - [c21]Nguyen Van Toan, Dam Minh Tung, Jeong-Gun Lee:
Energy-efficient and high performance 2-phase asynchronous micropipelines. MWSCAS 2017: 1188-1191 - 2016
- [j18]Jeong-Gun Lee, Sanghoon Kwak:
A performance-aware yield analysis and optimization of manycore architectures. Comput. Electr. Eng. 54: 40-52 (2016) - 2015
- [j17]Thi Yen Phuong, Jeong-Gun Lee:
Design space exploration of SW beamformer on GPU. Concurr. Comput. Pract. Exp. 27(7): 1718-1733 (2015) - 2014
- [j16]Jeong-Gun Lee, Myeong-Hoon Oh:
Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC. IEICE Trans. Electron. 97-C(4): 253-263 (2014) - [j15]Young Woong Ko, Min-Ja Kim, Jeong-Gun Lee, Chuck Yoo:
Deduplication TAR Scheme Using User-Level File System. IEICE Trans. Inf. Syst. 97-D(8): 2174-2177 (2014) - [j14]Jeong-Gun Lee:
A Low EMI Circuit Design with Asynchronous Multi-Frequency Clocking. IEICE Trans. Electron. 97-C(12): 1158-1161 (2014) - [c20]Thi Yen Phuong, Jeong-Gun Lee:
Software based ultrasound B-mode/beamforming optimization on GPU and its performance prediction. HiPC 2014: 1-10 - 2012
- [j13]Mi Jeong Song, Jeong-Gun Lee, Jong-Myeon Park, Sungjoo Lee:
Triggering navigators for innovative system design: The case of lab-on-a-chip technology. Expert Syst. Appl. 39(16): 12451-12459 (2012) - [c19]Seung-Joon Lee, Deok-Young Lee, Young Woong Ko, Jeong-Gun Lee:
Asynchronous Circuit Design on an FPGA: MIPS Processor Case Study. ICHIT (2) 2012: 480-487 - [c18]Byung Ki Kim, Jeong-Gun Lee, Seon Woo Lee, Young Woong Ko:
Low Latency Scheduling on Multi BOOST Environment. ICHIT (2) 2012: 720-724 - 2011
- [j12]Jeong-Gun Lee, Deok-Young Lee, Myeong-Hoon Oh, Young Woong Ko:
472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device. IEICE Electron. Express 8(9): 676-683 (2011) - [c17]Ho Min Jung, Won Vien Park, Wan Yeon Lee, Jeong-Gun Lee, Young Woong Ko:
Data Deduplication System for Supporting Multi-mode. ACIIDS (1) 2011: 78-87 - [c16]Jeong-Gun Lee, Kyung Woo Hur, Young Woong Ko:
Minimizing Scheduling Delay for Multimedia in Xen Hypervisor. ACN 2011: 96-108 - [c15]Ho Min Jung, Sung Woon Kang, Jin Kim, Wan Yeon Lee, Jeong-Gun Lee, Young Woong Ko:
Energy Efficient File Transfer Mechanism Using Deduplication Scheme. ICHIT (1) 2011: 421-428 - [c14]Byung Ki Kim, Jae Hyeok Jang, Kyung Woo Hur, Jeong-Gun Lee, Young Woong Ko:
Monitoring and Feedback Tools for Realtime Workloads for Xen Virtual Machine. ICITCS 2011: 151-161 - [c13]Eun-Gu Jung, Daewan Han, Jeong-Gun Lee:
Low area and high speed SHA-1 implementation. ISOCC 2011: 365-367 - 2010
- [j11]Jeong-Gun Lee, Wook Shin, Suk-Jin Kim, Eun-Gu Jung:
A Performance/Energy Analysis and Optimization of Multi-Core Architectures with Voltage Scaling Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(6): 1215-1225 (2010)
2000 – 2009
- 2009
- [j10]Min Zeng, Jeong-Gun Lee, Goang-Seog Choi, Jeong-A Lee:
Intelligent sensor node based a low power ECG monitoring system. IEICE Electron. Express 6(9): 560-565 (2009) - [j9]Sanghoon Kwak, Jeong-Gun Lee, Eun-Gu Jung, Dongsoo Har, Milos D. Ercegovac, Jeong-A Lee:
Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming. J. Circuits Syst. Comput. 18(4): 787-800 (2009) - [c12]Jeong-Gun Lee, Eun-Gu Jung, Wook Shin:
An Asymptotic Performance/Energy Analysis and Optimization of Multi-core Architectures. ICDCN 2009: 85-90 - 2008
- [c11]Jeong-Gun Lee, Eun-Gu Jung:
Embedding High-Performance Synchronous Routers to Asynchronous Network on Chip. CDES 2008: 124-128 - 2007
- [j8]Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har:
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions. J. VLSI Signal Process. 46(2-3): 133-151 (2007) - [c10]Jeong-Gun Lee, Jeong-A Lee, Byeong-Seok Lee, Milos D. Ercegovac:
A Design Method for Heterogeneous Adders. ICESS 2007: 121-132 - [c9]Daniel Greenfield, Arnab Banerjee, Jeong-Gun Lee, Simon W. Moore:
Implications of Rent's Rule for NoC Design and Its Fault-Tolerance. NOCS 2007: 283-294 - 2005
- [j7]Wook Shin, Jeong-Gun Lee, Hong Kook Kim, Kouichi Sakurai:
Procedural Constraints in the Extended RBAC and the Coloured Petri Net Modeling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(1): 327-330 (2005) - [j6]Jeong-Gun Lee, Suk-Jin Kim, Jeong-A Lee, Kiseon Kim:
A Low Latency Asynchronous FIFO Combining a Wave Pipeline with a Handshake Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 1031-1037 (2005) - [j5]Eun-Gu Jung, Jeong-Gun Lee, Kyoung-Sun Jhang, Dong-Soo Har:
Differential Value Encoding for Delay Insensitive Handshake Protocol. IEICE Trans. Inf. Syst. 88-D(7): 1437-1444 (2005) - [j4]Suk-Jin Kim, Jeong-Gun Lee, Kiseon Kim:
Low Latency Four-Flop Synchronizer with the Handshake Interface. IEICE Trans. Inf. Syst. 88-D(7): 1460-1463 (2005) - [j3]Jeong-Gun Lee, Jeong-A Lee, Suk-Jin Kim, Kiseon Kim:
Design of a Mutated Adder and Its Optimization Using ILP Formulation. IEICE Trans. Inf. Syst. 88-D(7): 1506-1508 (2005) - [j2]Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Son Jhang, Jeong-A Lee, Dong-Soo Har:
Asynchronous Multiple-Issue On-Chip Bus with In-Order/Out-of-Order Completion. IEICE Trans. Electron. 88-C(12): 2395-2399 (2005) - [j1]Jeong-Gun Lee, Euiseok Kim, Dong-Ik Lee:
Instruction level redundant number computations for fast data intensive processing in asynchronous processors. J. Syst. Archit. 51(3): 151-164 (2005) - [c8]Eun-Gu Jung, Jeong-Gun Lee, Sanghoon Kwak, Kyoung-Sun Jhang, Jeong-A Lee, Dong-Soo Har:
High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion. ACM Great Lakes Symposium on VLSI 2005: 152-155 - 2004
- [c7]Jeong-Gun Lee, Euiseok Kim, Jeong-A Lee, Eunok Paek:
Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization. Asia-Pacific Computer Systems Architecture Conference 2004: 582-595 - 2003
- [c6]Euiseok Kim, Dong-Ik Lee, Hiroshi Saito, Hiroshi Nakamura, Jeong-Gun Lee, Takashi Nanya:
Performance optimization of synchronous control units for datapaths with variable delay arithmetic units. ASP-DAC 2003: 816-819 - [c5]Euiseok Kim, Hiroshi Saito, Jeong-Gun Lee, Dong-Ik Lee, Hiroshi Nakamura, Takashi Nanya:
Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units. DATE 2003: 10276-10281 - 2001
- [c4]Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee:
Building a Distributed Asynchronous Control Unit through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFG. ARVLSI 2001: 2-15 - [c3]Jeong-Gun Lee, Euiseok Kim, Dong-Ik Lee:
Imprecise data computation for high performance asynchronous processors. ASP-DAC 2001: 261-266 - 2000
- [c2]Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee:
Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis. ASYNC 2000: 104-113 - [c1]Euiseok Kim, Jeong-Gun Lee, Dong-Ik Lee:
Automatic distributed asynchronous control circuit generation from data flow graph for asynchronous high-level synthesis. ISCAS 2000: 49-52
Coauthor Index
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