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2000 – 2009
- 2008
[j3]Sanghyun Park, Aviral Shrivastava
, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie:
Register File Power Reduction Using Bypass Sensitive Compiler. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1155-1159 (2008)- 2007
- [j2]Aviral Shrivastava, Sanghyun Park, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek:
Automatic Design Space Exploration of Register Bypasses in Embedded Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(12): 2102-2115 (2007) - 2006
- [j1]Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau:
Retargetable pipeline hazard detection for partially bypassed processors. IEEE Trans. Very Large Scale Integr. Syst. 14(8): 791-801 (2006) - [c5]Sanghyun Park, Eugene Earlie, Aviral Shrivastava, Alex Nicolau, Nikil D. Dutt, Yunheung Paek:
Automatic generation of operation tables for fast exploration of bypasses in embedded processors. DATE 2006: 1197-1202 - [c4]Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie:
Bypass aware instruction scheduling for register file power reduction. LCTES 2006: 173-181 - 2005
- [c3]Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau:
Aggregating processor free time for energy reduction. CODES+ISSS 2005: 154-159 - [c2]Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Eugene Earlie:
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors. DATE 2005: 1264-1269 - 2004
- [c1]Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau:
Operation tables for scheduling in the presence of incomplete bypassing. CODES+ISSS 2004: 194-199
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