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Automatic generation of operation tables for fast exploration of bypasses in embedded processors

Published: 06 March 2006 Publication History

Abstract

Customizing the bypasses in an embedded processor uncovers valuable trade-offs between the power, performance and the cost of the processor. Meaningful exploration of bypasses requires bypass-sensitive compiler. Operation Tables (OTs) have been proposed to perform bypass-sensitive compilation. However, due to lack of automated methods to generate OTs, OTs are currently manually specified by the designer. Manual specification of OTs is not only an extremely time consuming task, but is also highly error-prone. In this paper, we present AutoOT, an algorithm to automatically generate OTs from a high-level processor description. Our experiments on the Intel XScale processor model running MiBench benchmarks demonstrate that AutoOT greatly reduces the time and effort of specification. Automatic generation of OTs makes it feasible to perform full bypass exploration on the Intel XScale and thus discover interesting alternate bypass configurations in a reasonable time. To further reduce the compile-time overhead of OT generation, we propose another novel algorithm, AutoOTDB. AutoOTDB is able to cut the compile-time overhead of OT generation by half.

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Cited By

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  • (2007)Interactive presentation: Functional and timing validation of partially bypassed processor pipelinesProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266617(1164-1169)Online publication date: 16-Apr-2007
  • (2007)Compiler generation from structural architecture descriptionsProceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1289881.1289886(13-22)Online publication date: 30-Sep-2007
  • (2004)Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCsProceedings of the 41st annual Design Automation Conference10.1145/996566.1142985(626-658)Online publication date: 7-Jun-2004

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Published In

cover image Guide Proceedings
DATE '06: Proceedings of the conference on Design, automation and test in Europe: Proceedings
March 2006
1390 pages
ISBN:3981080106

Sponsors

  • EDAA: European Design Automation Association
  • The EDA Consortium
  • IEEE-CS\DATC: The IEEE Computer Society

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European Design and Automation Association

Leuven, Belgium

Publication History

Published: 06 March 2006

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DATE '06 Paper Acceptance Rate 267 of 834 submissions, 32%;
Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2007)Interactive presentation: Functional and timing validation of partially bypassed processor pipelinesProceedings of the conference on Design, automation and test in Europe10.5555/1266366.1266617(1164-1169)Online publication date: 16-Apr-2007
  • (2007)Compiler generation from structural architecture descriptionsProceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/1289881.1289886(13-22)Online publication date: 30-Sep-2007
  • (2004)Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCsProceedings of the 41st annual Design Automation Conference10.1145/996566.1142985(626-658)Online publication date: 7-Jun-2004

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