Article

Automatic generation of application specific processors

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CASES '03: Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems

Pages 137 - 147

https://doi.org/10.1145/951710.951730

Published: 30 October 2003 Publication History

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Abstract

An application-specific instruction-set processor (ASIP) is ideally suited for embedded applications that have demanding performance, size, and power requirements that cannot be satisfied by a general purpose processor. ASIPs also have time-to-market and programmability advantages when compared to custom ASICs. The AutoTIE system simplifies the creation of ASIPs by automatically enhancing a base processor with application specific instruction set architecture (ISA) extensions, including instructions, operations, and register files. The new instructions, operations, and register files are automatically recognized and exploited by the entire software tool chain, including the C/C++ compiler. Thus, taking advantage of the generated ASIP does not require any changes to the application or any assembly language coding. AutoTIE uses the C/C++ compiler to analyze an application, and based on the analysis generates thousands, or even millions, of possible ISA extensions for the application. AutoTIE then uses performance and hardware estimation techniques to combine the ISA extensions into a large number of potential ASIPs, and for a range of hardware costs, chooses the ASIP that provides the maximum performance improvement. For example, for an application performing a radix-4 FFT, AutoTIE considers over 34,000 potential sets of ISA extensions. For hardware costs ranging from 7800 gates to 128,000 gates, AutoTIE combines these extensions to form 31 ASIPs, which provide performance improvements ranging from a factor of 1.12 to a factor of 11.3 compared to a general-purpose processor.

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Cited By

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Wijtvliet MKumar ACorporaal H(2022)Blocks: Challenging SIMDs and VLIWs With a Reconfigurable ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312054141:9(2915-2928)Online publication date: Sep-2022
https://doi.org/10.1109/TCAD.2021.3120541
Chattopadhyay AWang ZMartin G(2022)Architecture Description LanguagesHandbook of Computer Architecture10.1007/978-981-15-6401-7_18-1(1-34)Online publication date: 25-Dec-2022
https://doi.org/10.1007/978-981-15-6401-7_18-1
Gnanasambandapillai VPeddersen JRagel RParameswaran S(2020)FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.3012211(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.3012211
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Index Terms

Automatic generation of application specific processors
1. Computer systems organization
  1. Architectures
    1. Other architectures

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Published In

CASES '03: Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems

October 2003

340 pages

ISBN:1581136765

DOI:10.1145/951710

General Chairs:
Jaime Moreno
IBM Research
,
Praveen Murthy
Fujitsu Labs of America
,
Program Chairs:
Tom Conte
North Carolina State University
,
Paolo Faraboschi
HP Labs

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 30 October 2003

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CASES03

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CASES03: 2003 International Conference on Compilers, Architectures and Synthesis for Embedded Systems

October 30 - November 1, 2003

California, San Jose, USA

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CASES '03 Paper Acceptance Rate 31 of 162 submissions, 19%;

Overall Acceptance Rate 52 of 230 submissions, 23%

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Wijtvliet MKumar ACorporaal H(2022)Blocks: Challenging SIMDs and VLIWs With a Reconfigurable ArchitectureIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2021.312054141:9(2915-2928)Online publication date: Sep-2022
https://doi.org/10.1109/TCAD.2021.3120541
Chattopadhyay AWang ZMartin G(2022)Architecture Description LanguagesHandbook of Computer Architecture10.1007/978-981-15-6401-7_18-1(1-34)Online publication date: 25-Dec-2022
https://doi.org/10.1007/978-981-15-6401-7_18-1
Gnanasambandapillai VPeddersen JRagel RParameswaran S(2020)FINDER: Find Efficient Parallel Instructions for ASIPs to Improve Performance of Large ApplicationsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2020.3012211(1-1)Online publication date: 2020
https://doi.org/10.1109/TCAD.2020.3012211
Hautala IBoutellier JSilven O(2020)TTADF: Power Efficient Dataflow-Based Multicore Co-Design FlowIEEE Transactions on Computers10.1109/TC.2019.293786769:1(51-64)Online publication date: 1-Jan-2020
https://doi.org/10.1109/TC.2019.2937867
Plagwitz PStreit FBecher AWildermann STeich J(2019)Compiler-Based High-Level Synthesis of Application-Specific Processors on FPGAs2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig)10.1109/ReConFig48160.2019.8994778(1-8)Online publication date: Dec-2019
https://doi.org/10.1109/ReConFig48160.2019.8994778
Savas SUl-Abdin ZNordström T(2018)Designing Domain-Specific Heterogeneous Architectures from Dataflow ProgramsComputers10.3390/computers70200277:2(27)Online publication date: 22-Apr-2018
https://doi.org/10.3390/computers7020027
Urban RSchölzel MVierhaus HAltmann ESeelig H(2015)Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIPProceedings of the 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems10.1109/DDECS.2015.15(17-22)Online publication date: 22-Apr-2015
https://dl.acm.org/doi/10.1109/DDECS.2015.15
Micconi LMadsen JPop P(2015)System-level synthesis of multi-ASIP platforms using an uncertainty modelIntegration, the VLSI Journal10.1016/j.vlsi.2015.07.00651:C(118-138)Online publication date: 1-Sep-2015
https://dl.acm.org/doi/10.1016/j.vlsi.2015.07.006
Miniskar NKohli SPark HYoo DChatha KErnst RRaghunathan AIyer R(2014)Retargetable automatic generation of compound instructions for CGRA based reconfigurable processor applicationsProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656125(1-9)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656106.2656125
Haaß MBauer LHenkel JChatha KErnst RRaghunathan AIyer R(2014)Automatic custom instruction identification in memory streaming algorithmsProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656114(1-9)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656106.2656114
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Automatic custom instruction identification for application-specific instruction set processors

Application-specific heterogeneous multiprocessor synthesis using extensible processors

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