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2020 – today
- 2022
[c19]Xuran Ge, Ming-che Lai, Yang Liu, Lizhou Wu, Zhutao Zhuang, Yang Ou, Zhiguang Chen, Nong Xiao:
SpacKV: A Pmem-Aware Key-Value Separation Store Based on LSM-Tree. NPC 2022: 327-339
2010 – 2019
- 2018
- [j9]Xiangke Liao, Kai Lu
, Canqun Yang, Jin-wen Li, Yuan Yuan, Ming-che Lai, Libo Huang, Ping-jing Lu, Jianbin Fang, Jing Ren, Jie Shen:
Moving from exascale to zettascale computing: challenges and techniques. Frontiers Inf. Technol. Electron. Eng. 19(10): 1236-1244 (2018) - 2014
- [j8]Sheng Ma, Natalie D. Enright Jerger, Zhiying Wang, Ming-che Lai, Libo Huang:
Holistic Routing Algorithm Design to Support Workload Consolidation in NoCs. IEEE Trans. Computers 63(3): 529-542 (2014) - 2013
- [j7]Ming-che Lai, Lei Gao, Nong Xiao, Zhiying Wang:
An accurate and highly-efficient performance evaluation approach based on queuing model for on-chip network. Sci. China Inf. Sci. 56(7): 1-20 (2013) - [j6]Libo Huang, Nong Xiao, Zhiying Wang, Yongwen Wang, Ming-che Lai:
Efficient multimedia coprocessor with enhanced SIMD engines for exploiting ILP and DLP. Parallel Comput. 39(10): 586-602 (2013) - [c18]Lei Gao, Ming-che Lai, Kefei Wang, Zhengbin Pang:
A Highly-Efficient Approach to Adaptive Load Balance for Scalable TBGP. NCCET 2013: 101-110 - 2011
- [j5]Nong Xiao, Zhiguang Chen, Fang Liu, Ming-che Lai, Longfei An:
P3Stor: A parallel, durable flash-based SSD for enterprise-scale storage systems. Sci. China Inf. Sci. 54(6): 1129-1141 (2011) - [j4]Ming-che Lai, Lei Gao:
Two-level tries: A general acceleration structure for parallel routing table accesses. J. Commun. Networks 13(4): 408-417 (2011) - [j3]Ming-che Lai, Lei Gao, Sheng Ma, Nong Xiao, Zhiying Wang:
A practical low-latency router architecture with wing channel for on-chip network. Microprocess. Microsystems 35(2): 98-109 (2011) - [c17]Yang Ou, Nong Xiao, Ming-che Lai:
A Scalable Multi-channel Parallel NAND Flash Memory Controller Architecture. ChinaGrid 2011: 48-53 - 2010
- [j2]Ming-che Lai, Lei Gao, Zhiying Wang:
Exploration and implementation of a highly efficient processor element for multimedia and signal processing domains. IET Comput. Digit. Tech. 4(5): 374-387 (2010)
2000 – 2009
- 2009
- [c16]Ming-che Lai, Lei Gao, Nong Xiao, Zhiying Wang:
An accurate and efficient performance analysis approach based on queuing model for network on chip. ICCAD 2009: 563-570 - [c15]Lei Gao, Ming-che Lai, Zhenghu Gong:
An Improved Parallel Access Technology on Routing Table for Threaded BGP. ICPADS 2009: 198-204 - [c14]Gao Lai, Ming-che Lai, Zhenghu Gong:
A Practical Non-blocking Route Propagation Technology for Threaded BGP. ScalCom-EmbeddedCom 2009: 206-211 - 2008
- [j1]Lei Gao, Zhenghu Gong, Yaping Liu, Ming-che Lai, Wei Peng:
A TLP approach for BGP based on local speculation. Sci. China Ser. F Inf. Sci. 51(11): 1772-1784 (2008) - [c13]Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang:
Memory System Design for a Multi-core Processor. CISIS 2008: 601-606 - [c12]Ming-che Lai, Jianjun Guo, Zhuxi Zhang, Zhiying Wang:
Using an Automated Approach to Explore and Design a High-Efficiency Processor Element for the Multimedia Domain. CISIS 2008: 613-618 - [c11]Ming-che Lai, Lei Gao, Wei Shi, Zhiying Wang:
Escaping from Blocking: A Dynamic Virtual Channel for Pipelined Routers. CISIS 2008: 795-800 - [c10]Lei Gao, Ming-che Lai, Zhenghu Gong:
Exploiting the Thread-Level Parallelism for BGP on Multi-core. CNSR 2008: 510-516 - [c9]Ming-che Lai, Zhiying Wang, Lei Gao, Hongyi Lu, Kui Dai:
A dynamically-allocated virtual channel architecture with congestion awareness for on-chip routers. DAC 2008: 630-633 - [c8]Jianjun Guo, Kui Dai, Ming-che Lai, Zhiying Wang:
The P2P Communication Model for a Local Memory based Multi-core Processor. ICYCS 2008: 1354-1359 - [c7]Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang:
Hierarchical memory system design for a heterogeneous multi-core processor. SAC 2008: 1504-1508 - 2007
- [c6]Ming-che Lai, Jianjun Guo, Lv Yasuai, Kui Dai, Zhiying Wang:
The Research of an Embedded Processor Element for Multimedia Domain. MCAM 2007: 267-276 - [c5]Libo Huang, Ming-che Lai, Kui Dai, Hong Yue, Li Shen:
Hardware Support for Arithmetic Units of Processor with Multimedia Extension. MUE 2007: 633-637 - [c4]Ming-che Lai, Zhiying Wang, Jianjun Guo, Kui Dai, Shen Li:
Template Vertical Dictionary-Based Program Compression Scheme on the TTA. PATMOS 2007: 43-52 - 2006
- [c3]Ming-che Lai, Kui Dai, Lu Hong-yi, Zhiying Wang:
A Novel Data-Parallel Coprocessor for Multimedia Signal Processing. ICME 2006: 369-372 - 2005
- [c2]Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang:
Design of a Configurable Embedded Processor Architecture for DSP Functions. ICPADS (2) 2005: 27-31 - 2004
- [c1]Ming-che Lai, Kui Dai, Li Shen, Zhiying Wang:
A New Technique for Program Code Compression in Embedded Microprocessor. ICESS 2004: 158-164
Coauthor Index
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