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2020 – today
- 2024
[j48]Yuto Arimura, Shigeru Yamashita:
Efficient Realization of an SC Circuit with Feedback and Its Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(7): 958-965 (2024)- [c79]Ryosuke Matsuo, Rudy Raymond, Shigeru Yamashita, Shin-ichi Minato:
Optimizing Decision Diagrams for Measurements of Quantum Circuits. ASPDAC 2024: 134-139 - [c78]Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
Simultaneous Routing with Washing Droplets in MEDA Biochips. ATAIT 2024: 190-201 - [c77]Zhidan Zheng
, Liaoyuan Cheng, Kanta Arisawa, Qingyu Li, Alexandre Truppel, Shigeru Yamashita, Tsun-Ming Tseng, Ulf Schlichtmann:
Multi-Resonance Mesh-Based Wavelength-Routed Optical Networks-on-Chip. DAC 2024: 74:1-74:6 - [c76]Kensuke Fukui, Shigeru Yamashita:
An Efficient Cost Reduction Method By Reusing Intermediate Droplets in MEDA Biochips. ISOCC 2024: 1-2 - [c75]Suzuki Koki, Shigeru Yamashita:
An Efficient Error Correction Method for DMFBs with Node Redundancy Considering Node Levels. ISOCC 2024: 294-295 - 2023
- [j47]Ikuru Yoshida, Shigeru Yamashita:
Making General Dilution Graphs Robust to Unbalanced-Split Errors on Digital Microfluidic Biochips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(2): 97-105 (2023) - [j46]Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita:
An Efficient Method to Decompose and Map MPMCT Gates That Accounts for Qubit Placement. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(2): 124-132 (2023) - [j45]Atsushi Matsuo, Shigeru Yamashita, Daniel J. Egger:
A SAT Approach to the Initial Mapping Problem in SWAP Gate Insertion for Commuting Gates. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(11): 1424-1431 (2023) - [j44]Atsushi Matsuo, Yudai Suzuki, Ikko Hamamura, Shigeru Yamashita:
Enhancing VQE Convergence for Optimization Problems with Problem-Specific Parameterized Quantum Circuits. IEICE Trans. Inf. Syst. 106(11): 1772-1782 (2023) - [j43]Tomohisa Kawakami, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
A Deep Reinforcement Learning Approach to Droplet Routing for Erroneous Digital Microfluidic Biochips. Sensors 23(21): 8924 (2023) - [j42]Debraj Kundu, Venkata Lavanya Sarvasiddi, Sukanta Bhattacharjee, Shigeru Yamashita, Sudip Roy:
Preparing Fluid Samples Under Retention Time Constraints Using Flow-Based Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 3021-3030 (2023) - [c74]Kyohei Seino, Shigeru Yamashita:
An SMT-Solver-Based Synthesis of NNA-Compliant Quantum Circuits Consisting of CNOT, H and T Gates. ASP-DAC 2023: 196-201 - [c73]Yuji Wada, Shigeru Yamashita:
Minimizing the Impact of Unbalanced Splitting Errors on DMFBs Without Any Overhead. DSD 2023: 531-538 - [c72]Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
Multi-Droplet Routing based on a Shape-Dependent Velocity Model on MEDA Biochips. ICEIC 2023: 1-4 - [c71]David Clarino, Naoya Asada, Shigeru Yamashita:
Optimizing LUT-Based Quantum Circuit Synthesis Using Relative Phase Boolean Operations. ICCAD 2023: 1-8 - [c70]David Clarino, Shohei Kuroda, Shigeru Yamashita:
Using S Gates and Relative Phase Toffoli Gates to Improve T-Count in Quantum Boolean Circuits. ISMVL 2023: 147-152 - [c69]Tomohisa Kawakami, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
A Deep Reinforcement Learning-based Routing Algorithm for Unknown Erroneous Cells in DMFBs. NEWCAS 2023: 1-5 - [c68]Kaito Mori, Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
A Fast Approach to Droplet Routing with Shape-Dependent Velocity on MEDA Biochips. NEWCAS 2023: 1-5 - [c67]Masataka Hirai, Debraj Kundu, Shigeru Yamashita, Sudip Roy, Hiroyuki Tomiyama:
Transport-Free Placement of Mixers for Realizing Bioprotocol on Programmable Microfluidic Devices. VLSID 2023: 193-198 - 2022
- [j41]Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita, Sudip Roy:
Shape-Dependent Velocity Based Droplet Routing on MEDA Biochips. IEEE Access 10: 122423-122430 (2022) - [j40]Yifang Bao, Shigeru Yamashita, Bing Li, Tsung-Yi Ho:
Mixer-Based Washing Methods for Programmable Microfluidic Devices. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(10): 1385-1391 (2022) - [j39]Syoki Kawaminami, Yukino Watanabe, Shigeru Yamashita:
Approximating stochastic numbers to reduce latency. it Inf. Technol. 64(3): 109-118 (2022) - [c66]Shohei Kuroda, Shigeru Yamashita:
Optimization of Quantum Boolean Circuits by Relative-Phase Toffoli Gates. RC 2022: 20-27 - 2021
- [j38]Debraj Kundu, Jitendra Giri, Sataru Maruyama, Sudip Roy, Shigeru Yamashita:
Fluid-to-cell assignment and fluid loading on programmable microfluidic devices for bioprotocol execution. Integr. 78: 95-109 (2021) - [c65]Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita:
Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures. ASP-DAC 2021: 786-791 - [c64]Chiharu Shiro, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama, Shigeru Yamashita:
Minimization of Routing Area in MEDA Biochips. BioCAS 2021: 1-5 - [c63]Shuaijie Ying, Sudip Roy, Juinn-Dar Huang, Shigeru Yamashita:
Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-Chip. DSD 2021: 488-494 - [c62]Shoki Kawaminami, Shigeru Yamashita:
Triple-Rail Stochastic Number and Its Applications. ISOCC 2021: 161-162 - [c61]Katsuhiro Ichikawa, Shigeru Yamashita:
A Multiply Accumulator for Stochastic Numbers Without Scaling Errors. VLSID 2021: 88-93 - [e2]Shigeru Yamashita, Tetsuo Yokoyama:
Reversible Computation - 13th International Conference, RC 2021, Virtual Event, July 7-8, 2021, Proceedings. Lecture Notes in Computer Science 12805, Springer 2021, ISBN 978-3-030-79836-9 [contents] - 2020
- [j37]Yiran Chen, Deliang Fan, Yanzhi Wang, Shigeru Yamashita:
Editorial for the special issue on disruptive computing technologies. CCF Trans. High Perform. Comput. 2(3): 209-210 (2020) - [j36]Yudai Sakamoto, Shigeru Yamashita:
Efficient Methods to Generate Constant SNs with Considering Trade-Off between Error and Overhead and Its Evaluation. IEICE Trans. Inf. Syst. 103-D(2): 321-328 (2020) - [j35]Jingwen Ding, Shigeru Yamashita:
Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architecture and Its Application to Large-Scale Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(5): 1045-1058 (2020) - [c60]Satoru Maruyama, Debraj Kundu, Shigeru Yamashita, Sudip Roy:
Optimization of Fluid Loading on Programmable Microfluidic Devices for Bio-protocol Execution. ASP-DAC 2020: 550-555 - [c59]Gautam Choudhary, Sandeep Pal, Debraj Kundu, Sukanta Bhattacharjee, Shigeru Yamashita, Bing Li, Ulf Schlichtmann, Sudip Roy:
Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve Arrays. DATE 2020: 1335-1338 - [c58]Soma Esaki, Shigeru Yamashita:
Reducing T-count When Decomposing Many MPMCT Gates Simultaneously. ISMVL 2020: 22-27
2010 – 2019
- 2019
- [j34]Kota Asai, Shigeru Yamashita:
Compaction of Topological Quantum Circuits by Modularization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(4): 624-632 (2019) - [j33]Wakaki Hattori, Shigeru Yamashita:
Mapping a Quantum Circuit to 2D Nearest Neighbor Architecture by Changing the Gate Order. IEICE Trans. Inf. Syst. 102-D(11): 2127-2134 (2019) - [j32]Chin-Heng Liu, Chia-Chun Lin, Yung-Chih Chen, Chia-Cheng Wu, Chun-Yao Wang, Shigeru Yamashita:
Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(12): 2284-2297 (2019) - [j31]Ankur Gupta, Juinn-Dar Huang, Shigeru Yamashita, Sudip Roy:
Design Automation for Dilution of a Fluid Using Programmable Microfluidic Device-Based Biochips. ACM Trans. Design Autom. Electr. Syst. 24(2): 21:1-21:24 (2019) - [c57]Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita:
Reducing the Overhead of Mapping Quantum Circuits to IBM Q System. ISCAS 2019: 1-5 - [c56]Kenta Shirane, Takahiro Yamamoto, Ittetsu Taniguchi, Yuko Hara-Azumi, Shigeru Yamashita, Hiroyuki Tomiyama:
Maximum Error-Aware Design of Approximate Array Multipliers. ISOCC 2019: 73-74 - [c55]Atsushi Matsuo, Shigeru Yamashita:
An Efficient Method for Quantum Circuit Placement Problem on a 2-D Grid. RC 2019: 162-168 - [c54]Kang-Yi Fan, Shigeru Yamashita, Juinn-Dar Huang:
Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic Biochips Using Network Flow Models. VLSI-DAT 2019: 1-4 - [c53]Yudai Sakamoto, Shigeru Yamashita:
Reducing the Overhead of Stochastic Number Generators Without Increasing Error. VLSID 2019: 52-57 - 2018
- [j30]Nurul Ain Binti Adnan, Shigeru Yamashita:
Logical Qubit Layout Problem for ICM Representation. J. Inf. Process. 26: 20-28 (2018) - [c52]Wakaki Hattori, Shigeru Yamashita:
Quantum Circuit Optimization by Changing the Gate Order for 2D Nearest Neighbor Architectures. RC 2018: 228-243 - 2017
- [j29]Nurul Ain Binti Adnan, Shigeru Yamashita, Alan Mishchenko:
Reduction of Quantum Cost by Making Temporary Changes to the Function. IEICE Trans. Inf. Syst. 100-D(7): 1393-1402 (2017) - [j28]Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi:
A Systematic Methodology for Design and Worst-Case Error Analysis of Approximate Array Multipliers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1496-1499 (2017) - [j27]Ritsuko Muguruma, Shigeru Yamashita:
Stochastic Number Generation with the Minimum Inputs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(8): 1661-1671 (2017) - [i8]Shigeru Yamashita, Tsung-Yi Ho, Robert Wille, Krishnendu Chakrabarty:
Microfluidic Biochips: Bridging Biochemistry with Computer Science and Engineering (NII Shonan Meeting 2017-1). NII Shonan Meet. Rep. 2017 (2017) - 2016
- [j26]Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Rudy Raymond, Seiichiro Tani, Shigeru Yamashita:
Quantum Query Complexity of Almost All Functions with Fixed On-set Size. Comput. Complex. 25(4): 723-735 (2016) - [j25]Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho:
A Full-Flexibility-Guaranteed Pin-Count Reduction Design for General-Purpose Digital Microfluidic Biochips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(2): 570-578 (2016) - [c51]Takahiro Yamamoto, Ittetsu Taniguchi, Hiroyuki Tomiyama, Shigeru Yamashita, Yuko Hara-Azumi:
A systematic methodology for design and analysis of approximate array multipliers. APCCAS 2016: 352-354 - [c50]Jason Helge Anderson, Yuko Hara-Azumi, Shigeru Yamashita:
Effect of LFSR seeding, scrambling and feedback polynomial on stochastic computing accuracy. DATE 2016: 1550-1555 - [c49]Nurul Ain Binti Adnan, Kouhei Kushida, Shigeru Yamashita:
A pre-optimization technique to generate initial reversible circuits with low quantum cost. ISCAS 2016: 2298-2301 - [c48]Tsung-Yi Ho, Shigeru Yamashita, Ansuman Banerjee, Sudip Roy:
Design of Microfluidic Biochips: Connecting Algorithms and Foundations of Chip Design to Biochemistry and the Life Sciences. VLSID 2016: 59-62 - [c47]Ritsuko Muguruma, Shigeru Yamashita:
Stochastic Number Generation with Few Inputs. VLSID 2016: 128-133 - [c46]Abhimanyu Yadav, Trung Anh Dinh, Daiki Kitagawa, Shigeru Yamashita:
ILP-based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips. VLSID 2016: 355-360 - [i7]P. Balasubramanian, Shigeru Yamashita:
Area/latency optimized early output asynchronous full adders and relative-timed ripple carry adders. CoRR abs/1604.04006 (2016) - 2015
- [j24]Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho:
An Optimal Pin-Count Design With Logic Optimization for Digital Microfluidic Biochips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(4): 629-641 (2015) - [c45]Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty:
Testing of digital microfluidic biochips with arbitrary layouts. ETS 2015: 1-2 - [c44]Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Krishnendu Chakrabarty:
A general testing method for digital microfluidic biochips under physical constraints. ITC 2015: 1-8 - 2014
- [j23]Hiroaki Yoshida, Masayuki Wakizaka, Shigeru Yamashita, Masahiro Fujita:
An Energy-Efficient Patchable Accelerator and Its Design Methods. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2507-2517 (2014) - [c43]Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho:
A network-flow-based optimal sample preparation algorithm for digital microfluidic biochips. ASP-DAC 2014: 225-230 - [c42]Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho:
A logic integrated optimal pin-count design for digital microfluidic biochips. DATE 2014: 1-6 - [c41]Shunichi Sanae, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima:
Better-Than-DMR Techniques for Yield Improvement. FCCM 2014: 34 - [c40]Nurul Ain Binti Adnan, Shigeru Yamashita, Simon J. Devitt, Kae Nemoto:
2D Qubit Layout Optimization for Topological Quantum Computation. RC 2014: 176-188 - [e1]Shigeru Yamashita, Shin-ichi Minato:
Reversible Computation - 6th International Conference, RC 2014, Kyoto, Japan, July 10-11, 2014. Proceedings. Lecture Notes in Computer Science 8507, Springer 2014, ISBN 978-3-319-08493-0 [contents] - 2013
- [j22]Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. IEICE Trans. Inf. Syst. 96-D(1): 1-8 (2013) - [j21]Tanvir Ahmed, Jun Yao, Yuko Hara-Azumi, Shigeru Yamashita, Yasuhiko Nakashima:
Selective Check of Data-Path for Effective Fault Tolerance. IEICE Trans. Inf. Syst. 96-D(8): 1592-1601 (2013) - [j20]Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi:
Clique-Based Architectural Synthesis of Flow-Based Microfluidic Biochips. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2668-2679 (2013) - [c39]Trung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho, Yuko Hara-Azumi:
A clique-based approach to find binding and scheduling result in flow-based microfluidic biochips. ASP-DAC 2013: 199-204 - [c38]P. Balasubramanian, Shigeru Yamashita:
On the Error Resiliency of Combinational Logic Cells - Implications for Nano-based Digital Design. PRDC 2013: 118-119 - 2012
- [j19]Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Quantum Walks on the Line with Phase Parameters. IEICE Trans. Inf. Syst. 95-D(3): 722-730 (2012) - [j18]Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller:
Synthesis of Semi-Classical Quantum Circuits. J. Multiple Valued Log. Soft Comput. 18(1): 99-114 (2012) - [c37]Hratch Mangassarian, Hiroaki Yoshida, Andreas G. Veneris, Shigeru Yamashita, Masahiro Fujita:
On error tolerance and Engineering Change with Partially Programmable Circuits. ASP-DAC 2012: 695-700 - [c36]Shigeru Yamashita:
An Optimization Problem for Topological Quantum Computation. Asian Test Symposium 2012: 61-66 - [c35]Masayuki Wakizaka, Hiroaki Yoshida, Yuko Hara-Azumi, Shigeru Yamashita:
A redundant wire addition method for Patchable Accelerator. ICECS 2012: 552-555 - [c34]Richard Cleve, Kazuo Iwama, François Le Gall, Harumichi Nishimura, Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita:
Reconstructing Strings from Substrings with Quantum Queries. SWAT 2012: 388-397 - [c33]Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. TAMC 2012: 400-411 - [i6]Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. CoRR abs/1202.6444 (2012) - [i5]Richard Cleve, Kazuo Iwama, François Le Gall, Harumichi Nishimura, Seiichiro Tani, Junichi Teruyama, Shigeru Yamashita:
Reconstructing Strings from Substrings with Quantum Queries. CoRR abs/1204.4691 (2012) - [i4]Marcos Villagra, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Tensor Rank and Strong Quantum Nondeterminism in Multiparty Communication. Electron. Colloquium Comput. Complex. TR12 (2012) - 2011
- [j17]Yuichi Hirata, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
An efficient conversion of quantum circuits to a linear nearest neighbor architecture. Quantum Inf. Comput. 11(1&2): 142-166 (2011) - [c32]Hiroshi Aoki, Shigeru Yamashita, Shin-ichi Minato:
An efficient algorithm for constructing a Sequence Binary Decision Diagram representing a set of reversed sequences. GrC 2011: 54-59 - [c31]Atsushi Matsuo, Shigeru Yamashita:
Changing the Gate Order for Optimal LNN Conversion. RC 2011: 89-101 - 2010
- [j16]Shigeru Yamashita, Igor L. Markov:
Fast equivalence - checking for quantum circuits. Quantum Inf. Comput. 10(9&10): 721-734 (2010) - [c30]Shigeru Yamashita, Igor L. Markov:
Fast equivalence-checking for quantum circuits. NANOARCH 2010: 23-28
2000 – 2009
- 2009
- [j15]Seiichiro Tani, Masaki Nakanishi, Shigeru Yamashita:
Multi-Party Quantum Communication Complexity with Routed Messages. IEICE Trans. Inf. Syst. 92-D(2): 191-199 (2009) - [j14]Yumi Nakajima, Yasuhito Kawano, Hiroshi Sekigawa, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
Synthesis of quantum circuits for d-level systems by using cosine-sine decomposition. Quantum Inf. Comput. 9(5&6): 423-443 (2009) - [i3]Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Rudy Raymond, Seiichiro Tani, Shigeru Yamashita:
Average/Worst-Case Gap of Quantum Query Complexities by On-Set Size. CoRR abs/0908.2468 (2009) - [i2]Shigeru Yamashita, Igor L. Markov:
Fast Equivalence-checking for Quantum Circuits. CoRR abs/0909.4119 (2009) - 2008
- [j13]Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller:
DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3793-3802 (2008) - [c29]Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller:
An efficient verification of quantum circuits under a practical restriction. CIT 2008: 873-879 - [c28]Seiichiro Tani, Masaki Nakanishi, Shigeru Yamashita:
Multi-party Quantum Communication Complexity with Routed Messages. COCOON 2008: 180-190 - [c27]Kazuo Iwama, Harumichi Nishimura, Mike Paterson, Rudy Raymond, Shigeru Yamashita:
Polynomial-Time Construction of Linear Network Coding. ICALP (1) 2008: 271-282 - [c26]Andris Ambainis, Kazuo Iwama, Masaki Nakanishi, Harumichi Nishimura, Rudy Raymond, Seiichiro Tani, Shigeru Yamashita:
Quantum Query Complexity of Boolean Functions with Small On-Sets. ISAAC 2008: 907-918 - [c25]Kouki Suzuki, Takashi Nakada, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
A Functional Unit with Small Variety of Highly Reliable Cells. PRDC 2008: 353-354 - 2007
- [j12]Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe:
Robust Quantum Algorithms Computing OR with epsilon-Biased Oracles. IEICE Trans. Inf. Syst. 90-D(2): 395-402 (2007) - [j11]Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Rudy Raymond, Shigeru Yamashita:
Improved algorithms for quantum identification of Boolean oracles. Theor. Comput. Sci. 378(1): 41-53 (2007) - [c24]Shinya Hiramoto, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima:
A Hardware SAT Solver Using Non-chronological Backtracking and Clause Recording Without Overheads. ARC 2007: 343-349 - [c23]Shigeru Yamashita, Masaki Nakanishi:
A practical framework to utilize quantum search. IEEE Congress on Evolutionary Computation 2007: 4086-4093 - [c22]Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita:
Unbounded-Error One-Way Classical and Quantum Communication Complexity. ICALP 2007: 110-121 - [c21]Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita:
Unbounded-Error Classical and Quantum Communication Complexity. ISAAC 2007: 100-111 - [c20]Masahito Hayashi, Kazuo Iwama, Harumichi Nishimura, Rudy Raymond Harry Putra, Shigeru Yamashita:
Quantum Network Coding. STACS 2007: 610-621 - 2006
- [j10]Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe:
An Efficient and Effective Algorithm for Online Task Placement with I/O Communications in Partially Reconfigurable FPGAs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3416-3426 (2006) - [j9]Kazuo Iwama, Akinori Kawachi, Shigeru Yamashita:
Quantum Biased Oracles. Inf. Media Technol. 1(1): 169-177 (2006) - [j8]Mark Adcock, Richard Cleve, Kazuo Iwama, Raymond H. Putra, Shigeru Yamashita:
Quantum lower bounds for the Goldreich-Levin problem. Inf. Process. Lett. 97(5): 208-211 (2006) - [c19]Shigeru Yamashita, Katsunori Tanaka, Hideyuki Takada, Koji Obata, Kazuyoshi Takagi:
A transduction-based framework to synthesize RSFQ circuits. ASP-DAC 2006: 266-272 - [c18]Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Kazuo Nakajima, Katsumasa Watanabe:
A New Approach to Online FPGA Placement. CISS 2006: 145-150 - [c17]Tomoya Suzuki, Shigeru Yamashita, Masaki Nakanishi, Katsumasa Watanabe:
Robust Quantum Algorithms with epsilon-Biased Oracles. COCOON 2006: 116-125 - [c16]Masahito Hayashi, Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita:
(4, 1)-Quantum Random Access Coding Does Not Exist. ISIT 2006: 446-450 - [c15]Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Rudy Raymond Harry Putra, Shigeru Yamashita:
Improved Algorithms for Quantum Identification of Boolean Oracles. SWAT 2006: 280-291 - [i1]Masahito Hayashi, Kazuo Iwama, Harumichi Nishimura, Rudy Raymond, Shigeru Yamashita:
Quantum Network Coding. Complexity of Boolean Functions 2006 - 2005
- [j7]Kazuo Iwama, Akinori Kawachi, Shigeru Yamashita:
Quantum Sampling for Balanced Allocations. IEICE Trans. Inf. Syst. 88-D(1): 39-46 (2005) - [j6]Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi:
SPFD-Based Flexible Transformation of LUT-Based FPGA Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 1038-1046 (2005) - [c14]Mitsuru Tomono, Masaki Nakanishi, Katsumasa Watanabe, Shigeru Yamashita:
Event-oriented computing with reconfigurable platform. ASP-DAC 2005: 1248-1251 - [c13]Nobuo Nakai, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe:
Reconfigurable 1-Bit Processor Array with Reduced Wirng Area. ERSA 2005: 225-234 - 2004
- [c12]Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi:
SPFD-based one-to-many rewiring. FPGA 2004: 250 - [c11]Katsunori Tanaka, Shigeru Yamashita, Yahiko Kambayashi:
SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits. ACM Great Lakes Symposium on VLSI 2004: 348-353 - [c10]Andris Ambainis, Kazuo Iwama, Akinori Kawachi, Hiroyuki Masuda, Raymond H. Putra, Shigeru Yamashita:
Quantum Identification of Boolean Oracles. STACS 2004: 105-116 - 2003
- [j5]Kazuo Iwama, Shigeru Yamashita:
Transformation Rules for CNOT-based Quantum Circuits and Their Applications. New Gener. Comput. 21(4): 297-317 (2003) - [j4]Noboru Kunihiro, Shigeru Yamashita:
Efficient Algorithms for NMR Quantum Computers with Small Qubits. New Gener. Comput. 21(4): 329-337 (2003) - [c9]Kazuo Iwama, Akinori Kawachi, Shigeru Yamashita:
Quantum Sampling for Balanced Allocations. COCOON 2003: 304-318 - 2002
- [c8]Kazuo Iwama, Yahiko Kambayashi, Shigeru Yamashita:
Transformation rules for designing CNOT-based quantum circuits. DAC 2002: 419-424 - 2000
- [j3]Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
SPFD: A new method to express functional flexibility. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(8): 840-849 (2000) - [c7]Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. ASP-DAC 2000: 253-258
1990 – 1999
- 1999
- [c6]Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
An Integrated Approach for Synthesizing LUT Networks. Great Lakes Symposium on VLSI 1999: 136-139 - 1998
- [c5]Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
New Methods to Find Optimal Non-Disjoint Bi-Decompositions. ASP-DAC 1998: 59-68 - [c4]Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya:
Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions. DATE 1998: 755-759 - 1997
- [c3]Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya:
Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables. Great Lakes Symposium on VLSI 1997: 39-44 - 1996
- [j2]Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga:
Design of logic circuits with wired-logic utilizing transduction method. Syst. Comput. Jpn. 27(11): 19-28 (1996) - [j1]Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga:
Optimization methods for look-up table-type FPGAs based on permissible functions. Syst. Comput. Jpn. 27(12): 92-101 (1996) - [c2]Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya:
A new method to express functional permissibilities for LUT based FPGAs and its applications. ICCAD 1996: 254-261 - 1995
- [c1]Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga:
Optimization methods for lookup-table-based FPGAs using transduction method. ASP-DAC 1995
Coauthor Index
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