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ORCIDDATE 1998: Paris, France
- Patrick M. Dewilde, Franz J. Rammig, Gerry Musgrave:
1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France. IEEE Computer Society 1998, ISBN 0-8186-8359-7
Design Optimization of Building Blocks
- Alexander Chatzigeorgiou, Spiridon Nikolaidis
:
Collapsing the Transistor Chain to an Effective Single Equivalent Transistor. 2-6 - Michael Nicolaidis, Ricardo de Oliveira Duarte:
Design of Fault-Secure Parity-Prediction Booth Multipliers. 7-14 - Kimihiro Ogawa, Michinari Kohno, Fusako Kitamura:
PASTEL: A Parameterized Memory Characterization System. 15-20
HW/SW Partitioning and Communication Synthesis
- Jesper Grode, Peter Voigt Knudsen, Jan Madsen:
Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System. 22-27 - Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri:
Hardware Software Partitioning with Integrated Hardware Design Space Exploration. 28-35 - Michael Gasteier, Manfred Glesner, Michael Münch:
Generation of Interconnect Topologies for Communication Synthesis. 36-42
Asynchronous and Hybrid VHDL-Based Design
- Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen:
The Design of an Asynchronous VHDL Synthesizer. 44-51 - Christoph Grimm, Klaus Waldschmidt:
Repartitioning and Technology-Mapping of Electronic Hybrid Systems. 52-58 - Eduard Moser, Norbert Mittwollen:
VHDL-AMS: The Missing Link in System Design - Experiments with Unified Modelling in Automotive Engineering. 59-63
Data Path and FPGA Testing
- Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer:
Scheduling and Module Assignment for Reducing Bist Resources. 66-73 - Laurence Tianruo Yang, Zebo Peng:
An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis. 74-81 - Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian:
RAM-Based FPGA's: A Test Approach for the Configurable Logic. 82-88 - Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi:
Novel Technique for Testing FPGAs. 89-94
Design Methods for High Performance Applications
- Juan Carlos Diaz, Pierre Plaza, Jesus Crespo:
ATM Traffic Shaper: ATS. 96-101 - E. Lago, Carlos Jesús Jiménez-Fernández, Diego R. López, Santiago Sánchez-Solano, Angel Barriga:
XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers. 102-107 - Wolfgang Eppler, Thomas Fischer, Hartmut Gemmeke, A. Menchikov:
High Speed Neural Network Chip for Trigger Purposes in High Energy Physics. 108-115
Scheduling in Embedded Systems
- Bharat P. Dave, Niraj K. Jha:
CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures. 118-124 - Jeroen A. J. Leijten, Jef L. van Meerbergen, Adwin H. Timmer, Jochen A. G. Jess:
Stream Communication between Real-Time Tasks in a High-Performance Multiprocessor. 125-131 - Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli, Paul Pop:
Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems. 132-138
Advanced Techniques for VHDL Design
- Yee-Wing Hsieh, Steven P. Levitan:
Model Abstraction for Formal Verification. 140-147 - Jason Coppens, Dhamin Al-Khalili, Côme Rozon:
VHDL Modelling and Analysis of Fault Secure Systems. 148-152 - Matthias Mutz:
Register Transfer Level VHDL Models without Clocks. 153-158 - Edwin Naroska:
Parallel VHDL Simulation. 159-163
Novel BIST Approaches
- Wei Zhao, Christos A. Papachristou:
Testing DSP Cores Based on Self-Test Programs. 166-172 - Vyacheslav N. Yarmolik, Sybille Hellebrand, Hans-Joachim Wunderlich:
Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs. 173-179 - T. Bogue, Michael Gössel, Helmut Jürgensen, Yervant Zorian:
Built-In Self-Test with an Alternating Output. 180-184
Architectures for Image Processing
- Claus Schneider, Martin Kayss, Thomas Hollstein, Jürgen Deicke:
From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms. 186-190 - A. M. Rassau, T. C. B. Yu, H. Cheung, Stefan Lachowicz, Kamran Eshraghian, William A. Crossland, Tim D. Wilkinson:
Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications. 191-195 - Isidoro Urriza, José Ignacio Artigas, José I. García-Nicolás, Luis Angel Barragan, Denis Navarro:
VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform. 196-201
Scheduling and Analysis of HW/SW
- Alberto Allara, William Fornaciari, Fabio Salice, Donatella Sciuto:
A Model for System-Level Timed Analysis and Profiling. 204-210 - Bill Lin:
Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling. 211-217 - Juan Antonio Maestro, Daniel Mozos, Hortensia Mecha:
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. 218-225 - Joachim Gerlach, Wolfgang Rosenstiel:
A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment. 226-231
Extensions to VHDL
- Guido Schumacher, Wolfgang Nebel:
Object-Oriented Modelling of Parallel Hardware Systems. 234-241 - Wolfram Putzke-Röming, Martin Radetzki, Wolfgang Nebel:
A Flexible Message Passing Mechanism for Objective VHDL. 242-249 - Michael Mrva:
Enhanced Reuse and Teamwork Capabilities for an Object-oriented Extension of VHDL. 250-256 - Ralf Reetz, Klaus Schneider, Thomas Kropf:
Formal Specification in VHDL for Hardware Verification. 257-263
Error Detection and Design Validation
- Anna Antola, Vincenzo Piuri, Mariagiovanna Sami:
A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths. 266-272 - Li-C. Wang, Magdy S. Abadir, Jing Zeng:
Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. 273-277 - Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee:
Functional Scan Chain Testing. 278-283
IP Based System-on-a-Chip Design
- Grant Martin:
Design Methodologies for System Level IP. 286-289 - Bart de Loore:
IP-Based System-on-a-Chip Design. 290
Design Reuse Methodologies
- Manfred Koegst, Dieter Garte, Peter Conradi, Michael G. Wahl:
A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits. 292-296 - Serafín Olcoz, Lorenzo Ayuda, Ivan Izaguirre, Olga Peñalba:
VHDL Teamwork, Organization Units and Workspace Management. 297-302 - Jörg Böttger, Karlheinz Agsteiner, Dieter Monjau, Sören Schulze:
An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse. 303-310
Flat and Timing-Driven Processor Design
- Jürgen Koehl, Ulrich Baur, Thomas Ludwig, Bernhard Kick, Thomas Pflueger:
A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset. 312-320 - Jens Vygen:
Algorithms for Detailed Placement of Standard Cells. 321-324 - Uwe Fassnacht, Jürgen Schietke:
Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset. 325-331 - Asmus Hetzel:
A Sequential Detailed Router for Huge Grid Graphs. 332-338
Reconfigurable Systems
- W. Shields Neely:
Reconfigurable Logic for Systems on a Chip. 340 - Jan M. Rabaey, Marlene Wan:
An Energy-Conscious Exploration Methodology for Reconfigurable DSPs. 341-342 - Ian Page:
Design Of Future Systems. 343-347
Digital Simulation and Estimation
- V. Chandramouli, Jesse Whittemore, Karem A. Sakallah:
AFTA: A Formal Delay Model for Functional Timing Analysis. 350-355 - Dirk Rabe, Gerd Jochens, Lars Kruse, Wolfgang Nebel:
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs. 356-361 - Stefan Schmerler, Yankin Tanurhan, Klaus D. Müller-Glaser:
Advanced Optimistic Approaches in Logic Simulation. 362-368
Synthesis of Reprogrammable and Reconfigurable Architectures
- Andreas Pyttel, Alexander Sedlmeier, Christian Veith:
PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems. 370-376 - Bart Mesman, Marino T. J. Strik, Adwin H. Timmer, Jef L. van Meerbergen, Jochen A. G. Jess:
A Constraint Driven Approach to Loop Pipelining and Register Binding. 377-383 - Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung:
Multiple Behavior Module Synthesis Based on Selective Groupings. 384-388 - Meenakshi Kaul, Ranga Vemuri:
Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures. 389-396
Partitioning and Routing
- Jianjian Song, Zhaoxuan Shen, Wenjun Zhuang:
An Effective General Connectivity Concept for Clustering. 398-405 - Christopher S. Helvig, Gabriel Robins, Alexander Zelikovsky:
Improved Approximation Bounds for the Group Steiner Problem. 406-413 - Thorsten Adler, Juergen Schaeuble:
An Interactive Router for Analog IC Design. 414-420
Panel - Formal Verification: A New Standard CAD Tool for the Industrial Design Flow
- Wolfgang Rosenstiel:
Formal Verification: A New Standard CAD Tool for the Industrial Design Flow. 422
Simulation for High-Level Design
- Guido Post, Andrea Müller, Thorsten Grötker:
A System-Level Co-Verification Environment for ATM Hardware Design. 424-428 - Holger Keding, Markus Willems, Martin Coors, Heinrich Meyr:
FRIDGE: A Fixed-Point Design and Simulation Environment. 429-435 - Cordula Hansen, Arno Kunzmann, Wolfgang Rosenstiel:
Verification by Simulation Comparison using Interface Synthesis. 436-443
Architectural Synthesis
- Min Xu, Fadi J. Kurdahi:
Layout-Driven High Level Synthesis for FPGA Based Architectures. 446-450 - Oliver Bringmann, Wolfgang Rosenstiel:
Cross-Level Hierarchical High-Level Synthesis. 451-456 - Jian Li, Rajesh K. Gupta:
An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions. 457-463
Timing and Crosstalk in Interconnect
- Dongsheng Wang, Ernest S. Kuh:
A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction. 466-470 - Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma:
Interconnect Tuning Strategies for High-Performance Ics. 471-478 - Chris C. N. Chu, D. F. Wong:
A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing. 479-485
Panel: Next Generation System Design Tools
- Wolfgang Rosenstiel:
Next Generation System Level Design Tools. 488-
IDDQ and Memory Testing
- Rosa Rodríguez-Montañés, Joan Figueras:
Estimation of the Defective IDDQ Caused by Shorts in Deep-Submicron CMOS ICs. 490-494 - B. Straka, Hans A. R. Manhaeve, Jozef Vanneuville, M. Svajda:
A Fully Digital Controlled Off-Chip IDDQ Measurement Unit. 495-500 - Ad J. van de Goor, Issam B. S. Tlili:
March Tests for Word-Oriented Memories. 501-508
Microsystems
- R. Neul, U. Becker, G. Lorenz, Peter Schwarz, Jürgen Haase, S. Wünsche:
A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation. 510-517 - Vladimír Székely, Márta Rencz:
Fast Field Solvers for Thermal and Electrostatic Analysis. 518-523 - Marcelo Lubaszewski, Érika F. Cota, Bernard Courtois:
Microsystems Testing: an Approach and Open Problems. 524-528
Interconnect Modeling
- Roland W. Freund, Peter Feldmann:
Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation. 530-537 - Nuno Alexandre Marques, Mattan Kamon, Jacob K. White, Luís Miguel Silveira:
An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models. 538-543 - Jianhua Shao, Richard M. M. Chen:
MCM Interconnect Design Using Two-Pole Approximation. 544-548
Design for Manufacturability - Embedded Tutorial
- Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare:
Design-Manufacturing Interface: Part I - Vision. 550-556 - Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon:
Design-Manufacturing Interface: Part II - Applications. 557-562 - Hans T. Heineken, Wojciech Maly:
Performance - Manufacturability Tradeoffs in IC Design. 563-567
Sequential Circuit Testing
- Elizabeth M. Rudnick, Roberto Vietti, Akilah Ellis, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. 570-576 - Michael S. Hsiao, Srimat T. Chakradhar:
State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits. 577-582 - Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. 583-587
Issues in Behavioral Synthesis
- Abderrazek Jemai, Polen Kission, Ahmed Amine Jerraya:
Architectural Simulation in the Context of Behavioral Synthesis. 590-595 - Johnny Öberg, Ahmed Hemani, Anshul Kumar:
Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols. 596-603 - Samuel Norman Hamilton, Alex Orailoglu:
Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs. 604-609
Formal Equivalence Checking Using Decision Diagrams
- Stefan Höreth, Rolf Drechsler:
Dynamic Minimization of Word-Level Decision Diagrams. 612-617 - C. A. J. van Eijk:
Sequential Equivalence Checking without State Space Traversal. 618-623 - Lluís Ribas, Jordi Carrabina:
On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits. 624-629
Silicon Debug of Systems-on-Chips
- Silicon Debug of Systems-on-Chips. 632-633
Characterization and Verification of Analogue Circuits
- Josef Eckmüller, Martin Groepl, Helmut E. Graeb:
Hierarchical Characterization of Analog Integrated CMOS Circuits. 636-643 - Guido Dröge, Manfred Thole, Ernst-Helmut Horneber:
EASY - a System for Computer-Aided Examination of Analog Circuits. 644-648 - Lars Hedrich, Erich Barke:
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. 649-654
Benchmark Circuits, Technology Mapping and Scan Chains
- Debabrata Ghosh, Nevin Kapur, Franc Brglez, Justin E. Harlow III:
Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking. 656-663 - Aiguo Lu, Guenter Stenz, Frank M. Johannes:
Technology Mapping for Minimizing Gate and Routing Area. 664-669 - Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante:
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection. 670-677
Physical to Gate Level Design for Low-Power
- Jean Michel Daga, E. Ottaviano, Daniel Auvergne:
Temperature Effect on Delay for Low Voltage Applications. 680-685 - Qi Wang, Sarma B. K. Vrudhula:
Data Driven Power Optimization of Sequential Circuits. 686-691 - Jaewon Oh, Massoud Pedram:
Gated Clock Routing Minimizing the Switched Capacitance. 692-697 - Yi-Min Jiang, Kwang-Ting Cheng:
Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits. 698-702
Embedded Memory and Embedded Logic
- Norbert Wehn, Søren Hein:
Embedded DRAM Architectural Trade-Offs. 704-708 - Francky Catthoor:
Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology versus Design Methodology Solutions. 709-714
Analogue Circuit Modeling and Design Methodology
- Jan Vandenbussche, Stéphane Donnay, Francky Leyn, Georges G. E. Gielen, Willy M. C. Sansen:
Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon. 716-720 - Ralf Rosenberger, Sorin A. Huss:
A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks. 721-728 - Labros Bisdounis, Odysseas G. Koufopavlou, Constantinos E. Goutis, Spiridon Nikolaidis:
Switching Response Modeling of the CMOS Inverter for Sub-micron Devices. 729-735
Combinational Logical Synthesis
- David Ihsin Cheng:
On Removing Multiple Redundancies in Combinational Circuits. 738-742 - Christoph Scholl:
Multi-output Functional Decomposition with Exploitation of Don't Cares. 743-748 - J. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren:
An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization. 749-754 - Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya:
Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions. 755-759
High Level Power Estimation
- Fabrizio Ferrandi, Franco Fummi, Enrico Macii, Massimo Poncino:
Power Estimation of Behavioral Descriptions. 762-766 - Alessandro Bogliolo, Luca Benini, Giovanni De Micheli:
Characterization-Free Behavioral Power Modeling. 767-773 - Diana Marculescu, Radu Marculescu, Massoud Pedram:
Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation. 774-779
Petri Nets and Dedicated Formalisms
- Steven Vercauteren, Diederik Verkest, Gjalt G. de Jong, Bill Lin:
Efficient Verification using Generalized Partial Order Analysis. 782-789 - Enric Pastor, Jordi Cortadella:
Efficient Encoding Schemes for Symbolic Analysis of Petri Nets. 790-795 - Maroun Kassab, Eduard Cerny, Sidi Aourid, Thomas H. Krodel:
Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis. 796-802 - Evguenii I. Goldberg, Yuji Kukimoto, Robert K. Brayton:
Combinational Verification based on High-Level Functional Specifications. 803-808
Mixed-Signal Test and DFT
- Salvador Mir, Adoración Rueda, Diego Vázquez, José Luis Huertas:
Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems. 810-814 - Michel Renovell, Florence Azaïs, Yves Bertrand:
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. 815-821 - Walter M. Lindermeir, Thomas J. Vogels, Helmut E. Graeb:
Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults. 822-827
Sequential Logic Synthesis
- Olivier Coudert:
A New Paradigm for Dichotomy-based Constrained Encoding. 830-834 - Manuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas:
A Dynamic Model for the State Assignment Problem. 835-839 - Naresh Maheshwari, Sachin S. Sapatnekar:
Efficient Minarea Retiming of Large Level-Clocked Circuits. 840-845
High-Level Power Optimization
- Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits. 848-854 - Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura:
Instruction Scheduling for Power Reduction in Processor-Based System Design. 855-860 - Luca Benini, Giovanni De Micheli, Donatella Sciuto, Enrico Macii, Cristina Silvano:
Address Bus Encoding Techniques for System-Level Power Optimization. 861-866
System Architecture Design
- Michael Mrva, Klaus Buchenrieder, Rainer Kress:
A Scalable Architecture for Multi-threaded JAVA Applications. 868-874 - Valentina Salapura, Michael Gschwind:
Hardware/Software Co-Design of a Fuzzy RISC Processor. 875-882 - Kazushige Higuchi, Kazuhiro Shirakawa:
Innovative System-level Design Environment Based on FORM for Transport Processing System. 883-890
Simulation and Test Tools for Analogue Circuits
- João Paulo Costa, Mike Chou, L. Miguel Silveira:
Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's. 892-898 - Michael W. Tian, Chuanjin Richard Shi:
Efficient DC Fault Simulation of Nonlinear Analog Circuits. 899-904 - Juan A. Prieto, Adoración Rueda, Ian Andrew Grout, Eduardo J. Peralías, José L. Huertas, Andrew Mark David Richardson:
An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits. 905-909
Poster Session
- Ralf Niemann, Peter Marwedel:
Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems. 912-913 - Marisa Luisa López-Vallejo, Carlos Angel Iglesias, Juan Carlos López:
A Knowledge-based System for Hardware-Software Partitioning. 914-915 - Tom J. Kazmierski:
A Formal Description of VHDL-AMS Analogue Systems. 916-920 - Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, Laurent Volpe:
Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. 921-922 - Davor Runje, Mario Kovac:
Universal Strong Encryption FPGA Core Implementation. 923-924 - Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau:
Data Cache Sizing for Embedded Processor Applications. 925-926 - Jean Paul Calvez, Dominique Heller, F. Muller, Olivier Pasquier:
A Programmable Multi-Language Generator for CoDesign. 927-928 - Anupam Basu, Rainer Leupers, Peter Marwedel:
Register-Constrained Address Computation in DSP Programs. 929-930 - Thomas Müller-Wipperfürth, Richard Hagelauer:
Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base. 931-932 - George Economakos, George K. Papakonstantinou, Panayotis Tsanakas:
AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems. 933-934 - Serafín Olcoz, Ana Castellvi, Maria Garcia, Jose Angel Gomez:
Static Analysis Tools for Soft-Core Reviews and Audits. 935-936 - Michael G. Wahl, Holger Völkel:
A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor. 937-938 - Hans-Georg Martin, Wolfgang Rosenstiel:
A Comparing Study of Technology Mapping for FPGA. 939-940 - Tom J. Kazmierski:
Fuzzy-logic digital-analogue interfaces for accurate mixed-signal simulation. 941-944 - Wonyong Sung, Soonhoi Ha:
Optimized Timed Hardware Software Cosimulation without Roll-back. 945-946 - Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez:
A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design. 947-948 - Jie Gong, Chih-Tung Chen, Kayhan Küçükçakar:
Architectural Rule Checking for High-level Synthesis. 949-950 - Hideaki Kimura, Norihito Iyenaga:
A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator. 951-952 - Petra Nordholz, Hartmut Grabinski, Dieter Treytnar, Jan Otterstedt, Dirk Niggemeyer, Uwe Arz, T. W. Williams:
Core Interconnect Testing Hazards. 953-954 - Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda:
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. 955-956 - Cristiana Bolchini, Fabio Salice, Donatella Sciuto:
Fault Analysis in Networks with Concurrent Error Detection Properties. 957-958 - M. Svajda, B. Straka, Hans A. R. Manhaeve:
IOCIMU - An Integrated Off-Chip IDDQ Measurement Unit. 959-960 - Markus Wolf, Ulrich Kleine:
Automatic Topology Optimization for Analog Module Generators. 961-962 - Anatoly Prihozhy:
Asynchronous Scheduling and Allocation. 963-964 - Matthias Ringe, Thomas Lindenkreuz, Erich Barke:
Path Verification Using Boolean Satisfiability. 965-966 - Sumit Roy, Harm Arts, Prithviraj Banerjee:
PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions. 967-968 - Wolfgang Roethig, A. M. Zarkesh, M. Andrews:
Power and Timing Modeling for ASIC Designs. 969-970 - Bogdan G. Arsintescu, Ralph H. J. M. Otten:
Constraints Space Management for the Layout of Analog IC's. 971-972 - Irith Pomeranz, Sudhakar M. Reddy:
A Synthesis Procedure for Flexible Logic Functions. 973-974 - Felix Nicoli:
Denotational Semantics of a Behavioral Subset of VHDL. 975-976 - José M. Mendías, Román Hermida:
Correct High-Level Synthesis: a Formal Perspective. 977-978 - Mehrdad Nourani, Christos A. Papachristou:
A Bypass Scheme for Core-Based System Fault Testing. 979-980 - Cecilia Metra, Michele Favalli, Bruno Riccò:
Highly Testable and Compact 1-out-of-n Code Checker with Single Output. 981-982 - Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. 983-984 - Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija:
CMOS Combinational Circuit Sizing by Stage-wise Tapering. 985-986 - Jaime Velasco-Medina, Th. Calin, Michael Nicolaidis:
Fault Detection for Linear Analog Circuits Using Current Injection. 987-988
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