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ORCIDAbhijit Dharchoudhury
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1990 – 1999
- 1999
[c14]Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw:
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC 1999: 436-441- [c13]Savithri Sundareswaran, David T. Blaauw, Abhijit Dharchoudhury:
A Three-Tier Assertion Technique for Spice Verification of Transistor Level Timing Analysis. VLSI Design 1999: 175-180 - [r1]Steve M. Kang, Abhijit Dharchoudhury, David T. Blaauw, Stantanu Ganguly:
Timing and Signal Integrity Analysis. The VLSI Handbook 1999 - 1998
- [c12]Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw:
Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC 1998: 388-391 - [c11]Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden:
Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC 1998: 738-743 - [c10]Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija:
CMOS Combinational Circuit Sizing by Stage-wise Tapering. DATE 1998: 985-986 - [c9]David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards:
Emerging power management tools for processor design. ISLPED 1998: 143-148 - 1997
- [c8]Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw:
Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662 - [c7]Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning:
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD 1997: 143-148 - 1996
- [c6]Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang:
iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. DAC 1996: 548-551 - 1995
- [j1]Abhijit Dharchoudhury, Sung-Mo Kang:
Worst-case analysis and optimization of VLSI circuit performances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4): 481-492 (1995) - 1994
- [c5]Abhijit Dharchoudhury, Sung-Mo Kang, K. H. (Kane) Kim, S. H. Lee:
Fast and accurate timing simulation with regionwise quadratic models of MOS I-V characteristics. ICCAD 1994: 190-194 - [c4]Abhijit Dharchoudhury, Sung-Mo Kang, Hungse Cha, Janak H. Patel:
Fast timing simulation of transient faults in digital circuits. ICCAD 1994: 719-722 - 1993
- [c3]Abhijit Dharchoudhury, Sung-Mo Kang:
Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits. DAC 1993: 154-158 - 1992
- [c2]Abhijit Dharchoudhury, Sung-Mo Kang:
An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits. DAC 1992: 704-709 - [c1]Abhijit Dharchoudhury, S. M. Kang:
Identification of Correlated Device Model Parameter Values for Worst-Case Circuit Performance Analysis. VLSI Design 1992: 339-340
Coauthor Index
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