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Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing

Authors:

Supamas Sirichotiyakul,

Tim Edwards,

Chanhee Oh,

Jingyan Zuo,

Abhijit Dharchoudhury,

Rajendran Panda,

David BlaauwAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 436 - 441

https://doi.org/10.1145/309847.309975

Published: 01 June 1999 Publication History

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Cited By

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Nemati APeimani MMobayen SSayyedfattahi S(2023)Adaptive terminal sliding mode controller design for cyber‐physical systems under external disturbance and actuator cyber‐attackInternational Journal of Adaptive Control and Signal Processing10.1002/acs.357737:6(1369-1388)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1002/acs.3577
Chakraborty TKundu SAgrawal DShinde SMathews JJames RCoskun AMargala MBehjat LHan J(2016)Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent PathsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902991(365-368)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2902991
Elango VRastello FPouchet LRamanujam JSadayappan P(2015)On Characterizing the Data Access Complexity of ProgramsACM SIGPLAN Notices10.1145/2775051.267701050:1(567-580)Online publication date: 14-Jan-2015
https://dl.acm.org/doi/10.1145/2775051.2677010
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Index Terms

Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
1. Hardware
  1. Electronic design automation
    1. Logic synthesis
      1. Circuit optimization

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DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 01 June 1999

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DAC99

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DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

Louisiana, New Orleans, USA

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DAC '99 Paper Acceptance Rate 154 of 451 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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June 22 - 26, 2025

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Cited By

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Nemati APeimani MMobayen SSayyedfattahi S(2023)Adaptive terminal sliding mode controller design for cyber‐physical systems under external disturbance and actuator cyber‐attackInternational Journal of Adaptive Control and Signal Processing10.1002/acs.357737:6(1369-1388)Online publication date: 1-Jun-2023
https://dl.acm.org/doi/10.1002/acs.3577
Chakraborty TKundu SAgrawal DShinde SMathews JJames RCoskun AMargala MBehjat LHan J(2016)Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent PathsProceedings of the 26th edition on Great Lakes Symposium on VLSI10.1145/2902961.2902991(365-368)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2902961.2902991
Elango VRastello FPouchet LRamanujam JSadayappan P(2015)On Characterizing the Data Access Complexity of ProgramsACM SIGPLAN Notices10.1145/2775051.267701050:1(567-580)Online publication date: 14-Jan-2015
https://dl.acm.org/doi/10.1145/2775051.2677010
Bastani OAnand SAiken A(2015)Specification Inference Using Context-Free Language ReachabilityACM SIGPLAN Notices10.1145/2775051.267697750:1(553-566)Online publication date: 14-Jan-2015
https://dl.acm.org/doi/10.1145/2775051.2676977
Agten PJacobs BPiessens F(2015)Sound Modular Verification of C Code Executing in an Unverified ContextACM SIGPLAN Notices10.1145/2775051.267697250:1(581-594)Online publication date: 14-Jan-2015
https://dl.acm.org/doi/10.1145/2775051.2676972
Mok SLee JGupta P(2013)Discrete sizing for leakage power optimization in physical designACM Transactions on Design Automation of Electronic Systems10.1145/2390191.239020618:1(1-11)Online publication date: 16-Jan-2013
https://dl.acm.org/doi/10.1145/2390191.2390206
Chen YWang YXie YTakach A(2012)Parametric yield-driven resource binding in high-level synthesis with multi-Vth/Vdd library and device sizingJournal of Electrical and Computer Engineering10.1155/2012/1052502012(3-3)Online publication date: 1-Jan-2012
https://dl.acm.org/doi/10.1155/2012/105250
Ghosh NGhosh S(2012)A planner-based approach to generate and analyze minimal attack graphApplied Intelligence10.1007/s10489-010-0266-836:2(369-390)Online publication date: 1-Mar-2012
https://dl.acm.org/doi/10.1007/s10489-010-0266-8
Gu JQu GYuan LZhuo CPhillips JHu AGraeb H(2011)Improving dual V technology by simultaneous gate sizing and mechanical stress optimizationProceedings of the International Conference on Computer-Aided Design10.5555/2132325.2132485(732-735)Online publication date: 7-Nov-2011
https://dl.acm.org/doi/10.5555/2132325.2132485
Abrishami HLou JQin JFroessl JPedram MStok LDutt NHassoun S(2011)Post sign-off leakage power optimizationProceedings of the 48th Design Automation Conference10.1145/2024724.2024829(453-458)Online publication date: 5-Jun-2011
https://dl.acm.org/doi/10.1145/2024724.2024829
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Recommendations

Effectiveness of low power dual-V_t designs in nano-scale technologies under process parameter variations

A design of low swing and multi threshold voltage based low power 12T SRAM cell

Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era