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ORCIDParthasarathi Dasgupta
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2010 – 2019
- 2016
[j11]Sarit Chakraborty, Susanta Chakraborty, Chandan Das, Parthasarathi Dasgupta:
Efficient two phase heuristic routing technique for digital microfluidic biochip. IET Comput. Digit. Tech. 10(5): 233-242 (2016)- [j10]Pranab Roy
, Swati Saha, Hafizur Rahaman, Parthasarathi Dasgupta:
Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips. IEEE Trans. Very Large Scale Integr. Syst. 24(11): 3345-3358 (2016) - [c55]Subrata Das, Parthasarathi Dasgupta, Petr Fiser, Sudip Ghosh, Debesh Kumar Das:
A rule-based approach for minimizing power dissipation of digital circuits. DDECS 2016: 237-242 - [c54]Subrata Das, Soma Das, Adrija Majumder, Parthasarathi Dasgupta, Debesh Kumar Das:
Delay Estimates for Graphene Nanoribbons: A Novel Measure of Fidelity and Experiments with Global Routing Trees. ACM Great Lakes Symposium on VLSI 2016: 263-268 - [c53]Debasis Pal, Abir Pramanik, Parthasarathi Dasgupta, Debesh Kumar Das:
Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff. VDAT 2016: 1-6 - 2015
- [c52]Pranab Roy, Pampa Howladar, Raja Dastidar, Hafizur Rahaman, Parthasarathi Dasgupta:
3D integration in biochips: New proposed architectures for 3D applications in ATDA based digital microfluidic biochips. DTIS 2015: 1-6 - [c51]Sarit Chakraborty, Chandan Das, Susanta Chakraborty, Parthasarathi Dasgupta:
A novel two phase heuristic routing technique in digital microfluidic biochip. VDAT 2015: 1-6 - 2014
- [j9]Subrata Das, Satrajit Ghosh, Parthasarathi Dasgupta, Samar Sen-Sarma:
Algorithms for rotation symmetric Boolean functions. Int. J. Inf. Coding Theory 2(4): 238-265 (2014) - [c50]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips. DDECS 2014: 122-128 - [c49]Pranab Roy, Samadrita Bhattacharya, Hafizur Rahaman, Parthasarathi Dasgupta:
A new technique for layout based functional testing of modules in Digital Microfluidic Biochips. EWDTS 2014: 1-6 - [c48]Pranab Roy, Aatreyi Bal, Mahua Raha Patra, Hafizur Rahaman, Parthasarathi Dasgupta:
Automated two stage detection and analyzer system in multipartitioned Digital Microfluidic Biochips. ISCAS 2014: 1836-1840 - [c47]Pranab Roy, Tamosa Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta:
Multilevel Homogeneous Detection Analyzer for Medical Diagnostic Application in Digital Microfluidic Biochips. ISED 2014: 73-78 - [c46]Pranab Roy, Samadrita Bhattacharya, Rupam Bhattacharyay, Firdousi Jamil Imam, Hafizur Rahaman, Parthasarathi Dasgupta:
A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips. VLSID 2014: 510-515 - 2013
- [j8]Indrajit Pan, Ritwik Mukherjee, Hafizur Rahaman, Tuhina Samanta, Parthasarathi Dasgupta:
Optimization algorithms for the design of digital microfluidic biochips: A survey. Comput. Electr. Eng. 39(1): 112-121 (2013) - [c45]Divya Sharma, Akz Alam, Parthasarathi Dasgupta, Debashis Saha:
A ranking algorithm for online social network search. COMPUTE 2013: 17:1-17:7 - [c44]Pranab Roy, Pampa Howladar, Rupam Bhattacharjee, Hafizur Rahaman, Parthasarathi Dasgupta:
A new cross contamination aware routing method with intelligent path exploration in digital microfluidic biochips. DTIS 2013: 50-55 - [c43]Pranab Roy, Hafizur Rahaman, Partha Sarathi Gupta, Parthasarathi Dasgupta:
A new customized testing technique using a novel design of droplet motion detector for digital microfluidic Biochip systems. ICACCI 2013: 897-902 - [c42]Pranab Roy, Mahua Raha Patra, Hafizur Rahaman, Parthasarathi Dasgupta:
Novel designs of digital detection analyzer for intelligent detection and analysis in digital microfluidic biochips. IDT 2013: 1-6 - [c41]Pranab Roy, Mahua Raha Patra, Hafizur Rahaman, Parthasarathi Dasgupta:
Digital microfluidic system: A new design for heterogeneous sample based integration of multiple DMFBs. ISCAS 2013: 1905-1909 - [c40]Pranab Roy, Mahua Raha Patra, Hafizur Rahaman, Parthasarathi Dasgupta:
An Intelligent Biochip System for Diagnostic Process Flow Based Integration of Combined Detection Analyzer. ISED 2013: 108-112 - [c39]Pranab Roy, Samadrita Bhattacharya, Hafizur Rahaman, Parthasarathi Dasgupta:
A New Method for Route Based Synthesis and Placement in Digital Microfluidic Biochips. VDAT 2013: 361-375 - 2012
- [j7]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
Two-level clustering-based techniques for intelligent droplet routing in digital microfluidic biochips. Integr. 45(3): 316-330 (2012) - [c38]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta, Bhargab B. Bhattacharya:
A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips. Asian Test Symposium 2012: 25-30 - [c37]Pranab Roy, Rupam Bhattacharjee, Modud Sohid, Sudipta Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta:
An intelligent compaction technique for pin constrained routing in cross referencing digital microfluidic biochips. CODES+ISSS 2012: 423-432 - [c36]Pranab Roy, Moudud Sohid, Sudipta Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta:
System on Biochips: A New Design for Integration of Multiple DMFBs. ISED 2012: 256-260 - [c35]Pranab Roy, Rupam Bhattacharjee, Hafizur Rahaman, Parthasarathi Dasgupta:
A New Algorithm for Routing-Aware Net Placement in Cross-Referencing Digital Microfluidic Biochips. ISVLSI 2012: 320-325 - [c34]Pranab Roy, Sudipta Chakraborty, Moudud Sohid, Hafizur Rahaman, Parthasarathi Dasgupta:
A new digital analyzer for optically detected samples in Digital Microfluidic Biochips. MWSCAS 2012: 462-465 - [c33]Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
Partitioning-based wirelength estimation technique for Y-routing. SBCCI 2012: 1-6 - [c32]Tuhina Samanta, Raka Sardar, Hafizur Rahaman, Parthasarathi Dasgupta, Bhargab B. Bhattacharya:
A heuristic method for obstacle avoiding group Steiner tree construction. SLIP 2012: 21 - [c31]Subrata Das, Parthasarathi Dasgupta, Samar Sen-Sarma:
Arithmetic Algorithms for Ternary Number System. VDAT 2012: 111-120 - [c30]Partha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman, Parthasarathi Dasgupta:
Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor. VDAT 2012: 379-380 - [c29]Ritwik Mukherjee, Hafizur Rahaman, Indrajit Banerjee, Tuhina Samanta, Parthasarathi Dasgupta:
A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip. VLSI Design 2012: 227-232 - 2011
- [j6]Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
Near-optimal Y-routed delay trees in nanometric interconnect design. IET Comput. Digit. Tech. 5(1): 36-48 (2011) - [c28]Prasun Ghosal, Hafizur Rahaman, Satrajit Das, Arindam Das, Parthasarathi Dasgupta:
Obstacle Aware Routing in 3D Integrated Circuits. ADCONS 2011: 451-460 - [c27]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
A Multi-pin Droplet Routing Algorithm for Digital Microfluidic Biochips. BIODEVICES 2011: 216-223 - [c26]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
Fast high-performance algorithms for multi-pin droplet routing in digital microfluidic biochips. ACM Great Lakes Symposium on VLSI 2011: 229-234 - [c25]Pranab Roy, Hafizur Rahaman, Rupam Bhattacharya, Parthasarathi Dasgupta:
A Best Path Selection Based Parallel Router for DMFBs. ISED 2011: 176-181 - [c24]Indrajit Pan, Parthasarathi Dasgupta, Hafizur Rahaman, Tuhina Samanta:
Ant Colony Optimization Based Droplet Routing Technique in Digital Microfluidic Biochip. ISED 2011: 223-229 - [c23]Tuhina Samanta, Sanoara Khatun, Hafizur Rahaman, Parthasarathi Dasgupta:
Crosstalk aware coupled line delay tree construction for on-chip interconnects. ISQED 2011: 353-358 - [c22]Pranab Roy, Rajesh Mandal, Hafizur Rahaman, Parthasarathi Dasgupta:
A Group-Preferential Parallel-Routing Algorithm for Cross-Referencing Digital Microfluidic Biochips. ISVLSI 2011: 317-318 - 2010
- [c21]Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
Minimizing Thermal Disparities during Placement in 3D ICs. CSE 2010: 160-167 - [c20]Pranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta:
A novel droplet routing algorithm for digital microfluidic biochips. ACM Great Lakes Symposium on VLSI 2010: 441-446
2000 – 2009
- 2009
- [j5]Sriparna Saha, Susmita Sur-Kolay, Parthasarathi Dasgupta, Sanghamitra Bandyopadhyay:
MAkE: Multiobjective algorithm for k-way equipartitioning of a point set. Appl. Soft Comput. 9(2): 711-724 (2009) - [c19]Raju Halder, Parthasarathi Dasgupta, Saptarshi Naskar, Samar Sen-Sarma:
An internet-based IP protection scheme for circuit designs using linear feedback shift register (LFSR)-based locking. SBCCI 2009 - [c18]Tuhina Samanta, Hafizur Rahaman, Prasun Ghosal, Parthasarathi Dasgupta:
A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment. VLSI Design 2009: 387-392 - 2008
- [c17]Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations. ISVLSI 2008: 369-374 - [c16]Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
Revisiting fidelity: a case of elmore-based Y-routing trees. SLIP 2008: 27-34 - 2007
- [c15]Debasri Saha, Parthasarathi Dasgupta, Susmita Sur-Kolay, Samar Sen-Sarma:
A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection. ICCTA 2007: 111-116 - [c14]Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
Minimum-Congestion Placement for Y-interconnects: Some studies and observations. ISVLSI 2007: 73-80 - 2006
- [c13]Sriparna Saha, Susmita Sur-Kolay, Sanghamitra Bandyopadhyay, Parthasarathi Dasgupta:
Multiobjective Genetic Algorithm for k-way Equipartitioning of a Point Set with Application to CAD-VLSI. ICIT 2006: 281-284 - [c12]Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Parthasarathi Dasgupta:
A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI. ISCAS 2006 - [c11]Parthasarathi Dasgupta, Prashant Yadava:
Linear Required-Arrival-Time Trees and their Construction. VLSI Design 2006: 790-793 - 2005
- [c10]Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta:
Recent Trends in the Application of Meta-Heuristics to VLSI Layout Design. IICAI 2005: 232-251 - [c9]Parthasarathi Dasgupta:
Revisiting VLSI Interconnects in Deep Sub-Micron: Some Open Questions. VLSI Design 2005: 615-620 - 2004
- [c8]Susmita Sur-Kolay, Parthasarathi Dasgupta, Bhargab B. Bhattacharya, Sujit T. Zachariah:
Physical Design Trends and Layout-Based Fault Modeling. VLSI Design 2004: 6-8 - 2003
- [c7]Parthasarathi Dasgupta, Andrew B. Kahng, Swamy Muddu:
A Novel Metric for Interconnect Architecture Performance. DATE 2003: 10448-10455 - [c6]Parthasarathi Dasgupta:
Range-Based Discrepancy Search with Applications to VLSI Design. IICAI 2003: 621-631 - 2002
- [j4]Parthasarathi Dasgupta, Peichen Pan, Subhas C. Nandy, Bhargab B. Bhattacharya:
Monotone bipartitioning problem in a planar point set with applications to VLSI. ACM Trans. Design Autom. Electr. Syst. 7(2): 231-248 (2002) - 2001
- [j3]Parthasarathi Dasgupta, Susmita Sur-Kolay:
Slicible rectangular graphs and their optimal floorplans. ACM Trans. Design Autom. Electr. Syst. 6(4): 447-470 (2001) - [j2]Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya:
Searching networks with unrestricted edge costs. IEEE Trans. Syst. Man Cybern. Part A 31(6): 497-507 (2001) - [c5]Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta:
Partitioning Routing Area into Zones with Distinct Pins. VLSI Design 2001: 345-
1990 – 1999
- 1998
- [j1]Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
A unified approach to topology generation and optimal sizing of floorplans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2): 126-135 (1998) - 1997
- [c4]Parthasarathi Dasgupta, Susmita Sur-Kolay:
Slicibility of rectangular graphs and floorplan optimization. ISPD 1997: 150-155 - 1996
- [c3]Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya:
Geometric bipartitioning problem and its applications to VLSI. VLSI Design 1996: 400-405 - 1995
- [c2]Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
A unified approach to topology generation and area optimization of general floorplans. ICCAD 1995: 712-715 - [c1]P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya:
VLSI floorplan generation and area optimization using AND-OR graph search. VLSI Design 1995: 370-375
Coauthor Index
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