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ORCIDITC 2023: Anaheim, CA, USA
- IEEE International Test Conference, ITC 2023, Anaheim, CA, USA, October 7-15, 2023. IEEE 2023, ISBN 979-8-3503-4325-0
- Li-C. Wang, Jeff Rearick:
Welcome Message ITC 2023. xiii - Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima, Oussama Laouamri, Naveen Khanna, Jeff Mayer, Nilanjan Mukherjee:
A New Framework for RTL Test Points Insertion Facilitating a "Shift-Left DFT" Strategy. 1-10 - Anshuman Chandra, Moiz Khan, Ankita Patidar, Fumiaki Takashima, Sandeep Kumar Goel, Bharath Shankaranarayanan, Vuong Nguyen, Vistrita Tyagi, Manish Arora:
A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation. 11-20 - Aswin R:
New Algorithm for Fast and Accurate Linearity Testing of High-Resolution SAR ADCs. 21-29 - Ferhat Can Ataman, Y. B. Chethan Kumar, Sandeep Rao, Sule Ozev:
Improving Angle of Arrival Estimation Accuracy for mm-Wave Radars. 30-36 - Suhasini Komarraju, Akhil Tammana, Chandramouli N. Amarnath, Abhijit Chatterjee:
OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems. 37-46 - Keno Sato, Takayuki Nakatani, Takashi Ishida, Toshiyuki Okamoto, Tamotsu Ichikawa, Shogo Katayama, Daisuke Iimori, Misaki Takagi, Yujie Zhao, Shuhei Yamamoto, Anna Kuwana, Kentaroh Katoh, Kazumi Hatayama, Haruo Kobayashi:
Low Distortion Sinusoidal Signal Generator with Harmonics Cancellation Using Two Types of Digital Predistortion. 47-55 - Arani Sinha, Glenn Colón-Bonet, Michael Fahy, Pankaj Pant, Haijing Mao, Akhilesh Shukla:
Maximizing Stress Coverage by Novel DFT Techniques and Relaxed Timing Closure. 56-59 - Sudhakar Kongala, Anuj Gupta, Yash Walia, Sahil Jain:
Novel Methodology to Optimize TAT and Resource Utilization for ATPG Simulations for Large SoCs. 60-64 - Szczepan Urban, Piotr Zimnowlodzki, Manish Sharma, Shraddha Bodhe, John Schulze, Abdullah Yassine, Adam Styblinski:
Global Control Signal Defect Diagnosis in Volume Production Environment. 65-70 - Seongkwan Lee, Jun Yeon Won, Cheolmin Park, Minho Kang, Jaemoo Choi:
Method for Diagnosing Channel Damage Using FPGA Transceiver. 71-76 - Seongkwan Lee, Minho Kang, Cheolmin Park, Jun Yeon Won, Jaemoo Choi:
Method for Adjusting Termination Resistance Using PMU in DC Test. 77-81 - Cyrille Dray, Khushal Gelda, Benoit Nadeau-Dostie, Wei Zou, Luc Romain, Jongsin Yun, Harshitha Kodali, Lori Schramm, Martin Keim:
Transitioning eMRAM from Pilot Project to Volume Production. 82-86 - Daehyun Chang, Youngdae Kim, Suksoo Pyo, Shin Hun, Daesop Lee, Sohee Hwang, Jaesik Choi, Siwoong Kim:
Algorithmic Read Resistance Trim for Improving Yield and Reducing Test Time in MRAM. 87-92 - Nadun Sinhabahu, Katherine Shu-Min Li, Sying-Jyan Wang, J. R. Wang, Matt Ho:
Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing. 93-98 - Yuxuan Yin, Rebecca Chen, Chen He, Peng Li:
Domain-Specific Machine Learning Based Minimum Operating Voltage Prediction Using On-Chip Monitor Data. 99-104 - Irith Pomeranz:
Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation Lines. 105-110 - Hanieh Jafarzadeh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi-Haghi, Hussam Amrouch, Sybille Hellebrand, Hans-Joachim Wunderlich:
Robust Pattern Generation for Small Delay Faults Under Process Variations. 111-116 - Yinxuan Lyu, Liangliang Yu, Pengju Li, Junlin Huang:
Logic Test Vehicles for High Resolution Diagnosis of Systematic FEOL/MEOL Yield Detractors. 117-121 - Matthew Dupree, Min Jian Yang, Yueling Jenny Zeng, Li-C. Wang:
IEA-Plot: Conducting Wafer-Based Data Analytics Through Chat. 122-131 - Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Takashi Sato
, Michihiro Shintani:
Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning. 132-140 - Zihu Wang, Hanbin Hu, Chen He, Peng Li:
Recognizing Wafer Map Patterns Using Semi-Supervised Contrastive Learning with Optimized Latent Representation Learning and Data Augmentation. 141-150 - Francesco Lorenzelli, Asser Elsayed, Clement Godfrin, Alexander Grill, Stefan Kubicek, Ruoyu Li, Michele Stucchi, Danny Wan, Kristiaan De Greve, Erik Jan Marinissen, Georges G. E. Gielen:
Wafer-Scale Electrical Characterization of Silicon Quantum Dots from Room to Low Temperatures. 151-158 - Huaxiao Liang, Xiaoze Lin, Liyang Lai, Naixing Wang, Yu Huang, Fei Yang, Yuxin Yang:
GPU-Based Concurrent Static Learning. 159-165 - Navajit Singh Baban, Ajymurat Orozaliev, Yong-Ak Song, Urbi Chatterjee, Sankalp Bose, Sukanta Bhattacharjee, Ramesh Karri, Krishnendu Chakrabarty:
Biochip-PUF: Physically Unclonable Function for Microfluidic Biochips. 166-175 - Fernando Fernandes dos Santos, Luigi Carro, Paolo Rech:
Understanding and Improving GPUs' Reliability Combining Beam Experiments with Fault Simulation. 176-185 - Anuj Dubey, Aydin Aysu:
A Full-Stack Approach for Side-Channel Secure ML Hardware. 186-195 - Yu Li, Qiang Xu:
Towards Robust Deep Neural Networks Against Design-Time and Run-Time Failures. 196-205 - Zhe-Jia Liang, Yu-Tsung Wu, Yun-Feng Yang, James Chien-Mo Li, Norman Chang, Akhilesh Kumar, Ying-Shiun Li:
High-Speed, Low-Storage Power and Thermal Predictions for ATPG Test Patterns. 206-215 - Shao-Chun Hung, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty:
Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs. 216-225 - Yunfei Gu, Xingyu Wang, Zixiao Chen, Chentao Wu, Xinfei Guo, Jie Li, Minyi Guo, Song Wu, Rong Yuan, Taile Zhang, Yawen Zhang, Haoran Cai:
Improving Productivity and Efficiency of SSD Manufacturing Self-Test Process by Learning-Based Proactive Defect Prediction. 226-235 - Sicong Yuan, Z. Zhang, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, M. Taouil, Said Hamdioui:
Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs. 236-245 - Hanzhi Xun, Sicong Yuan, Moritz Fieback, Hassen Aziza, Mottaqiallah Taouil, Said Hamdioui:
Device-Aware Test for Ion Depletion Defects in RRAMs. 246-255 - Dhruv Thapar, Simon Thomann, Arjun Chaudhuri, Hussam Amrouch, Krishnendu Chakrabarty:
Analysis and Characterization of Defects in FeFETs. 256-265 - Ayush Arunachalam, Sanjay Das, Monikka Rajan, Fei Su, Xiankun Jin, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu:
Enhanced ML-Based Approach for Functional Safety Improvement in Automotive AMS Circuits. 266-275 - Sam M.-H. Hsiao, Amy H.-Y. Tsai, Lowry P.-T. Wang, Aaron C.-W. Liang, Charles H.-P. Wen, Herming Chiueh:
Preventing Single-Event Double-Node Upsets by Engineering Change Order in Latch Designs. 276-285 - Saidapet Ramesh, Rahul Kalyan, Jesse Yanez, Andreas Glowatz, Maija Ryynänen, Sergej Schwarz:
Measuring Non-Redundant VIA Test-Coverage for Automotive Designs in Lower Process Nodes. 286-292 - Bing-Han Hsieh, Yun-Sheng Liu, James Chien-Mo Li, Chris Nigh, Mason Chern, Gaurav Bhargava:
Diagnosis of Systematic Delay Failures Through Subset Relationship Analysis. 293-302 - Manoj Devendhiran, Jakub Janicki, Szczepan Urban, Manish Sharma, Jayant D'Souza:
Predicting the Resolution of Scan Diagnosis. 303-309 - J. Lefevre, P. Debaud, Patrick Girard, Arnaud Virazel:
Predictor BIST: An "All-in-One" Optical Test Solution for CMOS Image Sensors. 310-319 - Rasheed Kibria, Farimah Farahmandi, Mark M. Tehranipoor:
ARC-FSM-G: Automatic Security Rule Checking for Finite State Machine at the Netlist Abstraction. 320-329 - Ryan Holzhausen, Tasnuva Farheen, Morgan Thomas, Nima Maghari, Domenic Forte:
Laser Fault Injection Vulnerability Assessment and Mitigation with Case Study on PG-TVD Logic Cells. 330-339 - Eduardo Ortega, Tyler K. Bletsch, Biresh Kumar Joardar, Jonti Talukdar, Woohyun Paik, Krishnendu Chakrabarty:
Simply-Track-and-Refresh: Efficient and Scalable Rowhammer Mitigation. 340-349 - Bharath Nandakumar, Sameer Chillarige:
Low cost production scan chain test for compression based designs. 350-356 - Ching-Min Liu, Chia-Heng Yen, Shu-Wen Lee, Kai-Chiang Wu, Mango Chia-Tso Chao:
Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information. 357-366 - Seyedeh Maryam Ghasemi, Sergej Meschkov, Jonas Krautter, Dennis R. E. Gnad, Mehdi B. Tahoori:
Enabling In-Field Parametric Testing for RISC-V Cores. 367-376 - Dimitris Gizopoulos, George Papadimitriou, Odysseas Chatzopoulos:
Estimating the Failures and Silent Errors Rates of CPUs Across ISAs and Microarchitectures. 377-382 - Costas Argyrides, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
Utilizing ECC Analytics to Improve Memory Lifecycle Management. 383-387 - Kranthi Kandula, Ramalingam Kolisetti, Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian:
SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor. 388-392
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