default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID8th SLIP 2006: Munich, Germany
- Mike Hutton, Joni Dambre:
The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings. ACM 2006, ISBN 1-59593-255-0
Prediction of individual wire properties
- Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh
, Stephen Dean Brown:
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. 3-8 - Pranav Anbalagan, Jeffrey A. Davis:
A priori prediction of tightly clustered connections based on heuristic classification trees. 9-15 - Andrew B. Kahng, Sherief Reda:
A tale of two nets: studies of wirelength progression in physical design. 17-24
Process variation
- Louis Scheffer:
An overview of on-chip interconnect variation. 27-28 - Andrew B. Kahng, Rasit Onur Topaloglu:
Generation of design guarantees for interconnect matching. 29-34
Design for manufacturability
- Chandu Visweswariah:
Statistical analysis and optimization in the presence of gate and interconnect delay variations. 37
Evaluation and prediction of FPGA routing resources
- Wenyi Feng, Jonathan W. Greene:
Post-placement interconnect entropy: how many configuration bits does a programmable logic device need? 41-48 - Manuel Saldaña, Lesley Shannon, Paul Chow:
The routability of multiprocessor network topologies in FPGAs. 49-56
Prediction and Optimization of global interconnect architectures
- Wim Heirman, Joni Dambre, Jan M. Van Campenhout:
Congestion modeling for reconfigurable inter-processor networks. 59-66 - Young-Sin Cho, Eun-Ju Choi, Kyoung-Rok Cho:
Modeling and analysis of the system bus latency on the SoC platform. 67-74 - Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor:
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture. 75-81
Physical interconnect analysis and optimization
- Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex:
Impact of interconnect resistance increase on system performance of low power and high performance designs. 85-90 - Andrew B. Kahng, Bao Liu, Xu Xu:
Statistical crosstalk aggressor alignment aware interconnect delay calculation. 91-97 - J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne:
Constant impedance scaling paradigm for interconnect synthesis. 99-105
Optimal interconnect buffering
- Prashant Saxena:
The scaling of interconnect buffer needs. 109-112 - Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen:
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. 113-120
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-10-18 19:16 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
