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ORCIDMike Hutton
Person information
- affiliation: Altera Corp., San Jose, USA
- affiliation: University of Toronto, Department of Computer Science
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2020 – today
- 2023
[c34]Yi He
, Mike Hutton, Steven Chan, Robert De Gruijl, Rama Govindaraju, Nishant Patil, Yanjing Li:
Understanding and Mitigating Hardware Failures in Deep Learning Training Systems. ISCA 2023: 70:1-70:16
2010 – 2019
- 2017
- [j8]Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang:
The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. 10(2): 15:1-15:17 (2017) - 2015
- [c33]Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang:
Arria™ 10 device architecture. CICC 2015: 1-8 - [c32]Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang:
Significant papers from the first 25 years of the FPL conference. FPL 2015: 1-3 - [c31]Mike Hutton:
Stratix® 10: 14nm FPGA delivering 1GHz. Hot Chips Symposium 2015: 1-24 - 2014
- [c30]Brad Vest, Sean Atsatt, Mike Hutton:
Design of a high-density SoC FPGA at 20nm. Hot Chips Symposium 2014: 1-24
2000 – 2009
- 2009
- [p1]Mike Hutton, Vaughn Betz:
FPGA Synthesis and Physical Design. Embedded Systems Design and Verification 2009: 17 - 2008
- [j7]André DeHon, Mike Hutton:
Guest Editorial: TRETS Special Edition on the 15th International Symposium on FPGAs. ACM Trans. Reconfigurable Technol. Syst. 1(1): 2:1-2:3 (2008) - [j6]Yan Lin, Lei He, Mike Hutton:
Stochastic Physical Synthesis Considering Prerouting Interconnect Uncertainty and Process Variation for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 124-133 (2008) - [e4]Mike Hutton, Paul Chow:
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008. ACM 2008, ISBN 978-1-59593-934-0 [contents] - 2007
- [j5]Yan Lin, Mike Hutton, Lei He:
Statistical placement for FPGAs considering. IET Comput. Digit. Tech. 1(4): 267-275 (2007) - [j4]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng:
Efficient Timing Analysis With Known False Paths Using Biclique Covering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 959-969 (2007) - [c29]Paul Chow, Mike Hutton:
Integrating FPGAs in high-performance computing: introduction. FPGA 2007: 131 - [c28]Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam:
Equivalence Verification of FPGA and Structured ASIC Implementations. FPL 2007: 423-428 - [c27]Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic:
An FPGA Based Memory Efficient Shared Buffer Implementation. FPL 2007: 661-664 - [c26]Lei Cheng, Deming Chen, Martin D. F. Wong, Mike Hutton, Jason Govig:
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains. ICCAD 2007: 370-375 - [c25]Jun Mu, Sakir Sezer, Gareth Douglas, Dwayne Burns, Emi Garcia, Mike Hutton, Kevin Cackovic:
Accelerating pattern matching for DPI. SoCC 2007: 83-86 - [e3]André DeHon, Mike Hutton:
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, FPGA 2007, Monterey, California, USA, February 18-20, 2007. ACM 2007, ISBN 978-1-59593-600-4 [contents] - 2006
- [c24]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton:
Efficient static timing analysis using a unified framework for false paths and multi-cycle paths. ASP-DAC 2006: 73-78 - [c23]Michael D. Hutton, Richard Yuan, Jay Schleicher, Gregg Baeckler, Sammy Cheung, Kar Keng Chua, Hee Kong Phoo:
A methodology for FPGA to structured-ASIC synthesis and verification. DATE Designers' Forum 2006: 64-69 - [c22]Lerong Cheng, Jinjun Xiong, Lei He, Mike Hutton:
FPGA Performance Optimization Via Chipwise Placement Considering Process Variations. FPL 2006: 1-6 - [c21]Mike Hutton:
FPGA Architecture Design Methodology. FPL 2006: 1 - [c20]Mike Hutton, Yan Lin, Lei He:
Placement and Timing for FPGAs Considering Variations. FPL 2006: 1-7 - [c19]Shuo Zhou, Yi Zhu, Yuanfang Hu, Ronald L. Graham, Mike Hutton, Chung-Kuan Cheng:
Timing model reduction for hierarchical timing analysis. ICCAD 2006: 415-422 - [e2]Mike Hutton, Joni Dambre:
The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings. ACM 2006, ISBN 1-59593-255-0 [contents] - 2005
- [c18]David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose:
The Stratix II logic and routing architecture. FPGA 2005: 14-20 - [c17]Mike Hutton, David Karchmer, Bryan Archell, Jason Govig:
Efficient static timing analysis and applications using edge masks. FPGA 2005: 174-183 - [c16]Boris Ratchev, Mike Hutton, David Mendel:
Coping With Uncertainty in FPGA Architecture Design. FPL 2005: 662-665 - [c15]Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris:
Improving the efficiency of static timing analysis with false paths. ICCAD 2005: 527-531 - [c14]Lei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton:
Challenges and opportunities for low power FPGAs in nanometer technologies. ISLPED 2005: 90 - [e1]Igor L. Markov, Mike Hutton:
The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings. ACM 2005, ISBN 1-59593-033-7 [contents] - 2004
- [c13]Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis:
MAX II: A low-cost, high-performance LUT-based CPLD. CICC 2004: 443-446 - [c12]Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini:
Improving FPGA Performance and Area Using an Adaptive Logic Module. FPL 2004: 135-144 - [c11]Mike Hutton:
Architecture and CAD for FPGAs. SBCCI 2004: 3 - [c10]Mike Hutton:
Advances and trends in FPGA design. SBCCI 2004: 8 - 2003
- [c9]Joachim Pistorius, Mike Hutton:
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation. SLIP 2003: 31-38 - 2002
- [j3]Michael D. Hutton, Jonathan Rose, Derek G. Corneil:
Automatic generation of synthetic sequential benchmark circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8): 928-940 (2002) - [c8]Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev:
Interconnect enhancements for a high-speed PLD architecture. FPGA 2002: 3-10 - 2001
- [c7]Michael D. Hutton:
Interconnect prediction for programmable logic devices. SLIP 2001: 125-131
1990 – 1999
- 1999
- [c6]Michael D. Hutton, Jonathan Rose:
Equivalence classes of clone circuits for physical-design benchmarking. ISCAS (6) 1999: 428-431 - [c5]Michael D. Hutton, Jonathan Rose:
Applications of clone circuits to issues in physical-design. ISCAS (6) 1999: 448-451 - 1998
- [j2]Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil:
Characterization and parameterized generation of synthetic combinational benchmark circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 985-996 (1998) - 1997
- [b1]Mike Hutton:
Characterization and parameterized generation of digital circuits. University of Toronto, Canada, 1997 - [c4]Michael D. Hutton, Jonathan Rose, Derek G. Corneil:
Generation of Synthetic Sequential Benchmark Circuits. FPGA 1997: 149-155 - 1996
- [j1]Michael D. Hutton, Anna Lubiw:
Upward Planning of Single-Source Acyclic Digraphs. SIAM J. Comput. 25(2): 291-311 (1996) - [c3]Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil:
Characterization and Parameterized Random Generation of Digital Circuits. DAC 1996: 94-99 - 1991
- [c2]Michael D. Hutton, Anna Lubiw:
Upward Planar Drawing of Single Source Acyclic Digraphs. Planar Graphs 1991: 41-57 - [c1]Michael D. Hutton, Anna Lubiw:
Upward Planar Drawing of Single Source Acyclic Digraphs. SODA 1991: 203-211
Coauthor Index
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