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Characterization and parameterized random generation of digital circuits

Authors:

Michael Hutton,

J. P. Grossman,

Jonathan Rose, and

Derek CorneilAuthors Info & Claims

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

Pages 94 - 99

https://doi.org/10.1145/240518.240537

Published: 01 June 1996 Publication History

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References

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Cited By

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Amir SForte DXie Y(2020)Adaptable and divergent synthetic benchmark generation for hardware securityProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415648(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415648
Józwiak L(2008)Benchmarking in digital circuit designProceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics10.5555/1415563.1415577(58-66)Online publication date: 27-May-2008
https://dl.acm.org/doi/10.5555/1415563.1415577
Schmit H(2005)Extra-dimensional Island-Style FPGAsNew Algorithms, Architectures and Applications for Reconfigurable Computing10.1007/1-4020-3128-9_1(3-13)Online publication date: 2005
https://doi.org/10.1007/1-4020-3128-9_1
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Index Terms

Characterization and parameterized random generation of digital circuits
1. Hardware
  1. Emerging technologies
  2. Very large scale integration design

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Published In

DAC '96: Proceedings of the 33rd annual Design Automation Conference

June 1996

839 pages

ISBN:0897917790

DOI:10.1145/240518

Chairmen:
Thomas P. Pennino
Bell Labs, Holmdel, NJ
,
Ellen J. Yoffa
IBM Corp., Yorktown Heights, NY

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 01 June 1996

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DAC96: The 33rd Design Automation Conference

June 3 - 7, 1996

Nevada, Las Vegas, USA

Acceptance Rates

DAC '96 Paper Acceptance Rate 142 of 377 submissions, 38%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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62nd ACM/IEEE Design Automation Conference

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Amir SForte DXie Y(2020)Adaptable and divergent synthetic benchmark generation for hardware securityProceedings of the 39th International Conference on Computer-Aided Design10.1145/3400302.3415648(1-9)Online publication date: 2-Nov-2020
https://dl.acm.org/doi/10.1145/3400302.3415648
Józwiak L(2008)Benchmarking in digital circuit designProceedings of the 7th WSEAS International Conference on Microelectronics, Nanoelectronics, Optoelectronics10.5555/1415563.1415577(58-66)Online publication date: 27-May-2008
https://dl.acm.org/doi/10.5555/1415563.1415577
Schmit H(2005)Extra-dimensional Island-Style FPGAsNew Algorithms, Architectures and Applications for Reconfigurable Computing10.1007/1-4020-3128-9_1(3-13)Online publication date: 2005
https://doi.org/10.1007/1-4020-3128-9_1
Cong JRomesis MXie M(2003)Optimality and Stability Study of Timing-Driven Placement AlgorithmsProceedings of the 2003 IEEE/ACM international conference on Computer-aided design10.5555/996070.1009932Online publication date: 9-Nov-2003
https://dl.acm.org/doi/10.5555/996070.1009932
Balachandran SBhatia DSylvester DStroobandt DScheffer LZarkesh-Ha P(2003)A-priori wirelength and interconnect estimation based on circuit characteristicsProceedings of the 2003 international workshop on System-level interconnect prediction10.1145/639929.639945(77-84)Online publication date: 5-Apr-2003
https://dl.acm.org/doi/10.1145/639929.639945
Schmit H(2003)Extra-dimensional Island-Style FPGAsField Programmable Logic and Application10.1007/978-3-540-45234-8_40(406-415)Online publication date: 2003
https://doi.org/10.1007/978-3-540-45234-8_40
Caldwell AKahng AMarkov I(2002)Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist PartitioningAlgorithm Engineering and Experimentation10.1007/3-540-48518-X_11(182-198)Online publication date: 19-Apr-2002
https://doi.org/10.1007/3-540-48518-X_11
Jain SKumar AKumar S(2002)Efficient Embedding of Partitioned Circuits onto Multi-FPGA BoardsField-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing10.1007/3-540-44614-1_23(201-210)Online publication date: 12-Apr-2002
https://doi.org/10.1007/3-540-44614-1_23
Cadambi SGoldstein S(2001)Static Profile-Driven Compilation for FPGAsField-Programmable Logic and Applications10.1007/3-540-44687-7_12(112-122)Online publication date: 17-Aug-2001
https://doi.org/10.1007/3-540-44687-7_12
Inacio CSchmit HNagle DRyan AThomas DTong YKlass B(1999)Vertical benchmarks for CADProceedings of the 36th annual ACM/IEEE Design Automation Conference10.1145/309847.309969(408-413)Online publication date: 1-Jun-1999
https://dl.acm.org/doi/10.1145/309847.309969
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Characterization and parameterized generation of digital circuits

Parameterized Random Complexity

Forecasting the efficiency of test generation algorithms for digital circuits

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Characterization and parameterized generation of digital circuits

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Forecasting the efficiency of test generation algorithms for digital circuits

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