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2020 – today
- 2022
[c47]Junning Fan, Oliver Diessel:
On the Single Event Upset Vulnerability and Mitigation of Binarized Neural Networks on FPGAs. FCCM 2022: 1- [c46]Tong Wu, Oliver Diessel:
Leveraging FPGA Runtime Reconfigurability to Implement Multi-Hash-Chain Proof-of-Work. FCCM 2022: 1-5
2010 – 2019
- 2019
- [j14]Nguyen Tran Huu Nguyen
, Ediz Cetin, Oliver Diessel:
Scheduling configuration memory error checks to improve the reliability of FPGA-based systems. IET Comput. Digit. Tech. 13(3): 154-165 (2019) - [j13]Alexander Kroh, Oliver Diessel:
Efficient Fine-grained Processor-logic Interactions on the Cache-coherent Zynq Platform. ACM Trans. Reconfigurable Technol. Syst. 11(4): 25:1-25:22 (2019) - [c45]Fernanda Lima, Oliver Diessel:
Introduction to RAW 2019. IPDPS Workshops 2019: 69 - 2018
- [j12]Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, Lingkan Gong:
Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery. Microprocess. Microsystems 60: 86-95 (2018) - [j11]Dimitris Agiakatsikas, Ediz Cetin, Oliver Diessel:
FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs. IEEE Trans. Aerosp. Electron. Syst. 54(6): 2695-2712 (2018) - [j10]Ganghee Lee, Ediz Cetin, Oliver Diessel:
Fault Recovery Time Analysis for Coarse-Grained Reconfigurable Architectures. ACM Trans. Embed. Comput. Syst. 17(2): 42:1-42:21 (2018) - [j9]Zhuoran Zhao, Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Ganghee Lee, Ediz Cetin, Oliver Diessel:
Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems. ACM Trans. Reconfigurable Technol. Syst. 11(1): 4:1-4:23 (2018) - [c44]Dimitris Agiakatsikas, Ganghee Lee, Thomas Mitchell, Ediz Cetin, Oliver Diessel:
From C to Fault-Tolerant FPGA-Based Systems. FCCM 2018: 212 - [c43]Alexander Kroh, Oliver Diessel:
A Short-Transfer Model for Tightly-Coupled CPU-FPGA Platforms. FPT 2018: 366-369 - 2017
- [j8]Chao Wang, Xi Li, Yunji Chen, Youhui Zhang, Oliver Diessel, Xuehai Zhou:
Service-Oriented Architecture on FPGA-Based MPSoC. IEEE Trans. Parallel Distributed Syst. 28(10): 2993-3006 (2017) - [j7]Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang:
The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. 10(2): 15:1-15:17 (2017) - [c42]Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel:
Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems. DFT 2017: 1-4 - [c41]Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel:
Scheduling Considerations for Voter Checking in TMR-MER Systems. FCCM 2017: 30 - [c40]Ganghee Lee, Dimitris Agiakatsikas, Tong Wu, Ediz Cetin, Oliver Diessel:
TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS. FCCM 2017: 129-132 - [c39]Lingkan Gong, Alexander Kroh, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel:
Reliable SEU monitoring and recovery using a programmable configuration controller. FPL 2017: 1-6 - 2016
- [c38]Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, Lingkan Gong:
Reconfiguration Control Networks for TMR Systems with Module-Based Recovery. FCCM 2016: 88-91 - [c37]Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel:
FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs. FPL 2016: 1-4 - [c36]Zhuoran Zhao, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Çetin, Oliver Diessel:
Fine-grained module-based error recovery in FPGA-based TMR systems. FPT 2016: 101-108 - [c35]Lingkan Gong, Tong Wu, Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Zhuoran Zhao, Ediz Cetin, Oliver Diessel:
A Programmable Configuration Controller for fault-tolerant applications. FPT 2016: 117-124 - [c34]Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel:
Dynamic scheduling of voter checks in FPGA-based TMR systems. FPT 2016: 169-172 - 2015
- [c33]Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang:
Significant papers from the first 25 years of the FPL conference. FPL 2015: 1-3 - [c32]Vinh T. Tran, Nagaraj Channarayapatna Shivaramaiah, Oliver Diessel, Andrew G. Dempster:
A programmable multi-GNSS baseband receiver. ISCAS 2015: 1178-1181 - [c31]Ediz Cetin, Oliver Diessel, Lingkan Gong:
Improving Fmax of FPGA circuits employing DPR to recover from configuration memory upsets. ISCAS 2015: 1190-1193 - 2014
- [j6]Lingkan Gong, Oliver Diessel:
Simulation-based functional verification of dynamically reconfigurable systems. ACM Trans. Embed. Comput. Syst. 13(4): 97:1-97:23 (2014) - [c30]Ediz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai:
Reconfiguration network design for SEU recovery in FPGAs. ISCAS 2014: 1524-1527 - 2013
- [c29]Ediz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai:
Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. FPL 2013: 1-4 - [c28]Lingkan Gong, Oliver Diessel, Johny Paul, Walter Stechele:
RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study. IPDPS Workshops 2013: 106-113 - 2012
- [j5]Lesley Shannon, Oliver Diessel, Neil W. Bergmann:
Guest Editorial: Field-Programmable Technology. J. Signal Process. Syst. 67(1): 1-2 (2012) - [c27]Lingkan Gong, Oliver Diessel:
Functionally verifying state saving and restoration in dynamically reconfigurable systems. FPGA 2012: 241-244 - 2011
- [c26]Lingkan Gong, Oliver Diessel:
Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification. FCCM 2011: 9-16 - [c25]Lingkan Gong, Oliver Diessel:
ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration. FPT 2011: 1-8 - 2010
- [j4]Shannon Koh, Oliver Diessel:
Configuration Merging in Point-to-Point Networks for Module-Based FPGA Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. 3(1): 4:1-4:36 (2010) - [c24]Benjamin Kwek, Freddie Sunarso, Melissa Teoh, Arrian van Zal, Philip Preston, Oliver Diessel:
FPGA-based video processing for a vision prosthesis. FPT 2010: 345-348 - [i2]Branislav Hredzak, Oliver Diessel:
Towards Dilated Placement of Dynamic NoC Cores. Dynamically Reconfigurable Architectures 2010
2000 – 2009
- 2009
- [e2]Neil W. Bergmann, Oliver Diessel, Lesley Shannon:
Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, December 9-11, 2009. IEEE Computer Society 2009, ISBN 978-1-4244-4377-2 [contents] - 2008
- [c23]Shannon Koh, Oliver Diessel:
The Effectiveness of Configuration Merging in Point-to-Point Networks for Module-based FPGA Reconfiguration. FCCM 2008: 65-76 - [c22]Jenny Yi-Chun Kuo, Anderson Kuei-An Ku, Jingling Xue, Oliver Diessel, Usama Malik:
ACS: An Addressless Configuration Support for efficient partial reconfigurations. FPT 2008: 161-168 - 2007
- [c21]Shannon Koh, Oliver Diessel:
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices. FPL 2007: 293-298 - 2006
- [c20]Lih Wen Koh, Oliver Diessel:
Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays. Asia-Pacific Computer Systems Architecture Conference 2006: 161-174 - [c19]Shannon Koh, Oliver Diessel:
COMMA: A Communications Methodology for Dynamic Module-based Reconfiguration of FPGAs. ARCS Workshops 2006: 173-182 - [c18]Shannon Koh, Oliver Diessel:
COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs. FCCM 2006: 273-274 - [c17]Usama Malik, Oliver Diessel:
The Entropy of FPGA Reconfiguration. FPL 2006: 1-6 - [c16]Shannon Koh, Oliver Diessel:
Communications infrastructure generation for modular FPGA reconfiguration. FPT 2006: 321-324 - [i1]Oliver Diessel, Shannon Koh:
Enabling RTR for industry. Dynamically Reconfigurable Architectures 2006 - 2005
- [c15]Marco Torre, Usama Malik, Oliver Diessel:
A Configuration System Architecture Supporting Bit-Stream Compression for FPGAs. Asia-Pacific Computer Systems Architecture Conference 2005: 415-428 - [c14]Usama Malik, Oliver Diessel:
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs. FPL 2005: 636-639 - 2004
- [j3]Bernd Scheuermann, Keith So, Michael Guntsch, Martin Middendorf, Oliver Diessel, Hossam A. ElGindy, Hartmut Schmeck:
FPGA implementation of population-based ant colony optimization. Appl. Soft Comput. 4(3): 303-322 (2004) - [c13]Usama Malik, Oliver Diessel:
On the placement and granularity of FPGA configurations. FPT 2004: 161-168 - [e1]Oliver Diessel, John Williams:
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004. IEEE 2004 [contents] - 2002
- [c12]Oliver Diessel, Usama Malik, Keith So:
Towards High-Level Specification, Synthesis, and Virtualization of Programmable Logic Designs (Research Note). Euro-Par 2002: 314-318 - [c11]Usama Malik, Keith So, Oliver Diessel:
Resource-aware run-time elaboration of behavioural FPGA specifications. FPT 2002: 68-75 - [c10]Michael Guntsch, Martin Middendorf, Bernd Scheuermann, Oliver Diessel, Hossam A. ElGindy, Hartmut Schmeck, Keith So:
Population based ant colony optimization on FPGA. FPT 2002: 125-132 - [c9]Oliver Diessel, Usama Malik:
An FPGA Interpreter with Virtual Hardware Management. IPDPS 2002 - 2001
- [j2]Oliver Diessel, Hossam A. ElGindy:
On Dynamic Task Scheduling for EPGA-Based Systems. Int. J. Found. Comput. Sci. 12(5): 645-669 (2001) - [c8]Gordon J. Brebner, Oliver Diessel:
Chip-Based Reconfigurable Task Management. FPL 2001: 182-191 - 2000
- [c7]Oliver Diessel, George J. Milne:
Behavioural Language Compilation with Virtual Hardware Management. FPL 2000: 707-717 - [c6]Hossam A. ElGindy, Viktor K. Prasanna, Hartmut Schmeck, Oliver Diessel:
Configurable Architectures Workshop (RAW 2000). IPDPS Workshops 2000: 870-872 - [c5]Oliver Diessel, George J. Milne:
Compiling Process Algebraic Descriptions into Reconfigurable Logic. IPDPS Workshops 2000: 916-923
1990 – 1999
- 1999
- [c4]Oliver Diessel, David A. Kearney, Grant B. Wigley:
A Web-Based Multiuser Operating System for Reconfiguarble Computing. IPPS/SPDP Workshops 1999: 579-587 - 1998
- [c3]Oliver Diessel, Hossam A. ElGindy:
Partial FPGA Rearrangement by Local Repacking (Abstract). FPGA 1998: 259 - [c2]Oliver Diessel, Hossam A. ElGindy:
Partial Rearrangements of Space-Shared FPGAs. IPPS/SPDP Workshops 1998: 913-918 - 1997
- [c1]Oliver Diessel, Hossam A. ElGindy:
Run-time compaction of FPGA designs. FPL 1997: 131-140 - 1996
- [j1]Bryan Beresford-Smith, Oliver Diessel, Hossam A. ElGindy:
Optimal Algorithms for Constrained Reconfigurable Meshes. J. Parallel Distributed Comput. 39(1): 74-78 (1996)
Coauthor Index
aka: Ediz Cetin
aka: Nguyen T. H. Nguyen
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