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ORCID26th FCCM 2018: Boulder, CO, USA
- 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2018, Boulder, CO, USA, April 29 - May 1, 2018. IEEE Computer Society 2018, ISBN 978-1-5386-5522-1
Presentation Papers
Session 1: Computation and NoCs
- Eric Matthews, Zavier Aguila, Lesley Shannon:
Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISA. 1-8 - Zhenyuan Ruan, Tong He, Bojie Li, Peipei Zhou
, Jason Cong:
ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGA. 9-16 - Siddhartha, Nachiket Kapre:
Hoplite-Q: Priority-Aware Routing in FPGA Overlay NoCs. 17-24 - Shivukumar B. Patil, Tianqi Liu, Russell Tessier:
A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip. 25-28
Session 2: Cryptography, Compression, and Security
- Farnoud Farahmand, William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj:
Improved Lightweight Implementations of CAESAR Authenticated Ciphers. 29-36 - Weikang Qiao, Jieqiong Du, Zhenman Fang, Michael Lo, Mau-Chung Frank Chang, Jason Cong:
High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms. 37-44 - Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sébastien Pillement, Daniel E. Holcomb, Russell Tessier:
FPGA Side Channel Attacks without Physical Access. 45-52 - Festus Hategekimana, Joel Mandebi Mbongue, Md Jubaer Hossain Pantho, Christophe Bobda:
Inheriting Software Security Policies within Hardware IP Components. 53-56
Session 3: Machine Learning
- Mohammad Ghasemzadeh, Mohammad Samragh, Farinaz Koushanfar:
ReBNet: Residual Binarized Neural Network. 57-64 - Amir Yazdanbakhsh, Michael Brzozowski, Behnam Khaleghi, Soroush Ghodrati, Kambiz Samadi, Nam Sung Kim, Hadi Esmaeilzadeh:
FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial Networks. 65-72 - Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis:
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs. 73-80 - Tong Geng, Tianqi Wang, Ahmed Sanaullah, Chen Yang, Rui Xu, Rushi Patel, Martin C. Herbordt:
FPDeep: Acceleration and Load Balancing of CNN Training on FPGA Clusters. 81-84
Session 4: Leveraging Platform Technology
- Sam Skalicky, Joshua S. Monson, Andrew G. Schmidt, Matthew French:
Hot & Spicy: Improving Productivity with Python and HLS for FPGAs. 85-92 - Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu, Shaochong Zhang:
Understanding Performance Differences of FPGAs and GPUs. 93-96 - Madison N. Emas, Austin Baylis, Greg Stitt:
High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlex. 97-100
Session 5: High-Level Synthesis
- Nadesh Ramanathan, George A. Constantinides, John Wickerson:
Concurrency-Aware Thread Scheduling for High-Level Synthesis. 101-108 - Omar Ragheb, Jason Helge Anderson:
High-Level Synthesis of FPGA Circuits with Multiple Clock Domains. 109-116 - Asif Islam, Nachiket Kapre:
LegUp-NoC: High-Level Synthesis of Loops with Indirect Addressing. 117-124 - Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou:
Latte: Locality Aware Transformation for High-Level Synthesis. 125-128 - Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F. Y. Young, Zhiru Zhang:
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning. 129-132
Session 6: FPGA CAD and Architectures
- Chris Lavin, Alireza Kaviani:
RapidWright: Enabling Custom Crafted Implementations for FPGAs. 133-140 - Matthew Cannon, Andrew M. Keller, Michael J. Wirthlin:
Improving the Effectiveness of TMR Designs on FPGAs with SEU-Aware Incremental Placement. 141-148 - Jeffrey Goeders, Tanner Gaskin, Brad L. Hutchings:
Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQ. 149-156
Session 7: Memory
- Dongyang Li, Fei Wu, Yang Weng, Qing Yang, Changsheng Xie:
HODS: Hardware Object Deserialization Inside SSD Storage. 157-164 - Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang:
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms. 165-172 - Abhishek Kumar Jain, G. Scott Lloyd, Maya B. Gokhale:
Microscope on Memory: MPSoC-Enabled Computer Memory System Assessments. 173-180
Session 8: Applications
- Zhuolun He, Hanxian Huang, Ming Jiang, Yuanchao Bai, Guojie Luo:
FPGA-Based Real-Time Super-Resolution System for Ultra High Definition Videos. 181-188 - Tobias Kenter, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, Christian Plessl:
OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes. 189-196 - Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise:
A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback Datapath. 197-204
Posters
Session P1
- Zhong Guan:
EM-Aware Memory Mapping Algorithms for SRAM Based FPGA. 205 - Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu:
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA Sequencing. 206 - Jialiang Zhang, Jing Li:
PQ-CNN: Accelerating Product Quantized Convolutional Neural Network on FPGA. 207 - Guohao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek:
NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing Overheads. 208 - Minghua Shen, Guojie Luo, Nong Xiao:
Exploiting Box Expansion and Grid Partitioning for Parallel FPGA Routing. 209 - Xiaofan Zhang, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong, Wen-Mei W. Hwu, Deming Chen:
AccDNN: An IP-Based DNN Generator for FPGAs. 210 - Björn Gottschall, Thomas PreuBer, Akash Kumar:
Reloc - An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration Tiles. 211 - Dimitris Agiakatsikas, Ganghee Lee, Thomas Mitchell, Ediz Cetin, Oliver Diessel:
From C to Fault-Tolerant FPGA-Based Systems. 212
Session P2
- Deshya Wijesundera, Alok Prakash, Thilina Perera, Kalindu Herath, Thambipillai Srikanthan:
Wibheda: Framework for Data Dependency-Aware Multi-Constrained Hardware-Software Partitioning in FPGA-Based SoCs for IoT Devices. 213 - Denis Matousek, Jirí Matousek, Jan Korenek:
High-Speed Regular Expression Matching with Pipelined Memory-Based Automata. 214 - Nele Mentens, Edoardo Charbon, Francesco Regazzoni:
Rethinking Secure FPGAs: Towards a Cryptography-Friendly Configurable Cell Architecture and Its Automated Design Flow. 215 - Abdul-Amir Yassine, Yasmin Afsharnejad, Omar Ragheb, Vaughn Betz, Paul Chow:
A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media. 216 - Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews, Marjan Asadinia:
Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube Computer. 217 - Sunwoong Kim, Rob A. Rutenbar:
Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA. 218 - Jiayi Sheng, Chen Yang, Tianqi Wang, Martin C. Herbordt:
High Performance Dynamic Communication on Reconfigurable Clusters. 219 - Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano:
Performance Prediction for Large-Scale Heterogeneous Platforms. 220
Session P3
- Katayoun Neshatpour, Hosein Mohammadi Makrani, Avesta Sasan, Hassan Ghasemzadeh, Setareh Rafatirad, Houman Homayoun:
Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduce. 221 - José Luis Imaña:
Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible Trinomials. 222 - Erwei Wang, James J. Davis, Peter Y. K. Cheung:
A PYNQ-Based Framework for Rapid CNN Prototyping. 223 - Ciro Ceissler, Ramon Nepomuceno, Márcio Machado Pereira, Guido Araujo:
Automatic Offloading of Cluster Accelerators. 224 - Jieming Xu, Miriam Leeser:
Cross Component Optimization for Modern LTE Downlink Shared Channel Implementation. 225 - Abhi D. Rajagopala, Ron Sass, Andrew G. Schmidt, Matthew French:
Bridging the Gap between Advanced Memory and Heterogeneous Architectures. 226 - Sajjad Taheri, Jin Heo, Payman Behnam, Jeffrey Chen, Alexander V. Veidenbaum, Alexandru Nicolau:
Acceleration Framework for FPGA Implementation of OpenVX Graph Pipelines. 227 - Jason Cong, Jie Wang:
Automatic Interior I/O Elimination in Systolic Array Architecture. 228
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