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2020 – today
- 2024
- [j65]Le Yu
, Zhiheng Liang
, Yaqi Li, Shiwei Zhang, Yiren Zhao, Peter Y. K. Cheung:
Verification and Fault Injection Platform Based on MTB Stimulus Generation Method for L2 Deep Market Quote Decoder. IEEE Access 12: 54272-54284 (2024) - 2023
- [j64]Erwei Wang
, James J. Davis
, Daniele Moro
, Piotr Zielinski
, Jia Jie Lim
, Claudionor Coelho
, Satrajit Chatterjee
, Peter Y. K. Cheung
, George A. Constantinides
:
Enabling Binary Neural Network Training on the Edge. ACM Trans. Embed. Comput. Syst. 22(6): 105:1-105:19 (2023) - [j63]Erwei Wang
, Marie Auffret
, Georgios-Ilias Stavrou
, Peter Y. K. Cheung
, George A. Constantinides
, Mohamed S. Abdelfattah
, James J. Davis
:
Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(4): 57:1-57:25 (2023) - 2022
- [c212]Erwei Wang, James J. Davis, Georgios-Ilias Stavrou
, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah:
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. FPGA 2022: 101-111 - 2021
- [j62]Michelangelo Bin, Peter Y. K. Cheung, Emanuele Crisostomi
, Pietro Ferraro
, Hugo Lhachemi
, Roderick Murray-Smith
, Connor Myant
, Thomas Parisini, Robert Shorten
, Sebastian Stein
, Lewi Stone
:
Post-lockdown abatement of COVID-19 by fast periodic switching. PLoS Comput. Biol. 17(1) (2021) - [c211]Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno
, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski
, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk:
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. ASAP 2021: 117-124 - [c210]Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Jia Jie Lim, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides:
Enabling Binary Neural Network Training on the Edge. EMDL@MobiSys 2021: 37-38 - [i9]Erwei Wang, James J. Davis, Daniele Moro, Piotr Zielinski, Claudionor Coelho, Satrajit Chatterjee, Peter Y. K. Cheung, George A. Constantinides:
Enabling Binary Neural Network Training on the Edge. CoRR abs/2102.04270 (2021) - [i8]Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk:
Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. CoRR abs/2106.14089 (2021) - [i7]Erwei Wang, James J. Davis, Georgios-Ilias Stavrou, Peter Y. K. Cheung, George A. Constantinides, Mohamed S. Abdelfattah:
Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. CoRR abs/2112.02346 (2021) - 2020
- [j61]Erwei Wang
, James J. Davis
, Peter Y. K. Cheung, George A. Constantinides
:
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. IEEE Trans. Computers 69(12): 1795-1808 (2020) - [i6]Michelangelo Bin, Peter Y. K. Cheung, Emanuele Crisostomi, Pietro Ferraro, Connor Myant, Thomas Parisini, Robert Shorten:
On Fast Multi-Shot Epidemic Interventions for Post Lock-Down Mitigation: Implications for Simple Covid-19 Models. CoRR abs/2003.09930 (2020)
2010 – 2019
- 2019
- [j60]Erwei Wang
, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. 52(2): 40:1-40:39 (2019) - [j59]Jianxiong Liu, Christos Bouganis
, Peter Y. K. Cheung:
Context-based image acquisition from memory in digital systems. J. Real Time Image Process. 16(4): 1057-1076 (2019) - [c209]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. FCCM 2019: 26-34 - [c208]Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas
, Peter Y. K. Cheung:
Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. FPL 2019: 81-87 - [c207]Yiren Zhao, Xitong Gao
, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu
:
Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs. FPT 2019: 45-53 - [i5]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR abs/1901.06955 (2019) - [i4]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. CoRR abs/1904.00938 (2019) - [i3]Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu:
Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs. CoRR abs/1910.10075 (2019) - [i2]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. CoRR abs/1910.12625 (2019) - 2018
- [j58]Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok:
CypherDB: A Novel Architecture for Outsourcing Secure Database Processing. IEEE Trans. Cloud Comput. 6(2): 372-386 (2018) - [j57]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11(1): 2:1-2:22 (2018) - [c206]Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas
, Philip Heng Wai Leong
, Peter Y. K. Cheung:
Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. ARC 2018: 16-28 - [c205]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas
, Philip Heng Wai Leong
, Peter Y. K. Cheung:
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC 2018: 29-42 - [c204]Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Hardware Compilation of Deep Neural Networks: An Overview. ASAP 2018: 1-8 - [c203]Erwei Wang, James J. Davis, Peter Y. K. Cheung:
A PYNQ-Based Framework for Rapid CNN Prototyping. FCCM 2018: 223 - [c202]Qiang Li, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung:
Accelerating Top-k ListNet Training for Ranking Using FPGA. FPT 2018: 242-245 - [c201]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL 2018: 4:1 - [i1]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR abs/1807.10577 (2018) - 2017
- [j56]James J. Davis
, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34(6): 36-45 (2017) - [c200]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
STRIPE: Signal selection for runtime power estimation. FPL 2017: 1-8 - 2016
- [j55]Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung:
Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. SIGARCH Comput. Archit. News 44(4): 68-73 (2016) - [c199]James J. Davis, Peter Y. K. Cheung:
Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators. ARC 2016: 361-368 - [c198]Jiang Su, David B. Thomas
, Peter Y. K. Cheung:
Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. FCCM 2016: 48-51 - [c197]Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM 2016: 56-63 - [c196]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA 2016: 276 - 2015
- [j54]Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan M. Maciejowski, Peter Y. K. Cheung, Wayne Luk:
Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 7(4): 36:1-36:17 (2015) - [c195]Peter Y. K. Cheung, Wayne Luk, Cristina Silvano
:
Preface. FPL 2015: 1-2 - [c194]Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok:
An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine. FPT 2015: 248-251 - [c193]Andrew Bean, Nachiket Kapre, Peter Y. K. Cheung:
G-DMA: improving memory access performance for hardware accelerated sparse graph computation. ReConFig 2015: 1-6 - 2014
- [j53]Zhenyu Guan, Justin S. J. Wong
, Sumanta Chaudhuri
, George A. Constantinides, Peter Y. K. Cheung:
Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. IEICE Electron. Express 11(3): 20130912 (2014) - [j52]Zhenyu Guan, Justin S. J. Wong
, Sumanta Chaudhuri
, George A. Constantinides, Peter Y. K. Cheung:
Mitigation of process variation effect in FPGAs with partial rerouting method. IEICE Electron. Express 11(3): 20140011 (2014) - [c192]Jianxiong Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung:
Image progressive acquisition for hardware systems. DATE 2014: 1-6 - [c191]Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre:
Timing Fault Detection in FPGA-Based Circuits. FCCM 2014: 96-99 - [c190]James J. Davis, Peter Y. K. Cheung:
Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration. FCCM 2014: 103 - [c189]Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong
, Peter Y. K. Cheung, Wayne Luk:
SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. FCCM 2014: 141-148 - [c188]Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung:
Dynamic voltage & frequency scaling with online slack measurement. FPGA 2014: 65-74 - [c187]James J. Davis, Peter Y. K. Cheung:
Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. FPL 2014: 1-6 - [c186]Jianxiong Liu, Christos Bouganis, Peter Y. K. Cheung:
Kernel-based Adaptive Image Sampling. VISAPP (1) 2014: 25-32 - 2013
- [j51]Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong
, Peter Y. K. Cheung:
Variation and Reliability in FPGAs. IEEE Des. Test 30(6): 50-59 (2013) - [j50]Adam Powell, Christos-Savvas Bouganis
, Peter Y. K. Cheung:
High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration. J. Syst. Archit. 59(10-D): 1144-1156 (2013) - [j49]Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski:
Accelerating sequential Monte Carlo method for real-time air traffic management. SIGARCH Comput. Archit. News 41(5): 35-40 (2013) - [j48]Justin S. J. Wong
, Peter Y. K. Cheung:
Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2307-2320 (2013) - [c185]Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski:
Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. ARC 2013: 1-12 - [c184]Zhenyu Guan, Justin S. J. Wong
, Sumanta Chaudhuri
, George A. Constantinides, Peter Y. K. Cheung:
A variation-adaptive retiming method exploiting reconfigurability. FPL 2013: 1-4 - [c183]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. FPL 2013: 1-4 - [c182]Thomas C. P. Chau, Ka-Wai Kwok
, Gary C. T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse
, Peter Y. K. Cheung, Wayne Luk:
Acceleration of real-time Proximity Query for dynamic active constraints. FPT 2013: 206-213 - [c181]Zhenyu Guan, Justin S. J. Wong
, Sumanta Chaudhuri
, George A. Constantinides, Peter Y. K. Cheung:
Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. FPT 2013: 254-261 - [c180]James J. Davis, Peter Y. K. Cheung:
Datapath fault tolerance for parallel accelerators. FPT 2013: 366-369 - [c179]Jianxiong Liu, Christos Bouganis
, Peter Y. K. Cheung:
Domain-specific progressive sampling of face images. GlobalSIP 2013: 1021-1024 - 2012
- [j47]Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung:
Roberts: reconfigurable platform for benchmarking real-time systems. SIGARCH Comput. Archit. News 40(5): 10-15 (2012) - [c178]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM 2012: 109-116 - [c177]Zhenyu Guan, Justin S. J. Wong
, Sumanta Chaudhuri
, George A. Constantinides, Peter Y. K. Cheung:
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL 2012: 519-522 - [c176]Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski:
Adaptive Sequential Monte Carlo approach for real-time applications. FPL 2012: 527-530 - [c175]Adam Powell, Christos-Savvas Bouganis
, Peter Y. K. Cheung:
Early performance estimation of image compression methods on soft processors. FPL 2012: 587-590 - 2011
- [j46]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. Comput. J. 54(1): 1-10 (2011) - [j45]Maria E. Angelopoulou, Christos-Savvas Bouganis
, Peter Y. K. Cheung:
Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array. IET Comput. Digit. Tech. 5(4): 271-286 (2011) - [j44]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes:
A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. Trans. High Perform. Embed. Archit. Compil. 4: 63-83 (2011) - [j43]Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk:
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Trans. Ind. Electron. 58(8): 3701-3716 (2011) - [j42]Peter Y. K. Cheung:
Introduction to special section FPGA 2009. ACM Trans. Reconfigurable Technol. Syst. 4(4): 31:1 (2011) - [c174]Justin S. J. Wong
, Peter Y. K. Cheung:
Improved delay measurement method in FPGA based on transition probability. FPGA 2011: 163-172 - [c173]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA 2011: 284 - [c172]Edward A. Stott, Peter Y. K. Cheung:
Improving FPGA Reliability with Wear-Levelling. FPL 2011: 323-328 - [c171]Sumanta Chaudhuri
, Justin S. J. Wong
, Peter Y. K. Cheung:
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. FPT 2011: 1-8 - 2010
- [j41]Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung:
Fault tolerance and reliability in field-programmable gate arrays. IET Comput. Digit. Tech. 4(3): 196-210 (2010) - [j40]Tobias Becker
, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa:
Power Characterisation for Fine-Grain Reconfigurable Fabrics. Int. J. Reconfigurable Comput. 2010: 787405:1-787405:9 (2010) - [j39]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined intra-chip signaling for on-FPGA communications. Integr. 43(2): 188-201 (2010) - [j38]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes:
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study. IEEE Trans. Computers 59(4): 433-448 (2010) - [j37]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
FPGA Architecture Optimization Using Geometric Programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(8): 1163-1176 (2010) - [j36]Peter Jamieson, Tobias Becker
, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen:
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. ACM Trans. Design Autom. Electr. Syst. 15(2): 14:1-14:24 (2010) - [j35]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. ACM Trans. Reconfigurable Technol. Syst. 3(3): 13:1-13:21 (2010) - [j34]Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. ACM Trans. Reconfigurable Technol. Syst. 4(1): 3:1-3:23 (2010) - [j33]Christos-Savvas Bouganis
, Iosifina Pournara, Peter Y. K. Cheung:
Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 436-449 (2010) - [c170]Peter Y. K. Cheung:
Process Variability and Degradation: New Frontier for Reconfigurable. ARC 2010: 2 - [c169]Sebastián López, Roberto Sarmiento
, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung:
Exploration of hardware sharing for image encoders. DATE 2010: 1737-1742 - [c168]Tobias Becker
, Wayne Luk, Peter Y. K. Cheung:
Energy-Aware Optimisation for Run-Time Reconfiguration. FCCM 2010: 55-62 - [c167]Edward A. Stott, Justin S. J. Wong
, N. Pete Sedcole, Peter Y. K. Cheung:
Degradation in FPGAs: measurement and modelling. FPGA 2010: 229-238 - [c166]David Huw Jones
, Adam Powell, Christos-Savvas Bouganis
, Peter Y. K. Cheung:
GPU Versus FPGA for High Productivity Computing. FPL 2010: 119-124 - [c165]Edward A. Stott, Justin S. J. Wong
, Peter Y. K. Cheung:
Degradation Analysis and Mitigation in FPGAs. FPL 2010: 428-433 - [c164]David Huw Jones
, Adam Powell, Christos-Savvas Bouganis
, Peter Y. K. Cheung:
A Salient Region Detector for GPU Using a Cellular Automata Architecture. ICONIP (2) 2010: 501-508 - [c163]Yan Wu
, Polake Kuvinichkul, Peter Y. K. Cheung, Yiannis Demiris
:
Towards anthropomorphic robot Thereminist. ROBIO 2010: 235-240 - [e4]Peter Y. K. Cheung, John Wawrzynek:
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010. ACM 2010, ISBN 978-1-60558-911-4 [contents]
2000 – 2009
- 2009
- [j32]Yang Liu, Christos-Savvas Bouganis
, Peter Y. K. Cheung:
Hardware architectures for eigenvalue computation of real symmetric matrices. IET Comput. Digit. Tech. 3(1): 72-84 (2009) - [j31]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. IET Comput. Digit. Tech. 3(3): 235-246 (2009) - [j30]Suhaib A. Fahmy
, Peter Y. K. Cheung, Wayne Luk:
High-throughput one-dimensional median and weighted median filters on FPGA. IET Comput. Digit. Tech. 3(4): 384-394 (2009) - [j29]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 305-315 (2009) - [j28]Jonathan A. Clarke
, George A. Constantinides, Peter Y. K. Cheung:
Word-length selection for power minimization via nonlinear optimization. ACM Trans. Design Autom. Electr. Syst. 14(3): 39:1-39:28 (2009) - [j27]Christos-Savvas Bouganis
, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung:
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. ACM Trans. Reconfigurable Technol. Syst. 1(4): 24:1-24:28 (2009) - [j26]Justin S. J. Wong
, N. Pete Sedcole, Peter Y. K. Cheung:
Self-Measurement of Combinatorial Circuit Delays in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 10:1-10:22 (2009) - [j25]Maria E. Angelopoulou, Christos-Savvas Bouganis
, Peter Y. K. Cheung, George A. Constantinides:
Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement. ACM Trans. Reconfigurable Technol. Syst. 2(4): 22:1-22:29 (2009) - [c162]Tobias Becker
, Wayne Luk, Peter Y. K. Cheung:
Parametric Design for Reconfigurable Software-Defined Radio. ARC 2009: 15-26 - [c161]Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung:
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. ARC 2009: 133-144 - [c160]Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS 2009: 119-128 - [c159]Philip G. Potter, Wayne Luk, Peter Y. K. Cheung:
Partition-based exploration for reconfigurable JPEG designs. DATE 2009: 886-889 - [c158]Peter Jamieson, Tobias Becker
, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen:
Benchmarking Reconfigurable Architectures in the Mobile Domain. FCCM 2009: 131-138 - [c157]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Area estimation and optimisation of FPGA routing fabrics. FPL 2009: 256-261 - [c156]N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung:
Compensating for variability in FPGAs by re-mapping and re-placement. FPL 2009: 613-616 - [c155]Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung:
Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT 2009: 54-61 - [c154]Maria E. Angelopoulou, Christos-Savvas Bouganis
, Peter Y. K. Cheung:
A sensor-based approach to linear blur identification for real-time video enhancement. ICIP 2009: 141-144 - [c153]Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung:
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. ISCAS 2009: 1293-1296 - [e3]Paul Chow, Peter Y. K. Cheung:
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009. ACM 2009, ISBN 978-1-60558-410-2 [contents] - 2008
- [j24]Peter Y. K. Cheung, Alexandre Yakovlev:
Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber. Comput. J. 51(6): 741-742 (2008) - [j23]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
Custom parallel caching schemes for hardware-accelerated image compression. J. Real Time Image Process. 3(4): 289-302 (2008) - [j22]Sutjipto Arifin, Peter Y. K. Cheung:
Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information. IEEE Trans. Multim. 10(7): 1325-1341 (2008) - [j21]N. Pete Sedcole, Peter Y. K. Cheung:
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. ACM Trans. Reconfigurable Technol. Syst. 1(2): 10:1-10:28 (2008) - [j20]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 733-744 (2008) - [j19]Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung:
Outer Loop Pipelining for Application Specific Datapaths in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1268-1280 (2008) - [j18]Maria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos:
Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs. J. Signal Process. Syst. 51(1): 3-21 (2008) - [c152]Maria E. Angelopoulou, Christos-Savvas Bouganis
, Peter Y. K. Cheung, George A. Constantinides:
FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. ARC 2008: 124-135 - [c151]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. BCS Int. Acad. Conf. 2008: 295-304 - [c150]Ben Cope, Peter Y. K. Cheung, Wayne Luk:
Using Reconfigurable Logic to Optimise GPU Memory Accesses. DATE 2008: 44-49 - [c149]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258 - [c148]N. Pete Sedcole, Justin S. J. Wong
, Peter Y. K. Cheung:
Measuring and modeling FPGA clock variability. FPGA 2008: 258 - [c147]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL 2008: 179-184 - [c146]Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung:
Fault tolerant methods for reliability in FPGAs. FPL 2008: 415-420 - [c145]Tobias Becker
, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa:
Towards benchmarking energy efficiency of reconfigurable architectures. FPL 2008: 691-694 - [c144]Justin S. J. Wong
, Peter Y. K. Cheung, N. Pete Sedcole:
Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL 2008: 703-704 - [c143]Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos:
Co-optimisation of datapath and memory in outer loop pipelining. FPT 2008: 1-8 - [c142]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined signaling for on-FPGA communication. FPT 2008: 9-16 - [c141]Justin S. J. Wong
, N. Pete Sedcole, Peter Y. K. Cheung:
A transition probability based delay measurement method for arbitrary circuits on FPGAs. FPT 2008: 105-112 - [c140]N. Pete Sedcole, Justin S. J. Wong
, Peter Y. K. Cheung:
Modelling and compensating for clock skew variability in FPGAs. FPT 2008: 217-224 - [c139]Maria E. Angelopoulou, Christos-Savvas Bouganis
, Peter Y. K. Cheung:
Video enhancement on an adaptive image sensor. ICIP 2008: 681-684 - [c138]Jonathan A. Clarke
, George A. Constantinides, Peter Y. K. Cheung, Alastair M. Smith:
Glitch-aware output switching activity from word-level statistics. ISCAS 2008: 1792-1795 - [c137]N. Pete Sedcole, Justin S. J. Wong
, Peter Y. K. Cheung:
Characterisation of FPGA Clock Variability. ISVLSI 2008: 322-328 - [c136]Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk:
Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS 2008: 213-214 - [c135]Ben Cope, Peter Y. K. Cheung, Wayne Luk:
Systematic design space exploration for customisable multi-processor architectures. ICSAMOS 2008: 57-64 - [c134]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Interconnection lengths and delays estimation for communication links in FPGAs. SLIP 2008: 1-10 - [c133]Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk:
Global interconnections in FPGAs: modeling and performance analysis. SLIP 2008: 51-58 - 2007
- [j17]Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung:
ROM to DSP block transfer for resource constrained synthesis. IET Comput. Digit. Tech. 1(1): 17-26 (2007) - [j16]Suhaib A. Fahmy
, Christos-Savvas Bouganis
, Peter Y. K. Cheung, Wayne Luk:
Real-time hardware acceleration of the trace transform. J. Real Time Image Process. 2(4): 235-248 (2007) - [j15]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 1003-1016 (2007) - [c132]Ben Cope, Peter Y. K. Cheung, Wayne Luk:
Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. ASAP 2007: 308-313 - [c131]Tobias Becker
, Wayne Luk, Peter Y. K. Cheung:
Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. FCCM 2007: 35-44 - [c130]Christos-Savvas Bouganis
, Iosifina Pournara, Peter Y. K. Cheung:
Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs. FCCM 2007: 141-150 - [c129]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Automatic On-chip Memory Minimization for Data Reuse. FCCM 2007: 251-260 - [c128]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
A Hybrid Memory Sub-system for Video Coding Applications. FCCM 2007: 317-318 - [c127]N. Pete Sedcole, Peter Y. K. Cheung:
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. FPGA 2007: 178-187 - [c126]Jonathan A. Clarke
, George A. Constantinides, Peter Y. K. Cheung:
On the feasibility of early routing capacitance estimation for FPGAs. FPL 2007: 234-239 - [c125]Yang Liu, Christos-Savvas Bouganis
, Peter Y. K. Cheung:
Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. FPL 2007: 345-350 - [c124]Justin S. J. Wong
, N. Pete Sedcole, Peter Y. K. Cheung:
Self-characterization of Combinatorial Circuit Delays in FPGAs. FPT 2007: 17-23 - [c123]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction. FPT 2007: 105-112 - [c122]Sutjipto Arifin, Peter Y. K. Cheung:
A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information. ICIP (6) 2007: 333-336 - [c121]Sutjipto Arifin, Peter Y. K. Cheung:
A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional information. ACM Multimedia 2007: 68-77 - [c120]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182 - [c119]Sutjipto Arifin, Peter Y. K. Cheung:
A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on "Working Memory". ICSC 2007: 147-154 - 2006
- [j14]Gabriel Caffarena
, George A. Constantinides, Peter Y. K. Cheung, Carlos Carreras
, Octavio Nieto-Taladriz:
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 339-343 (2006) - [c118]Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC 2006: 205-216 - [c117]Sutjipto Arifin, Peter Y. K. Cheung:
A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. DATE Designers' Forum 2006: 227-232 - [c116]Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung, Philip Heng Wai Leong, Stephen J. Motley:
Hardware efficient architectures for Eigenvalue computation. DATE 2006: 953-958 - [c115]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. FCCM 2006: 275-276 - [c114]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
Yield enhancements of design-specific FPGAs. FPGA 2006: 93-100 - [c113]Sutjipto Arifin, Peter Y. K. Cheung:
Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. FPL 2006: 1-4 - [c112]Christos-Savvas Bouganis
, Peter Y. K. Cheung, Zhaoping Li:
FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. FPL 2006: 1-6 - [c111]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. FPL 2006: 1-6 - [c110]Suhaib A. Fahmy
, Christos-Savvas Bouganis
, Peter Y. K. Cheung, Wayne Luk:
Efficient Realtime FPGA Implementation of the Trace Transform. FPL 2006: 1-6 - [c109]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
On-FPGA Communication Architectures and Design Factors. FPL 2006: 1-8 - [c108]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. FPL 2006: 1-6 - [c107]N. Pete Sedcole, Peter Y. K. Cheung:
Within-die delay variability in 90nm FPGAs and beyond. FPT 2006: 97-104 - [c106]Maria E. Angelopoulou, Konstantinos Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos:
A comparison of 2-D discrete wavelet transform computation schedules on FPGAs. FPT 2006: 181-188 - [c105]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
The cost of data dependence in motion vector estimation for reconfigurable platforms. FPT 2006: 333-336 - [c104]Christos-Savvas Bouganis
, Iosifina Pournara, Peter Y. K. Cheung:
A statistical framework for dimensionality reduction implementation in FPGAs. FPT 2006: 365-368 - [c103]Sutjipto Arifin, Peter Y. K. Cheung:
User Attention Based Arousal Content Modeling. ICIP 2006: 433-436 - [c102]Yang Liu, Christos-Savvas Bouganis
, Peter Y. K. Cheung:
A Spatiotemporal Saliency Framework. ICIP 2006: 437-440 - [c101]Jonathan A. Clarke, Altaf Abdul Gaffar, George A. Constantinides, Peter Y. K. Cheung:
Fast word-level power models for synthesis of FPGA-based arithmetic. ISCAS 2006 - [c100]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS 2006: 168-176 - 2005
- [j13]Theerayod Wiangtong
, Peter Y. K. Cheung, Wayne Luk:
Hardware/software codesign: a systematic approach targeting data-intensive applications. IEEE Signal Process. Mag. 22(3): 14-22 (2005) - [j12]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 39-57 (2005) - [j11]Ray C. C. Cheung
, N. J. Telle, Wayne Luk, Peter Y. K. Cheung:
Customizable elliptic curve cryptosystems. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1048-1059 (2005) - [c99]Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung:
Automating custom-precision function evaluation for embedded processors. CASES 2005: 22-31 - [c98]Suhaib A. Fahmy
, Peter Y. K. Cheung, Wayne Luk:
Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. DATE 2005: 8-13 - [c97]Ray C. C. Cheung
, Wayne Luk, Peter Y. K. Cheung:
Reconfigurable Elliptic Curve Cryptosystems on a Chip. DATE 2005: 24-29 - [c96]Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen:
Cell Based Motion Estimators for Reconfigurable Platforms. ERSA 2005: 218-224 - [c95]Christos-Savvas Bouganis
, George A. Constantinides, Peter Y. K. Cheung:
A Novel 2D Filter Design Methodology for Heterogeneous Devices. FCCM 2005: 13-22 - [c94]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. FPGA 2005: 138-148 - [c93]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Exploration of heterogeneous reconfigurable architectures (abstract only). FPGA 2005: 268 - [c92]Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung:
Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. FPL 2005: 77-82 - [c91]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung:
Power and Area Optimization for Multiple Restricted Multiplication. FPL 2005: 112-117 - [c90]Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides:
Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. FPL 2005: 124-129 - [c89]Suhaib A. Fahmy
, Peter Y. K. Cheung, Wayne Luk:
Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. FPL 2005: 142-147 - [c88]Christos-Savvas Bouganis
, Peter Y. K. Cheung, George A. Constantinides:
Heterogeneity Exploration for Multiple 2D Filter Designs. FPL 2005: 263-268 - [c87]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. FPL 2005: 341-346 - [c86]Nicola Campregher, Peter Y. K. Cheung, George A. Constantinides, Milan Vasilko:
Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. FPL 2005: 409-414 - [c85]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt:
Have GPUs Made FPGAs Redundant in the Field of Video Processing? FPT 2005: 111-118 - [c84]Laurence A. Hey, Peter Y. K. Cheung, Michael Gellman:
FPGA Based Router for Cognitive Packet Networks. FPT 2005: 331-332 - [c83]Christos-Savvas Bouganis
, George A. Constantinides, Peter Y. K. Cheung:
A novel 2D filter design methodology. ISCAS (1) 2005: 532-535 - [c82]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung:
A heuristic approach for multiple restricted multiplication. ISCAS (1) 2005: 692-695 - 2004
- [b1]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthesis and optimization of DSP algorithms. Kluwer 2004, ISBN 978-1-4020-7930-6, pp. I-XI, 1-164 - [j10]Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
:
Guest Editors' Introduction: Field Programmable Logic and Applications. IEEE Trans. Computers 53(11): 1361-1362 (2004) - [j9]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung:
A Gaussian Noise Generator for Hardware-Based Simulations. IEEE Trans. Computers 53(12): 1523-1534 (2004) - [c81]Sambuddhi Hettiaratchi, Peter Y. K. Cheung:
A Novel Implementation of Tile-Based Address Mapping. DATE 2004: 306-311 - [c80]Tero Rissa, Wayne Luk, Peter Y. K. Cheung:
Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. ERSA 2004: 184-193 - [c79]Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung:
Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. FCCM 2004: 79-88 - [c78]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM 2004: 271-272 - [c77]Gareth W. Morris, George A. Constantinides, Peter Y. K. Cheung:
Migrating Functionality from ROMS to Embedded Multipliers. FCCM 2004: 287-288 - [c76]Tero Rissa, Peter Y. K. Cheung, Wayne Luk:
SoftSONIC: A Customisable Modular Platform for Video Applications. FPL 2004: 54-63 - [c75]Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides:
Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. FPL 2004: 200-208 - [c74]Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko:
BIST Based Interconnect Fault Location for FPGAs. FPL 2004: 322-332 - [c73]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung:
Multiple Restricted Multiplication. FPL 2004: 374-383 - [c72]Christos-Savvas Bouganis
, Peter Y. K. Cheung, Jeffrey Ng, Anil A. Bharath:
A Steerable Complex Wavelet Construction and Its Implementation on FPGA. FPL 2004: 394-403 - [c71]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Structured Methodology for System-on-an-FPGA Design. FPL 2004: 1047-1051 - [c70]Ray C. C. Cheung, Ashley Brown, Wayne Luk, Peter Y. K. Cheung:
A scalable hardware architecture for prime number validation. FPT 2004: 177-184 - [c69]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
Scalable structured data access by combining autonomous memory blocks. FPT 2004: 457-460 - [c68]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
Autonomous Memory Block for reconfigurable computing. ISCAS (2) 2004: 581-584 - 2003
- [j8]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Wordlength optimization for linear digital signal processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1432-1442 (2003) - [j7]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. 8(3): 334-354 (2003) - [c67]Sambuddhi Hettiaratchi, Peter Y. K. Cheung:
Mesh Partitioning Approach to Energy Efficient Data Layout. DATE 2003: 11076-11081 - [c66]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung:
A Hardware Gaussian Noise Generator for Channel Code Evaluation. FCCM 2003: 69- - [c65]Andrew Royal, Peter Y. K. Cheung:
Globally Asynchronous Locally Synchronous FPGA Architectures. FPL 2003: 355-364 - [c64]Theerayod Wiangtong
, Peter Y. K. Cheung, Wayne Luk:
A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. FPL 2003: 396-405 - [c63]N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk:
A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL 2003: 606-615 - [c62]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung:
Non-uniform Segmentation for Hardware Function Evaluation. FPL 2003: 796-807 - [c61]Theerayod Wiangtong
, Peter Y. K. Cheung, Wayne Luk:
Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. FPL 2003: 1071-1074 - [c60]Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung:
Hierarchical segmentation schemes for function evaluation. FPT 2003: 92-99 - [c59]T. K. Lee, Arran Derbyshire, Wayne Luk, Peter Y. K. Cheung:
High-level language extensions for run-time reconfigurable systems. FPT 2003: 144-151 - [c58]Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk:
Multitasking in hardware-software codesign for reconfigurable computer. ISCAS (5) 2003: 621-624 - [c57]Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung:
Architectures for function evaluation on FPGAs. ISCAS (2) 2003: 804-807 - [c56]Theerayod Wiangtong, Chun Te Ewe, Peter Y. K. Cheung:
SONICmole: a debugging environment for the UltraSONIC reconfigurable computer. ISCAS (2) 2003: 808-811 - [e2]Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
:
Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings. Lecture Notes in Computer Science 2778, Springer 2003, ISBN 3-540-40822-3 [contents] - 2002
- [j6]Theerayod Wiangtong
, Peter Y. K. Cheung, Wayne Luk:
Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign. Des. Autom. Embed. Syst. 6(4): 425-449 (2002) - [c55]Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke:
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory. DATE 2002: 902-908 - [c54]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. FCCM 2002: 3-12 - [c53]Jörn Gause, Peter Y. K. Cheung, Wayne Luk:
Reconfigurable Shape-Adaptive Template Matching Architectures. FCCM 2002: 98- - [c52]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Optimum Wordlength Allocation. FCCM 2002: 219-228 - [c51]Theerayod Wiangtong
, Peter Y. K. Cheung, Wayne Luk:
Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. FCCM 2002: 297-298 - [c50]Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi:
Customising Floating-Point Designs. FCCM 2002: 315-317 - [c49]Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang:
Automating Customisation of Floating-Point Designs. FPL 2002: 523-533 - [c48]Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung:
Run-Time Adaptive Flexible Instruction Processors. FPL 2002: 545-555 - [c47]Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk:
Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. FPL 2002: 1148-1151 - [c46]Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi:
Floating-point bitwidth analysis via automatic differentiation. FPT 2002: 158-165 - [c45]Dong-U Lee, T. K. Lee, Wayne Luk, Peter Y. K. Cheung:
Incremental programming for reconfigurable engines. FPT 2002: 411-415 - [c44]Shay Ping Seng, Krishna V. Palem, Rodric M. Rabbah, Weng-Fai Wong
, Wayne Luk, Peter Y. K. Cheung:
PD-XML: extensible markup language for processor description. FPT 2002: 437-440 - [c43]Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen:
Strassen's matrix multiplication for customisable processors. FPT 2002: 453-456 - [c42]Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas J. W. Clarke:
Energy efficient address assignment through minimized memory row switching. ICCAD 2002: 577-581 - 2001
- [j5]Nabeel Shirazi, Dan Benyamin, Wayne Luk, Peter Y. K. Cheung, Shaori Guo:
Quantitative Analysis of FPGA-based Database Searching. J. VLSI Signal Process. 28(1-2): 85-96 (2001) - [c41]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Heuristic datapath allocation for multiple wordlength systems. DATE 2001: 791-797 - [c40]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
The Multiple Wordlength Paradigm. FCCM 2001: 51-60 - [c39]Jörn Gause, Carsten Reuter, Holger Kropp, Peter Y. K. Cheung, Wayne Luk:
The Effect of FPGA Granularity on Video Codec Implementations. FCCM 2001: 287-288 - [c38]Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk:
A Digit-Serial Structure for Reconfigurable Multipliers. FPL 2001: 565-573 - [c37]Kei-Tee Tiew, Alison J. Payne, Peter Y. K. Cheung:
MASH delta-sigma modulators for wideband and multi-standard applications. ISCAS (4) 2001: 778-781 - 2000
- [j4]Simon D. Haynes, John Stone, Peter Y. K. Cheung, Wayne Luk:
Video Image Processing with the Sonic Architecture. Computer 33(4): 50-57 (2000) - [c36]Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung:
Flexible instruction processors. CASES 2000: 193-200 - [c35]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Multiple Precision for Resource Minimization. FCCM 2000: 307-308 - [c34]Jörn Gause, Peter Y. K. Cheung, Wayne Luk:
Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. FPL 2000: 96-105 - [c33]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Multiple-Wordlength Resource Binding. FPL 2000: 646-655 - [c32]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Roundoff-noise shaping in filter design. ISCAS 2000: 57-60
1990 – 1999
- 1999
- [c31]Simon D. Haynes, Antonio B. Ferrari, Peter Y. K. Cheung:
Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs. CICC 1999: 191-194 - [c30]Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung:
Reconfigurable Computing for Augmented Reality. FCCM 1999: 136-145 - [c29]Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone:
SONIC - A Plug-In Architecture for Video Processing. FCCM 1999: 280-281 - [c28]Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone:
SONIC - A Plug-In Architecture for Video Processing. FPL 1999: 21-30 - [c27]Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung:
Quantitative Analysis of Run-Time Reconfigurable Database Search. FPL 1999: 253-263 - [c26]George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. FPL 1999: 323-332 - 1998
- [c25]Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung:
Automating Production of Run-Time Reconfigurable Designs. FCCM 1998: 147-156 - [c24]Simon D. Haynes, Peter Y. K. Cheung:
A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure. FCCM 1998: 226-234 - [c23]Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung:
Run-Time Management of Dynamically Recongigurable Designs. FPL 1998: 59-68 - [c22]Simon D. Haynes, Antonio B. Ferrari, Peter Y. K. Cheung:
Algorithms and Structures for Reconfigurable Multiplication Units. SBCCI 1998: 13 - 1997
- [j3]José T. de Sousa
, Peter Y. K. Cheung:
Diagnosis of Boards for Realistic Interconnect Shorts. J. Electron. Test. 11(2): 157-171 (1997) - [j2]Majd Alwan, Peter Y. K. Cheung:
Modelling and Handling Uncertainties in Mobile Robotics. J. Intell. Fuzzy Syst. 5(3): 205-217 (1997) - [c21]Pedro A. Molina, Peter Y. K. Cheung:
A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. ASYNC 1997: 126-139 - [c20]José T. de Sousa, Peter Y. K. Cheung:
Improved diagnosis of realistic interconnect shorts. ED&TC 1997: 501-505 - [c19]Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung:
Compilation tools for run-time reconfigurable designs. FCCM 1997: 56-65 - [c18]Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Luk, Richard Sandiford:
Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. FPL 1997: 91-100 - [c17]Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung:
Pipeline morphing and virtual pipelines. FPL 1997: 111-120 - [c16]Anjit Sekhar Chaudhuri, Peter Y. K. Cheung, Wayne Luk:
A reconfigurable data-localised array for morphological algorithms. FPL 1997: 344-353 - [c15]David S. Bormann, Peter Y. K. Cheung:
Asnchronous Wrapper for Heterogeneous Systems. ICCD 1997: 307-314 - [e1]Wayne Luk, Peter Y. K. Cheung, Manfred Glesner:
Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings. Lecture Notes in Computer Science 1304, Springer 1997, ISBN 3-540-63465-7 [contents] - 1996
- [j1]Timo Koskinen, Peter Y. K. Cheung:
Hierarchical tolerance analysis using statistical behavioral models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 506-516 (1996) - [c14]Nawwaf N. Kharma, Majd Alwan, Peter Y. K. Cheung:
An incremental machine learning mechanism applied to robot navigation. ANZIIS 1996: 325-328 - [c13]Majd Alwan, Peter Y. K. Cheung, Akram Saleh, Nour E. Cheikh Obeid:
Combining goal-directed, reactive and reflexive navigation in autonomous mobile robots. ANZIIS 1996: 346-349 - [c12]José T. de Sousa, T. Shen, Peter Y. K. Cheung:
Realistic Fault Extraction for Boards. ED&TC 1996: 612 - [c11]Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung:
Modelling and optimising run-time reconfigurable systems. FCCM 1996: 167-176 - [c10]Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke:
On the viability of FPGA-based integrated coprocessors. FCCM 1996: 206-215 - [c9]Hasan Demirel, Thomas J. Clarke, Peter Y. K. Cheung:
Adaptive Automatic Facial Feature Segmentation. FG 1996: 277-282 - 1994
- [c8]Salman Ahmed, Peter Y. K. Cheung, Phil Collins:
A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation. EDAC-ETC-EUROASIC 1994: 665 - [c7]Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke:
Area & Time Limitations of FPGA-based Virtual Hardware. ICCD 1994: 184-189 - [c6]Akachai Sang-In, Peter Y. K. Cheung:
A Method of Representative Fault Selection in Digital Circuits for ATPG. ISCAS 1994: 73-76 - [c5]Osama T. Albaharna, Peter Y. K. Cheung, Thomas J. Clarke:
Virtual Hardware and the Limits of Computational Speed-up. ISCAS 1994: 159-162 - [c4]Salman Ahmed, Peter Y. K. Cheung:
Analog Fault Diagnosis - A Practical Approach. ISCAS 1994: 351-354 - 1993
- [c3]Nasir-ud-Din Gohar, Peter Y. K. Cheung:
A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout. ISCAS 1993: 1770-1773 - 1991
- [c2]Benjamin Rogel-Favila, Antony Wakeling, Peter Y. K. Cheung:
Model-based fault diagnosis of sequential circuits and its acceleration. EURO-DAC 1991: 224-229 - [c1]Vicente Fuentes-Sánchez, Peter Y. K. Cheung:
A Tag Coprocessor Architecture for Symbolic Languages. ICCD 1991: 370-373
Coauthor Index
aka: Christos Bouganis
aka: Konstantinos Masselos
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