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Manfred Glesner
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2010 – 2019
- 2017
- [c299]Ricardo Reis, Manfred Glesner:
VLSI-SoC: An Enduring Tradition. VLSI-SoC (Selected Papers) 2017: 240-255 - 2014
- [c298]François Philipp, Manfred Glesner:
High-level abstraction for teaching smart systems design with modular hardware. EWME 2014: 146-150 - 2013
- [j48]Luciano Ost
, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Möller, Leandro Soares Indrusiak
, Gilles Sassatelli, Pascal Benoit, Manfred Glesner, Michel Robert
, Fernando Moraes
:
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach. ACM Trans. Embed. Comput. Syst. 12(3): 75:1-75:22 (2013) - [j47]Faizal Arya Samman
, Thomas Hollstein
, Manfred Glesner:
Runtime Contention and Bandwidth-Aware Adaptive Routing Selection Strategies for Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. 24(7): 1411-1421 (2013) - [c297]Ramkumar Ganesan, Jürgen Krumm, Sebastian Pankalla, Klaus Ludwig, Manfred Glesner:
Design of an organic electronic label on a flexible substrate for temperature sensing. ESSCIRC 2013: 423-426 - [c296]François Philipp, Manfred Glesner:
An event-based middleware for the remote management of runtime hardware reconfiguration. FPL 2013: 1-4 - [c295]Manfred Glesner, François Philipp:
Embedded systems design for smart system integration. ISVLSI 2013: 32-33 - 2012
- [j46]Élvio Carlos Dutra e Silva Júnior, Leandro Soares Indrusiak
, Weiler Alves Finamore, Manfred Glesner:
A Programmable Look-Up Table-Based Interpolator with Nonuniform Sampling Scheme. Int. J. Reconfigurable Comput. 2012: 647805:1-647805:14 (2012) - [j45]Faizal Arya Samman
, Thomas Hollstein
, Manfred Glesner:
Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method. Microprocess. Microsystems 36(6): 449-461 (2012) - [j44]Faizal Arya Samman
, Thomas Hollstein
, Manfred Glesner:
Erratum to Planar adaptive network-on-chip supporting deadlock-free and efficient tree-based multicast routing method Microprocessors and Microsystems (2012) 449-461. Microprocess. Microsystems 36(6): 527 (2012) - [c294]D. Erdenechimeg, Ts. Sugir, François Philipp, Manfred Glesner:
Implementation and outcomes of FPGA-based system design in Mongolian education. FPL 2012: 491-494 - [c293]François Philipp, Manfred Glesner:
(GECO)2: A graphical tool for the generation of configuration bitstreams for a smart sensor interface based on a Coarse-Grained Dynamically Reconfigurable Architecture. FPL 2012: 679-682 - [c292]Leandro Möller, Leandro Soares Indrusiak
, Luciano Ost
, Fernando Gehm Moraes
, Manfred Glesner:
Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCs. ISSoC 2012: 1-4 - [c291]François Philipp, Conrad Klytta, Manfred Glesner, Élvio Dutra:
Hardware acceleration of combined cipher and forward error correction for low-power wireless applications. ReCoSoC 2012: 1-7 - 2011
- [j43]Faizal Arya Samman
, Thomas Hollstein
, Manfred Glesner:
Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip. Microprocess. Microsystems 35(3): 343-358 (2011) - [j42]Faizal Arya Samman
, Thomas Hollstein
, Manfred Glesner:
New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip. IEEE Trans. Parallel Distributed Syst. 22(4): 544-557 (2011) - [c290]Faizal Arya Samman
, François Philipp, Manfred Glesner:
Reconfigurable interconnect infrastructure for multi-FPGA-based adaptive multiprocessing systems. CHANGE@ASPLOS 2011: 1-8 - [c289]Surapong Pongyupinpanich, Manfred Glesner:
Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC. FPL 2011: 382-384 - [c288]François Philipp, Manfred Glesner:
Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node. FPL 2011: 396-398 - [c287]François Philipp, Manfred Glesner:
A Multi-level Reconfigurable Architecture for a Wireless Sensor Node Coprocessing Unit. IPDPS Workshops 2011: 334-337 - [c286]Ping Zhao, Manfred Glesner:
RF energy harvester design with autonomously adaptive impedance matching network based on auxiliary charge-pump rectifier. ISCAS 2011: 2477-2480 - [c285]Thomas Hollstein
, Faizal Arya Samman
, Ashok Jaiswal, Haoyuan Ying, Manfred Glesner, Klaus Hofmann:
Invited paper: Design criteria for dependable System-on-Chip architectures. ReCoSoC 2011: 1-6 - [c284]Faizal Arya Samman
, Surapong Pongyupinpanich, Manfred Glesner:
Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems. ReCoSoC 2011: 1-6 - [c283]François Philipp, Faizal Arya Samman
, Manfred Glesner:
Design of an autonomous platform for distributed sensing-actuating systems. International Symposium on Rapid System Prototyping 2011: 85-90 - [c282]Surapong Pongyupinpanich, Manfred Glesner:
On-chip efficient Round-Robin scheduler for high-speed interconnection. International Symposium on Rapid System Prototyping 2011: 199-202 - [c281]Luciano Ost
, Marcelo Mandelli, Gabriel Marchesan Almeida, Leandro Soares Indrusiak
, Leandro Möller, Manfred Glesner, Gilles Sassatelli, Michel Robert, Fernando Moraes
:
Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework. SBCCI 2011: 185-190 - 2010
- [j41]Sanna Määttä, Leandro Möller, Leandro Soares Indrusiak
, Luciano Ost
, Manfred Glesner, Jari Nurmi
, Fernando Moraes
:
Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms. Int. J. Embed. Real Time Commun. Syst. 1(1): 86-101 (2010) - [j40]Faizal Arya Samman
, Thomas Hollstein
, Manfred Glesner:
Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip. IEEE Trans. Very Large Scale Integr. Syst. 18(7): 1067-1080 (2010) - [c280]Leandro Möller, Peter Fischer, Fernando Moraes
, Leandro Soares Indrusiak
, Manfred Glesner:
Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers. FPL 2010: 229-233 - [c279]Élvio Dutra, Manfred Glesner, Weiler Alves Finamore, Leandro Soares Indrusiak
:
Novel method of chaotic systems evaluation for implementations of encryption algorithms. ICT 2010: 89-96 - [c278]Sanna Määttä, Leandro Soares Indrusiak
, Luciano Ost
, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes
, Jari Nurmi
:
A case study of hierarchically heterogeneous application modelling using UML and Ptolemy II. SoC 2010: 68-71 - [c277]Leandro Möller, André Rodrigues, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner:
Instruction Set Simulator for MPSoCs based on NoCs and MIPS Processors. ReCoSoC 2010: 7-11 - [p2]Heiko Hinkelmann, Peter Zipf
, Manfred Glesner:
Dynamically Reconfigurable Systems for Wireless Sensor Networks. Dynamically Reconfigurable Systems 2010: 315-334
2000 – 2009
- 2009
- [j39]Peter Zipf
, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner:
A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips. Int. J. Reconfigurable Comput. 2009: 453970:1-453970:14 (2009) - [j38]Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak
, Manfred Glesner:
Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms. Int. J. Reconfigurable Comput. 2009: 851613:1-851613:15 (2009) - [j37]Alberto García Ortiz
, Leandro Soares Indrusiak
, Tudor Murgan, Manfred Glesner:
Low-Power Coding for Networks-on-Chip with Virtual Channels. J. Low Power Electron. 5(1): 77-84 (2009) - [j36]Heiko Hinkelmann, Peter Zipf
, Jia Li, Guifang Liu, Manfred Glesner:
On the design of reconfigurable multipliers for integer and Galois field multiplication. Microprocess. Microsystems 33(1): 2-12 (2009) - [j35]Faizal Arya Samman
, Thomas Hollstein
, Manfred Glesner:
Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management. VLSI Design 2009: 941701:1-941701:15 (2009) - [c276]Andre Guntoro
, Manfred Glesner:
A flexible floating-point wavelet transform and wavelet packet processor. DATE 2009: 1314-1319 - [c275]Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf
, Manfred Glesner:
An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. FPL 2009: 92-98 - [c274]Heiko Hinkelmann, Peter Zipf
, Manfred Glesner:
Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. FPL 2009: 359-366 - [c273]Haile Yu, Philip Heng Wai Leong
, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf
:
Towards a unique FPGA-based identification circuit using process variations. FPL 2009: 397-402 - [c272]Thomas C. P. Chau, S. Man Ho Ho, Philip Heng Wai Leong
, Peter Zipf
, Manfred Glesner:
Generation of Synthetic Floating-Point benchmark circuits. IPDPS 2009: 1-9 - [c271]Sanna Määttä, Leandro Soares Indrusiak
, Luciano Ost
, Leandro Möller, Manfred Glesner, Fernando Gehm Moraes
, Jari Nurmi
:
Characterising embedded applications using a UML profile. SoC 2009: 172-175 - [c270]Petru Bogdan Bacinschi, Manfred Glesner:
A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures. VLSI-SoC 2009: 156-180 - 2008
- [j34]Radu Dogaru, Manfred Glesner:
A fast and compact classifier based on sorting in an iteratively expanded input space. Int. J. Intell. Syst. 23(5): 607-618 (2008) - [c269]Andre Guntoro
, Manfred Glesner:
Low-latency VLSI architecture of a 3-input floating-point adder. APCCAS 2008: 180-183 - [c268]Andre Guntoro
, Massoud Momeni, Hans-Peter Keil, Manfred Glesner:
High-performance floating-point VLSI architecture of lifting-based forward and inverse wavelet transforms. APCCAS 2008: 457-460 - [c267]Hans-Peter Keil, Massoud Momeni, Andre Guntoro
, Alberto García Ortiz, Manfred Glesner:
A novel leakage-estimation method for input-vector control. APCCAS 2008: 570-573 - [c266]Massoud Momeni, Andre Guntoro
, Hans-Peter Keil, Manfred Glesner:
Impact of circuit nonidealities on the implementation of switched-capacitor resonators. APCCAS 2008: 1624-1627 - [c265]Andre Guntoro
, Manfred Glesner:
Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters. ASAP 2008: 299-304 - [c264]Massoud Momeni, Petru Bogdan Bacinschi, Manfred Glesner:
Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation. DATE 2008: 688-693 - [c263]Petru Bogdan Bacinschi, Tudor Murgan, Klaus Koch, Manfred Glesner:
An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs. DATE 2008: 698-703 - [c262]Faizal Arya Samman
, Thomas Hollstein
, Manfred Glesner:
Multicast Parallel Pipeline Router Architecture for Network-on-Chip. DATE 2008: 1396-1401 - [c261]Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig
, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf
, Manfred Glesner:
Coarse-grained reconfiguration. FPL 2008: 349 - [c260]Heiko Hinkelmann, Peter Zipf
, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll:
Application-specific reconfigurable processors. FPL 2008: 350 - [c259]Andre Guntoro
, Manfred Glesner:
A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor. FPL 2008: 479-482 - [c258]Andre Guntoro
, Manfred Glesner:
High-performance fpga-based floating-point adder with three inputs. FPL 2008: 627-630 - [c257]Heiko Hinkelmann, Peter Zipf
, Manfred Glesner:
A scalable reconfiguration mechanism for fast dynamic reconfiguration. FPT 2008: 145-152 - [c256]Peter Zipf
, Heiko Hinkelmann, Hui Shao, Radu Dogaru, Manfred Glesner:
An area-efficient FPGA realisation of a codebook-based image compression method. FPT 2008: 349-352 - [c255]Enkhbold Ochirsuren, Leandro Soares Indrusiak
, Manfred Glesner:
An Actor-Oriented Group Mobility Model for Wireless Ad Hoc Sensor Networks. ICDCS Workshops 2008: 174-179 - [c254]Andre Guntoro
, Hans-Peter Keil, Manfred Glesner:
High-Speed Configurable VLSI Architecture of a General Purpose Lifting-Based Discrete Wavelet Processor. ICETE (Selected Papers) 2008: 318-330 - [c253]Enkhbold Ochirsuren, Heiko Hinkelmann, Leandro Soares Indrusiak
, Manfred Glesner:
TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor. DIPES 2008: 161-170 - [c252]Faizal Arya Samman
, Thomas Hollstein
, Manfred Glesner:
Flexible parallel pipeline network-on-chip based on dynamic packet identity management. IPDPS 2008: 1-8 - [c251]Sujan Pandey, Rolf Drechsler
, Tudor Murgan, Manfred Glesner:
Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS 2008: 2989-2992 - [c250]Leandro Soares Indrusiak
, Luciano Ost
, Leandro Möller, Fernando Moraes
, Manfred Glesner:
Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects. ISVLSI 2008: 491-494 - [c249]Alberto García Ortiz
, Leandro Soares Indrusiak
, Tudor Murgan, Manfred Glesner:
PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels. PATMOS 2008: 219-228 - [c248]Heiko Hinkelmann, Andreas Reinhardt, Manfred Glesner:
A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support. IEEE International Workshop on Rapid System Prototyping 2008: 82-88 - [c247]Christopher Spies, Peter Zipf
, Manfred Glesner, Harald Klingbeil
:
Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II. IEEE International Workshop on Rapid System Prototyping 2008: 196-202 - [c246]Luciano Ost
, Fernando Gehm Moraes
, Leandro Möller, Leandro Soares Indrusiak
, Manfred Glesner, Sanna Määttä, Jari Nurmi
:
A simplified executable model to evaluate latency and throughput of networks-on-chip. SBCCI 2008: 170-175 - [c245]Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak
, Manfred Glesner:
Enabling self-reconfiguration on a video processing platform. SIES 2008: 19-26 - [c244]Sanna Määttä, Leandro Soares Indrusiak
, Luciano Ost
, Leandro Möller, Jari Nurmi
, Manfred Glesner, Fernando Moraes
:
Validation of executable application models mapped onto network-on-chip platforms. SIES 2008: 118-125 - [c243]Andre Guntoro, Hans-Peter Keil, Manfred Glesner:
Configurable VLSI Architecture of a General Purpose Lifting-based Wavelet Processor. SIGMAP 2008: 69-75 - [c242]Andre Guntoro
, Manfred Glesner:
A Flexible Floating-Point Wavelet Processor. SITIS 2008: 403-410 - [c241]Andre Guntoro
, Manfred Glesner:
A Lifting-Based Discrete Wavelet Transform and Discrete Wavelet Packet Processor with Support for Higher Order Wavelet Filters. VLSI-SoC (Selected Papers) 2008: 154-173 - [p1]Manfred Glesner, Tudor Murgan, Thomas Hollstein:
Hardware Based Rapid Prototyping. Wiley Encyclopedia of Computer Science and Engineering 2008 - 2007
- [j33]Thomas Hollstein
, Manfred Glesner:
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms. Comput. Electr. Eng. 33(4): 310-319 (2007) - [j32]Heiko Hinkelmann, Peter Zipf
, Manfred Glesner, Thilo Pionteck
:
Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). it Inf. Technol. 49(3): 174- (2007) - [j31]Alberto García Ortiz, Tudor Murgan, Manfred Glesner:
Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems. J. Low Power Electron. 3(2): 189-198 (2007) - [j30]Leandro Soares Indrusiak
, Manfred Glesner, Ricardo Reis:
On the Evolution of Remote Laboratories for Prototyping Digital Electronic Systems. IEEE Trans. Ind. Electron. 54(6): 3069-3077 (2007) - [j29]Sujan Pandey, Manfred Glesner:
Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. IEEE Trans. Very Large Scale Integr. Syst. 15(10): 1111-1124 (2007) - [c240]Leandro Soares Indrusiak
, Andreas Thuy, Manfred Glesner:
Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns. DATE 2007: 301-306 - [c239]Peter Zipf
, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume
, Tobias G. Noll:
A Power Estimation Model for an FPGA-based Softcore Processor. FPL 2007: 171-176 - [c238]Heiko Hinkelmann, Peter Zipf
, Manfred Glesner:
A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks. FPT 2007: 313-316 - [c237]Mihail Petrov, Manfred Glesner:
A Scalable Resampling Architecture. GLOBECOM 2007: 3102-3106 - [c236]Mihail Petrov, Manfred Glesner:
An Efficient Fractional-Rate Interpolation Architecture. GLOBECOM 2007: 4554-4558 - [c235]José Carlos S. Palma, Leandro Soares Indrusiak
, Fernando Gehm Moraes
, Ricardo Reis, Manfred Glesner:
Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes. ICECS 2007: 1007-1010 - [c234]José Carlos S. Palma, Leandro Soares Indrusiak
, Fernando Gehm Moraes
, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis:
Inserting Data Encoding Techniques into NoC-Based Systems. ISVLSI 2007: 299-304 - [c233]Peter Zipf, Yang Qiao, Manfred Glesner:
Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen. MBMV 2007: 253-262 - [c232]Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner:
On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. PATMOS 2007: 242-254 - [c231]Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, Petru Bogdan Bacinschi, Manfred Glesner:
Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling. ReCoSoC 2007: 7-14 - [c230]Kurt Franz Ackermann, Leandro Soares Indrusiak, Manfred Glesner:
System Level Design of a Dynamically Self-Reconfigurable Image Processing System. ReCoSoC 2007: 47-54 - [c229]Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner:
A Customizable LEON2-Based VLIW Processor. ReCoSoC 2007: 55-60 - [c228]Heiko Hinkelmann, Tudor Murgan, Guifang Liu, Peter Zipf, Manfred Glesner:
On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. ReCoSoC 2007: 185-191 - [c227]Leandro Soares Indrusiak
, Manfred Glesner:
Specification of alternative execution semantics of UML sequence diagrams within actor-oriented models. SBCCI 2007: 330-335 - [e8]Gilles Sassatelli, Manfred Glesner, Christophe Bobda, Pascal Benoit:
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007. Univ. Montpellier II 2007, ISBN 2-9517461-3-X [contents] - 2006
- [c226]Heiko Hinkelmann, Peter Zipf
, Manfred Glesner:
Design Concepts for a Dynamically ReconfigurableWireless Sensor Node. AHS 2006: 436-441 - [c225]Andre Guntoro
, Peter Zipf
, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner:
Implementation of Realtime and Highspeed Phase Detector on FPGA. ARC 2006: 1-11 - [c224]Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
A metric for the energy-efficiency of dynamically reconfigurable systems. ARCS Workshops 2006: 152-161 - [c223]Sujan Pandey, Manfred Glesner:
Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint. DAC 2006: 663-668 - [c222]Oliver Soffke, Peter Zipf
, Tudor Murgan, Manfred Glesner:
A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits. DATE 2006: 632-637 - [c221]Andreas Thuy, Leandro Soares Indrusiak, Manfred Glesner:
Applying Communication Patterns to Actor-Oriented Models. FDL 2006: 407-409 - [c220]Heiko Hinkelmann, Andreas Gunberg, Peter Zipf
, Leandro Soares Indrusiak
, Manfred Glesner:
Multitasking Support for Dynamically Reconfig Urable Systems. FPL 2006: 1-6 - [c219]Sujan Pandey, Manfred Glesner:
Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture. FPL 2006: 1-6 - [c218]Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner:
A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects. ICCAD 2006: 323-328 - [c217]Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier:
Reduction of Crosstalk Pessimism using Tendency Graph Approach. ICCD 2006: 50-55 - [c216]Sujan Pandey, Manfred Glesner:
Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique. ISCAS 2006 - [c215]Romualdo Begale Prudencio, Leandro Soares Indrusiak
, Manfred Glesner:
An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard. ISVLSI 2006: 77-84 - [c214]José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak
, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes
:
Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. ISVLSI 2006: 426-427 - [c213]Leandro Soares Indrusiak, Manfred Glesner:
An Actor-Oriented Model-Based Design Flow for Systems-on-Chip. MBEES 2006: 65-74 - [c212]Peter Zipf, Volker Hampel, Manfred Glesner, Thilo Pionteck:
Eine Scheduling Heuristik zur Minimierung der Verlustleistung. MBMV 2006: 51-60 - [c211]Tudor Murgan, Petru Bogdan Bacinschi, Alberto García Ortiz, Manfred Glesner:
Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. PATMOS 2006: 169-180 - [c210]Clemens Schlachta, Manfred Glesner:
A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages. PATMOS 2006: 563-572 - [c209]José Carlos S. Palma, Leandro Soares Indrusiak
, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis:
Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. PATMOS 2006: 603-613 - [c208]Heiko Hinkelmann, Peter Zipf, Manfred Glesner:
A Concept for a Profile-based Dynamic Reconfiguration Mechanism. ReCoSoC 2006: 105-110 - [c207]Hua Zhong, Leandro Soares Indrusiak, Heiko Hinkelmann, Manfred Glesner:
Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms. ReCoSoC 2006: 160-167 - [c206]Kurt Franz Ackermann, Friedhelm Mayer, Leandro Soares Indrusiak, Manfred Glesner:
Adaptable Image Processing System based on FPGA Modular Multi Kernel Instantiations. ReCoSoC 2006: 183-188 - [c205]Sujan Pandey, Nurten Utlu, Manfred Glesner:
Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture. VLSI-SoC 2006: 222-227 - [c204]Sujan Pandey, Tudor Murgan, Manfred Glesner:
Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis. VLSI-SoC 2006: 296-301 - [c203]Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner:
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. VLSI-SoC 2006: 302-307 - [e7]Gilles Sassatelli, Leandro Soares Indrusiak, Manfred Glesner, Lionel Torres:
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006. Univ. Montpellier II 2006, ISBN 2-9517461-2-1 [contents] - [e6]Manfred Glesner, Ricardo Augusto da Luz Reis, Leandro Soares Indrusiak
, Vincent John Mooney III, Hans Eveking:
VLSI-SOC: From Systems to Chips - IFIP TC 10/ WG 10.5 Twelfth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC 2003), December 1-3, 2003, Darmstadt, Germany. IFIP 200, Springer 2006, ISBN 978-0-387-33402-8 [contents] - [i1]Peter Zipf, Manfred Glesner:
Towards an Automated Design of Application-specific Reconfigurable Logic. Dynamically Reconfigurable Architectures 2006 - 2005
- [j28]Cristian Chitu, Manfred Glesner:
An FPGA implementation of the AES-Rijndael in OCB/ECB modes of operation. Microelectron. J. 36(2): 139-146 (2005) - [c202]Heiko Hinkelmann, Thilo Pionteck, Oliver Kleine, Manfred Glesner:
Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten. ARCS Workshops 2005: 45-51 - [c201]Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici, Adrian M. Ionescu, Oliver Soffke, Peter Zipf
, Manfred Glesner, Antonio Rubio:
CONAN - A Design Exploration Framework for Reliable Nano-Electronics. ASAP 2005: 260-267 - [c200]Peter Zipf
, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner:
Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. FPL 2005: 329-334 - [c199]Peter Zipf
, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner:
A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. FPL 2005: 335-340 - [c198]Sujan Pandey, Manfred Glesner, Max Mühlhäuser:
On-Chip Communication Topology Synthesis for a Shared Memory Architecture. FPL 2005: 374-379 - [c197]Mihail Petrov, Manfred Glesner:
Optimal FFT Architecture Selection for OFDM Receivers on FPGA. FPT 2005: 313-314 - [c196]Mihail Petrov, Manfred Glesner:
A State-Serial Viterbi Decoder Architecture for Digital Radio on FPGA. FPT 2005: 323-324 - [c195]Peter Zipf, Oliver Soffke, Michael Velten, Manfred Glesner:
Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC. GI Jahrestagung (1) 2005: 329-333 - [c194]Clemens Schlachta, Oliver Soffke, Peter Zipf, Manfred Glesner:
Eine weiterentwickelte quasi-statische adiabatische Logikfamilie. GI Jahrestagung (1) 2005: 448 - [c193]Martin K. F. Schafer, Thomas Hollstein
, Heiko Zimmer, Manfred Glesner:
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. ICCAD 2005: 238-245 - [c192]Abdulfattah Mohammad Obeid, Tudor Murgan, Abdelouahid Taadou, Manfred Glesner:
HW/SW design and realization of a size-reconfigurable DCT accelerator. ICECS 2005: 1-4 - [c191]Heiko Zimmer, Stefan Zink, Thomas Hollstein
, Manfred Glesner:
Buffer-Architecture Exploration for Routers in a Hierarchical Network-on-Chip. IPDPS 2005 - [c190]Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser
:
High level hardware/software communication estimation in shared memory architecture. ISCAS (1) 2005: 37-40 - [c189]Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner:
A linear model for high-level delay estimation in VDSM on-chip interconnects. ISCAS (2) 2005: 1078-1081 - [c188]A. Petrov, Tudor Murgan, Peter Zipf
, Manfred Glesner:
Functional modeling techniques for a wireless LAN OFDM transceiver. ISCAS (4) 2005: 3970-3973 - [c187]Diego Fernando Jimenez Orostegui, Leandro Soares Indrusiak
, Manfred Glesner:
Proxy-Based Integration of Reconfigurable Hardware Within Simulation Environments: Improving E-Learning Experience in Microelectronics. MSE 2005: 59-60 - [c186]Peter Zipf, Claude Stötzler, Manfred Glesner:
Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model. ReCoSoC 2005: 53-58 - [c185]Leandro Soares Indrusiak, Manfred Glesner:
Experiences on Actor-oriented Design of Reconfigurable Systems. ReCoSoC 2005: 79-84 - [c184]Thomas Hollstein, Sujan Pandey, Manfred Glesner:
Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. ReCoSoC 2005: 85-92 - [c183]Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel:
Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. ReCoSoC 2005: 151-156 - [c182]Leandro Soares Indrusiak, Romualdo Begale Prudencio, Manfred Glesner:
Modeling and Prototyping of Communication Systems Using Java: A Case Study. IEEE International Workshop on Rapid System Prototyping 2005: 225-231 - [c181]Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf
:
Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. SAMOS 2005: 12-21 - [c180]Sujan Pandey, Manfred Glesner, Max Mühlhäuser:
Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture. SBCCI 2005: 230-235 - [c179]Élvio Dutra, Leandro Soares Indrusiak, Manfred Glesner:
Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator. SBCCI 2005: 242-247 - [c178]Thilo Pionteck
, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner:
On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction. VLSI-SoC 2005: 283-297 - [e5]Gilles Sassatelli, Manfred Glesner, Lionel Torres, Leandro Soares Indrusiak, Thomas Hollstein:
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005. Univ. Montpellier II 2005, ISBN 2-9517-4611-3 [contents] - 2004
- [j27]Oliver Mitea, Manfred Glesner:
A power-constrained design strategy for CMOS tuned low noise amplifiers. Microelectron. Reliab. 44(5): 877-883 (2004) - [j26]Leandro Soares Indrusiak, Ricardo A. L. Reis, Manfred Glesner:
Um Framework de Apoio à Colaboração no Projeto Distribuído de Sistemas Integrados. RITA 11(2): 49-74 (2004) - [c177]Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Lukusa D. Kabulepa, Manfred Glesner:
Integration dynamisch rekonfigurierbarer Funktionseinheiten in Prozessoren. ARCS Workshops 2004: 155-164 - [c176]Manfred Glesner, Thomas Hollstein, Leandro Soares Indrusiak, Peter Zipf
, Thilo Pionteck, Mihail Petrov, Heiko Zimmer, Tudor Murgan:
Reconfigurable platforms for ubiquitous computing. Conf. Computing Frontiers 2004: 377-389 - [c175]Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf
, Manfred Glesner, Ulrich Heinkel, Jörg Pleickhardt, Bernd Bleisteiner:
Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. Conf. Computing Frontiers 2004: 404-418 - [c174]Thilo Pionteck
, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner:
On the design of a function-specific reconfigurable: hardware accelerator for the MAC-layer in WLANs. FPGA 2004: 258 - [c173]Ralf Ludewig, Oliver Soffke, Peter Zipf
, Manfred Glesner, Kong-Pang Pun, Kuen Hung Tsoi, Kin-Hong Lee, Philip Heng Wai Leong
:
IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. FPL 2004: 526-535 - [c172]Mihail Petrov, Tudor Murgan, Frank May, Martin Vorbach, Peter Zipf, Manfred Glesner:
The XPP Architecture and Its Co-simulation Within the Simulink Environment. FPL 2004: 761-770 - [c171]Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner:
A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals. FPL 2004: 1090-1092 - [c170]Thilo Pionteck, Thorsten Staake, Thomas Stiefmeier, Lukusa D. Kabulepa, Manfred Glesner:
Design of a reconfigurable AES encryption/decryption engine for mobile terminals. ISCAS (2) 2004: 545-548 - [c169]Mihail Petrov, Tudor Murgan, Abdulfattah Mohammad Obeid, Cristian Chitu, Peter Zipf, Jörg Brakensiek, Manfred Glesner:
Dynamic power optimization of the trace-back process for the Viterbi algorithm. ISCAS (2) 2004: 721-724 - [c168]Peter Zipf, Claude Stötzler, Manfred Glesner:
A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. ISVLSI 2004: 266-267 - [c167]Tudor Murgan, Mihail Petrov, Mateusz Majer, Peter Zipf, Manfred Glesner, Ulrich Heinkel:
Flexible Overhead Processing Architectures for G.709 Optical Transport Networks. MBMV 2004: 156-164 - [c166]Peter Zipf, Heiko Hinkelmann, Adeel Ashraf, Thomas Hollstein, Manfred Glesner:
An Asynchronous Switch Implmentation for Systems-on-a-Chip. MBMV 2004: 224-231 - [c165]Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner:
On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects. PATMOS 2004: 819-828 - [c164]Alberto García Ortiz, Tudor Murgan, Manfred Glesner:
Moment-Based Estimation of Switching Activity for Correlated Distributions. PATMOS 2004: 859-868 - [c163]Ralf Ludewig, Thomas Hollstein, Falko Schütz, Manfred Glesner:
Rapid Prototyping of an Integrated Testing and Debugging Unit. IEEE International Workshop on Rapid System Prototyping 2004: 187-192 - [c162]Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis:
Accurate capture of timing parameters in inductively-coupled on-chip interconnects. SBCCI 2004: 117-122 - [c161]Peter Zipf
, Heiko Hinkelmann, Adeel Ashraf, Manfred Glesner:
A switch architecture and signal synchronization for GALS system-on-chips. SBCCI 2004: 210-215 - [c160]Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis:
Lookup-based Remote Laboratory for FPGA Digital Design Prototyping. VIRTUAL-LAB 2004: 3-11 - 2003
- [j25]Thilo Pionteck
, Lukusa D. Kabulepa, Manfred Glesner:
On the Rapid Prototyping of Equalizers for OFDM Systems. Des. Autom. Embed. Syst. 8(4): 283-295 (2003) - [j24]Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Manfred Glesner:
Hardware-Assisted Signal Activity Analysis for Power Estimation in Rapid Prototyped Systems. Des. Autom. Embed. Syst. 8(4): 297-308 (2003) - [c159]Leandro Soares Indrusiak, Florian Lubitz, Ricardo Augusto da Luz Reis, Manfred Glesner:
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues. DATE 2003: 10940-10945 - [c158]Leandro Soares Indrusiak, Ricardo Reis, Manfred Glesner:
Supporting Consistency Control between Functional and Structural Views in Interface-based Design Models. FDL 2003: 364-373 - [c157]Stephan Bingemer
, Peter Zipf
, Manfred Glesner:
A granularity-based classification model for systems-on-a-chip. FPGA 2003: 239 - [c156]Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf
, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek:
Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. FPL 2003: 1111-1114 - [c155]Chun Hok Ho, Kuen Hung Tsoi, Jackson H. C. Yeung, Yuet Ming Lam, Kin-Hong Lee, Philip Heng Wai Leong
, Ralf Ludewig, Peter Zipf
, Alberto García Ortiz, Manfred Glesner:
Arbitrary function approximation in HDLs with application to the N-body problem. FPT 2003: 84-91 - [c154]Thilo Pionteck
, Lukusa D. Kabulepa, Clemens Schlachta, Manfred Glesner:
Reconfiguration requirements for high speed wireless communication systems. FPT 2003: 118-125 - [c153]Alberto García Ortiz, Lukusa D. Kabulepa, Tudor Murgan, Manfred Glesner:
Moment-Based Power Estimation in Very Deep Submicron Technologies. ICCAD 2003: 107-112 - [c152]Octavian Mitrea, Cosmin Popa, Anca Manuela Manolescu, Manfred Glesner:
A linearization technique for radio frequency CMOS Gilbert-type mixers. ICECS 2003: 1086-1089 - [c151]Octavian Mitrea, Juan Jesús Ocampo Hidalgo, Manfred Glesner:
A low-IF architecture for dual-standard GSM/UMTS fully integrated receivers. ICECS 2003: 1101-1104 - [c150]Abdulfattah Mohammad Obeid, Alberto García Ortiz, Mihail Petrov, Manfred Glesner:
A multi-path high speed Viterbi decoder. ICECS 2003: 1160-1163 - [c149]Radu Dogaru, Ioana Dogaru, Manfred Glesner:
Compact image compression using simplicial and ART neural systems with mixed signal implementations. ISCAS (5) 2003: 689-692 - [c148]Leandro Soares Indrusiak, Manfred Glesner, Ricardo Augusto da Luz Reis, Giuliana Alcántara, Stefan Hoermann, Ralf Steinmetz:
Reducing Authoring Costs of Online Training in Microelectronics Design by Reusing Design Documentation Content. MSE 2003: 57-58 - [c147]Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner:
Switching Activity Estimation in Non-linear Architectures. PATMOS 2003: 269-278 - [c146]Thilo Pionteck
, A. Garcya, Lukusa D. Kabulepa, Manfred Glesner:
The requirement for flexibility in IP-based designs increasesHardware Evaluation of Low Power Communication Mechanisms for Transport-Triggered Architectures. IEEE International Workshop on Rapid System Prototyping 2003: 141-147 - [c145]Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Juan Jesús Ocampo Hidalgo
, Manfred Glesner:
Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems. IEEE International Workshop on Rapid System Prototyping 2003: 172-178 - [c144]Thomas Hollstein
, Ralf Ludewig, Heiko Zimmer, Christoph Mager, Simon Hohenstern, Manfred Glesner:
Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs. VLSI-SoC (Selected Papers) 2003: 39-54 - [c143]Thomas Hollstein, Ralf Ludewig, Christoph Mager, Peter Zipf, Manfred Glesner:
A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. VLSI-SOC 2003: 44-49 - [c142]Cristian Chitu, Manfred Glesner:
High Performance of an AES-Rijndael ASIC working in OCB/ECB Modes of Operation. VLSI-SOC 2003: 62-67 - [c141]Thilo Pionteck
, Lukusa D. Kabulepa, Manfred Glesner:
Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans. VLSI-SoC (Selected Papers) 2003: 149-164 - [c140]Thilo Pionteck, Lukusa D. Kabulepa, Manfred Glesner:
Exploring the Capabilities of Reconfigurable Hardware for OFDM-based WLANs. VLSI-SOC 2003: 161-166 - [c139]Mihail Petrov, Abdulfattah Mohammad Obeid, Tudor Murgan, Peter Zipf, Jörg Brakensiek, Bernard Ölkrug, Manfred Glesner:
An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. VLSI-SOC 2003: 167- - [c138]Radu Dogaru, Cristian Chitu, Manfred Glesner:
A Versatile Cellular Neural Circuit Based on a Multi-nested Approach: Functional Capabilities and Applications. VLSI-SOC 2003: 356-361 - [c137]Stephan Bingemer, Peter Zipf, Manfred Glesner:
An Integrated Model Bridging the Gap between Technology and Economy. VLSI-SOC 2003: 442- - [c136]Alberto García Ortiz
, Tudor Murgan, Manfred Glesner:
Transition Activity Estimation for General Correlated Data Distributions. VLSI Design 2003: 440-445 - [e4]Manfred Glesner, Ricardo Augusto da Luz Reis, Hans Eveking, Vincent John Mooney III, Leandro Soares Indrusiak, Peter Zipf:
IFIP VLSI-SoC 2003, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Darmstadt, Germany, 1-3 December 2003. Technische Universität Darmstadt, Insitute of Microelectronic Systems 2003, ISBN 3-901882-17-0 [contents] - 2002
- [j23]Radu Dogaru, Pedro Julián
, Leon O. Chua, Manfred Glesner:
The simplicial neural cell and its mixed-signal circuit implementation: an efficient neural-network architecture for intelligent signal processing in portable multimedia applications. IEEE Trans. Neural Networks 13(4): 995-1008 (2002) - [c135]Jochen Mades, Manfred Glesner:
Regularization of hierarchical VHDL-AMS models using bipartite graphs. DAC 2002: 548-551 - [c134]Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner:
Estimation of Power Consumption in Encoded Data Buses. DATE 2002: 1103 - [c133]Leandro Soares Indrusiak
, Manfred Glesner, Ricardo Augusto da Luz Reis:
Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments. DATE 2002: 1130 - [c132]Chun Hok Ho, Philip Heng Wai Leong
, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf
, Alberto García Ortiz, Manfred Glesner:
Fly - A Modifiable Hardware Compiler. FPL 2002: 381-390 - [c131]Thilo Pionteck, Peter Zipf
, Lukusa D. Kabulepa, Manfred Glesner:
A Framework for Teaching (Re)Configurable Architectures in Student Projects. FPL 2002: 444-451 - [c130]Peter Zipf
, Manfred Glesner, Christine Bauer, Hans Wojtkowiak:
Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. FPL 2002: 586-595 - [c129]Cosmin Popa, Anca Manuela Manolescu, Octavian Mitrea, Manfred Glesner:
Low-power CMOS active resistor independent on the threshold voltage. ICECS 2002: 57-60 - [c128]Juan Jesús Ocampo Hidalgo, Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner:
Analysis of bandpass sigma-delta modulator architectures. ICECS 2002: 311-314 - [c127]Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner:
Power reduction techniques for an OFDM burst synchronization core. ISCAS (1) 2002: 265-268 - [c126]Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner:
Design of an efficient OFDM burst synchronization scheme. ISCAS (3) 2002: 449-452 - [c125]Jochen Mades, Diana Estévez Schwarz, Manfred Glesner:
A discrete algorithm for the regularization of hierarchical VHDL-AMS models. ISCAS (5) 2002: 477-480 - [c124]Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner:
Efficient estimation of signal transition activity in MAC architectures. ISLPED 2002: 319-322 - [c123]Chun Hok Ho, Monk-Ping Leong, Philip Heng Wai Leong
, Jürgen Becker, Manfred Glesner:
Rapid Prototyping of FPGA Based Floating Point DSP Systems. IEEE International Workshop on Rapid System Prototyping 2002: 19-24 - [c122]Abdulfattah Mohammad Obeid, Alberto García Ortiz, Ralf Ludewig, Manfred Glesner:
Prototyping of a High Performance Generic Viterbi Decoder. IEEE International Workshop on Rapid System Prototyping 2002: 42-47 - [c121]Thilo Pionteck
, N. Toender, Lukusa D. Kabulepa, Manfred Glesner, Tideya Kella:
On the Rapid Prototyping of Equalizers for OFDM Systems. IEEE International Workshop on Rapid System Prototyping 2002: 48-52 - [c120]Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Manfred Glesner:
Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System. IEEE International Workshop on Rapid System Prototyping 2002: 138- - [c119]Alberto García Ortiz, Tudor Murgan, Leandro Soares Indrusiak, Manfred Glesner:
Power Consumption in Point-to-Point Interconnect Architectures. SBCCI 2002: 155-162 - [e3]Manfred Glesner, Peter Zipf
, Michel Renovell:
Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings. Lecture Notes in Computer Science 2438, Springer 2002, ISBN 3-540-44108-5 [contents] - 2001
- [j22]Jürgen Becker, Manfred Glesner:
A Parallel Dynamically Reconfigurable Architecture Designed for Flexible Application-Tailored Hardware/Software Systems in Future Mobile Communication. J. Supercomput. 19(1): 105-127 (2001) - [c118]Jürgen Becker, Nicolas Liebau, Thilo Pionteck, Manfred Glesner:
Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. FPL 2001: 584-589 - [c117]Lukusa D. Kabulepa, Manfred Glesner, Tideya Kella:
Finite-precision analysis of an OFDM burst synchronization scheme. GLOBECOM 2001: 310-314 - [c116]Lukusa D. Kabulepa, Tideya Kella, Thilo Pionteck, Ralf Ludewig, Jürgen Becker, J. Plechinger, Manfred Glesner:
On the numerical accuracy of CORDIC-based frequency offset compensation in burst oriented OFDM systems. ICECS 2001: 1069-1072 - [c115]Leandro Soares Indrusiak, Jürgen Becker, Manfred Glesner, Ricardo Augusto da Luz Reis:
Distributed Collaborative Design over Cave2 Framework. VLSI-SOC 2001: 97-108 - [c114]Burkart Voss, Manfred Glesner:
A low power sinusoidal clock. ISCAS (4) 2001: 108-111 - [c113]Marc Theisen, Burkart Voss, Manfred Glesner:
Transformierende Synthese zur Verlustleistungsreduktion mittels Partitionierung. MBMV (1) 2001: 73-81 - [c112]Jochen Mades, Thomas Schneider, André Windisch, Thomas Hollstein
, Jürgen Becker, Manfred Glesner:
Concept of a Joint University/Industry Course for Mixed-Signal System-On-Chip Design. MSE 2001: 2-3 - [c111]Amar Mukherjee, Nitin Motgi, Jürgen Becker, A. Friebe, C. Habermann, Manfred Glesner:
Prototyping of Efficient Hardware Algorithms for Data Compression in Future Communication Systems. IEEE International Workshop on Rapid System Prototyping 2001: 58-63 - [c110]Jürgen Becker, Thilo Pionteck, Manfred Glesner:
Adaptive Systems-on-Chip: Architectures, Technologies and Applications. SBCCI 2001: 2-7 - [c109]Lukusa D. Kabulepa, Tideya Kella, Manfred Glesner:
Lower bound on the accuracy of the CORDIC-based frequency offset compensation in burst oriented OFDM systems. VTC Fall 2001: 839-842 - 2000
- [j21]Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. Des. Autom. Embed. Syst. 5(3-4): 351-363 (2000) - [j20]Frank-Michael Renner, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner:
Synthese von Kommunikationsstrukturen und architekturgenaues Rapid-Prototyping eingebetteter Echtzeitsysteme (Communication Synthesis and Architecture-Precise Rapid Prototyping of Embedded systems with Hard Real-Time Constraints). Informationstechnik Tech. Inform. 42(2): 27-33 (2000) - [j19]André Windisch, Thomas Schneider, Jochen Mades, Dieter Monjau, Manfred Glesner, Carsten Hammer, Wolfgang Ecker:
Eine flexible Simulationsumgebung für System-On-Chip Design (A Flexible Simulation Environment for System-On-Chip Design). Informationstechnik Tech. Inform. 42(5): 43- (2000) - [j18]Frank-Michael Renner, Karl-Josef Hoffmann, Richard Markert, Manfred Glesner:
Design methodology of application specific integrated circuits for mechatronic systems. Microprocess. Microsystems 24(2): 95-103 (2000) - [j17]Thuyen Le, Manfred Glesner:
Flexible architectures for DCT of variable-length targeting shape-adaptive transform. IEEE Trans. Circuits Syst. Video Technol. 10(8): 1489-1495 (2000) - [j16]Thuyen Le, Manfred Glesner:
A flexible and approximate computing approach for time-frequency distributions. IEEE Trans. Signal Process. 48(4): 1193-1196 (2000) - [c108]Thomas Schneider, Jochen Mades, Manfred Glesner, André Windisch, Wolfgang Ecker:
An Open VHDL-AMS Simulation Framework. BMAS 2000: 89-94 - [c107]Ahmad Alsolaim, Jürgen Becker, Manfred Glesner, Janusz A. Starzyk:
A dynamically reconfigurable system-on-a-chip architecture for future mobile digital signal processing. EUSIPCO 2000: 1-4 - [c106]Ahmad Alsolaim, Janusz A. Starzyk, Jürgen Becker, Manfred Glesner:
Architecture and Application of a Dynamically Reconfigurable Hardware Array for Future Mobile Communication Systems. FCCM 2000: 205-216 - [c105]Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Field Programmable Communication Emulation and Optimization for Embedded System Design. FPL 2000: 58-67 - [c104]Jürgen Becker, Thilo Pionteck, Manfred Glesner:
DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communications Applications. FPL 2000: 312-321 - [c103]Thuyen Le, Manfred Glesner:
Computing discrete time-frequency distributions using principal component filter bank. ICASSP 2000: 528-531 - [c102]Lukusa D. Kabulepa, Manfred Glesner:
Design of random number generators for the HIPERLAN/1 channel access mechanism. ICECS 2000: 234-237 - [c101]Burkart Voss, Manfred Glesner:
Adiabatic charging of long interconnects. ICECS 2000: 835-838 - [c100]Matthias Rychetsky, John Shawe-Taylor, Manfred Glesner:
Direct Bayes Point Machines. ICML 2000: 815-822 - [c99]Thuyen Le, Manfred Glesner:
Configurable VLSI-architectures for both standard DCT and shape-adaptive DCT in future MPEG-4 circuit implementations. ISCAS 2000: 461-464 - [c98]Thuyen Le, Manfred Glesner:
An efficient filter bank architecture for the cross-term reduced processing of discrete time-frequency distributions. ISCAS 2000: 519-522 - [c97]Ulrich Mayer, Jürgen Deicke, Manfred Glesner:
Statistical modelling of the MPEG-4 FlexMux. ISCAS 2000: 594-597 - [c96]Thuyen Le, Manfred Glesner:
Rotating stall analysis using signal-adapted filter bank and Cohen's time-frequency distributions. ISCAS 2000: 603-606 - [c95]Ulrich Mayer, Jürgen Deicke, Manfred Glesner:
Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams Connected to (R)CBR Channels. ISCC 2000: 298-303 - [c94]Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Communication Performance Estimation and Communication Synthesis for Architecture-precise Prototyping of Real-time Embedded Systems. MBMV 2000: 227-235 - [c93]Jürgen Becker, Manfred Glesner:
IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures. PDPTA 2000 - [c92]Jürgen Becker, Manfred Glesner, Ahmad Alsolaim, Janusz A. Starzyk:
Fast Communication Mechanisms in Coarse-grained Dynamically Reconfigurable Array Architectures. PDPTA 2000 - [c91]Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Automated Communication Synthesis for Architecture-Precise Rapid Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping 2000: 154-159 - [c90]Jürgen Becker, Lukusa D. Kabulepa, Frank-Michael Renner, Manfred Glesner:
Simulation and Rapid Prototyping of Flexible Systems-on-a-Chip for Future Mobile Communication Applications. IEEE International Workshop on Rapid System Prototyping 2000: 160- - [c89]Ulrich Mayer, Manfred Glesner:
Hardware Accelerated Estimation of Multiplexer-Introduced Loss for MPEG-4 Data Streams. IEEE International Workshop on Rapid System Prototyping 2000: 214- - [c88]Jochen Mades, Thomas Schneider, Manfred Glesner, André Windisch, Wolfgang Ecker:
A JAVA-Based Mixed-Signal Design Environment. SBCCI 2000: 301-306 - [c87]Jürgen Becker, Thilo Pionteck, Manfred Glesner:
An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband Processing. SBCCI 2000: 341-346
1990 – 1999
- 1999
- [j15]Manfred Glesner:
Mikrosystemtechnik. Informationstechnik Tech. Inform. 41(4): 5-6 (1999) - [j14]Alexander Steudel, Manfred Glesner:
Fuzzy segmented image coding using orthonormal bases and derivative chain coding. Pattern Recognit. 32(11): 1827-1841 (1999) - [j13]Michael Gasteier, Manfred Glesner:
Bus-based communication synthesis on system level. ACM Trans. Design Autom. Electr. Syst. 4(1): 1-11 (1999) - [c86]Marc Theisen, Jürgen Becker, Manfred Glesner, Tri Caohuu:
Parallel Hardware Compilation in Complex Hardware/Software Systems based on High-Level Code Transformations. ARCS 1999: 143-154 - [c85]Peter Gerken, Stefan Schultz, Gerald Knabe, Franco Casalino, Gianluca Di Cagno, Mauro Quaglia, Jean-Claude Dufourd, Souhila Boughoufalah, Frédéric Bouilhaguet, Michael Stepping, Thomas Bonse, Ulrich Mayer, Jürgen Deicke, Manfred Glesner:
MPEG-4 PC - Authoring and Playing of MPEG-4 Content for Local and Broadcast Applications. ECMAST 1999: 108-119 - [c84]Tri Caohuu, Thuy Trong Le, Manfred Glesner, Jürgen Becker:
Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. FPL 1999: 507-513 - [c83]Thuyen Le, Manfred Glesner:
A data-driven scheme for the approximated computing of alias-free generalized discrete time-frequency distributions. ICASSP 1999: 1717-1720 - [c82]Thuyen Le, Manfred Glesner:
A new flexible architecture for variable length DCT targeting shape-adaptive transform. ICASSP 1999: 1949-1952 - [c81]Thuyen Le, Manfred Glesner:
A flexible subband-based computation scheme for generalized discrete time-frequency distributions. ICECS 1999: 545-548 - [c80]Andreas Kirschbaum, Jürgen Becker, Manfred Glesner:
ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect. VLSI 1999: 659-670 - [c79]Radu Dogaru, Marinel Alangiu, Matthias Rychetsky, Manfred Glesner:
Perceptrons revisited: the addition of a non-monotone recursion greatly enhances their representation and classification properties. IJCNN 1999: 862-867 - [c78]Matthias Rychetsky, Stefan Ortmann, Manfred Glesner:
Support vector approaches for engine knock detection. IJCNN 1999: 969-974 - [c77]Matthias Rychetsky, Stefan Ortmann, Michael Ullmann, Manfred Glesner:
Accelerated training of support vector machines. IJCNN 1999: 998-1003 - [c76]Stefan Ortmann, Matthias Rychetsky, Manfred Glesner:
On the variance reduction of neural networks-experimental results for an automotive application. IJCNN 1999: 3356-3360 - [c75]Matthias Meixner, Jürgen Becker, Thomas Hollstein, Manfred Glesner:
Object-oriented Specification Approach for Synthesis of Hardware-/Software Systems. MBMV 1999: 182-191 - [c74]Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. IEEE International Workshop on Rapid System Prototyping 1999: 108-113 - [c73]Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimír Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner:
Design and Test of MEMs. VLSI Design 1999: 270- - 1998
- [j12]Jürgen Deicke, Ulrich Mayer, Manfred Glesner:
A client/server application as an example for MPEG-4 systems. Comput. Commun. 21(15): 1302-1309 (1998) - [j11]Stefan Ortmann, Manfred Glesner:
Development and Implementation of a Neural Knock Detector Using Constructive Learning Methods. Int. J. Uncertain. Fuzziness Knowl. Based Syst. 6(2): 127-138 (1998) - [j10]Hans-Jürgen Herpel, Manfred Glesner:
Rapid Prototyping of Real-Time Information Processing Units for Mechatronic Systems. Real Time Syst. 14(3): 269-291 (1998) - [c72]Thomas Hollstein, Jürgen Becker, Andreas Kirschbaum, Manfred Glesner:
HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. CODES 1998: 29-33 - [c71]Michael Gasteier, Manfred Glesner, Michael Münch:
Generation of Interconnect Topologies for Communication Synthesis. DATE 1998: 36-42 - [c70]Manfred Glesner, Matthias Rychetsky, Stefan Ortmann:
Advanced Hardware and Software Architectures for Computational Intelligence: Application to a Real World Problem. EUROMICRO 1998: 21068- - [c69]Thuyen Le, Thomas Dombek, Manfred Glesner:
Sound signature analysis using time-frequency signal processing: Application to active stall avoidance in axial compressors. EUSIPCO 1998: 1-4 - [c68]Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner:
Perspectives of Reconfigurable Computing in Research, Industry and Education. FPL 1998: 39-48 - [c67]Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
An FPFA Implementation of a Magnetic Bearing Controller for Mechatronic Applications. FPL 1998: 179-188 - [c66]Jürgen Deicke, Ulrich Mayer, A. Knoll, Manfred Glesner:
Flexible Multiplexing in MPEG-4 Systems. IDMS 1998: 83-94 - [c65]Andreas Kirschbaum, Jürgen Becker, Manfred Glesner:
A Reconfigurable Hardware-Monitor for Communication Analysis in Distributed Real-Time Systems. IPPS/SPDP Workshops 1998: 61-66 - [c64]Matthias Rychetsky, Stefan Ortmann, Manfred Glesner:
Pruning and Regularization Techniques for Feed Forward Nets Applied on a Real World Data Base. NC 1998: 603-609 - [c63]Stefan Ortmann, Matthias Rychetsky, Manfred Glesner:
Constructive Learning of a Sub-Feature Detector Network by Means of Prediction Risk Estimation. NC 1998: 995-1001 - [c62]Andreas Kirschbaum, Jürgen Becker, Manfred Glesner:
Run-Time Monitoring of Communication Activities in a Rapid Prototyping Environment. International Workshop on Rapid System Prototyping 1998: 52-57 - [c61]Andreas Kirschbaum, Stefan Ortmann, Manfred Glesner:
Rapid Prototyping of a Co-Processor Based Engine Knock Detection System. International Workshop on Rapid System Prototyping 1998: 124-129 - [c60]Jürgen Becker, Andreas Kirschbaum, Frank-Michael Renner, Manfred Glesner:
Internet-based Training of Reconfigurable Technologies. SBCCI 1998: 25-30 - [c59]Manfred Glesner, Andreas Kirschbaum:
State-of-the-Art in Rapid Prototyping. SBCCI 1998: 60-66 - 1997
- [j9]Harald Genther, Manfred Glesner:
Advanced data preprocessing using fuzzy clustering techniques. Fuzzy Sets Syst. 85(2): 155-164 (1997) - [j8]T. Waschek, S. Levegrün, M. van Kampen, Manfred Glesner, R. Engenhart-Cabillic, Wolfgang Schlegel:
Determination of target volumes for three-dimensional radiotherapy of cancer patients with a fuzzy system. Fuzzy Sets Syst. 89(3): 361-370 (1997) - [j7]Michael Münch, Norbert Wehn, Manfred Glesner:
An efficient ILP-based scheduling algorithm for control-dominated VHDL descriptions. ACM Trans. Design Autom. Electr. Syst. 2(4): 344-364 (1997) - [c58]Jean-Michel Karam, Bernard Courtois, Hicham Boutamine, P. Drake, András Poppe, Vladimír Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner:
CAD and Foundries for Microsystems. DAC 1997: 674-679 - [c57]Klaus Hofmann, Manfred Glesner, Nicu Sebe, Anca Manuela Manolescu, Santiago Marco, Josep Samitier, Jean-Michel Karam, Bernard Courtois:
Generation of the HDL-A-model of a micromembrane from its finite-element-description. ED&TC 1997: 108-112 - [c56]M. Lang, D. David, Manfred Glesner:
Automatic transfer of parametric FEM models into CAD-layout formats for top-down design of microsystems. ED&TC 1997: 200-204 - [c55]Thomas Hollstein
, Andreas Kirschbaum, Manfred Glesner:
A prototyping environment for fuzzy controllers. FPL 1997: 482-490 - [c54]Jürgen Deicke, Ulrich Mayer, Manfred Glesner:
An Object-Oriented Client/Server Architecture for Video-on-Demand Applications. IDMS 1997: 440-449 - [c53]Thuyen Le, Frank-Michael Renner, Manfred Glesner:
Hardware in-the-loop simulation-a rapid prototyping approach for designing mechatronics systems. IEEE International Workshop on Rapid System Prototyping 1997: 116-121 - [c52]Andreas Kirschbaum, Manfred Glesner:
Rapid prototyping of communication architectures. IEEE International Workshop on Rapid System Prototyping 1997: 136-141 - [e2]Wayne Luk, Peter Y. K. Cheung, Manfred Glesner:
Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings. Lecture Notes in Computer Science 1304, Springer 1997, ISBN 3-540-63465-7 [contents] - 1996
- [j6]Thomas Hollstein
, Saman K. Halgamuge
, Manfred Glesner:
Computer-aided design of fuzzy systems based on generic VHDL specifications. IEEE Trans. Fuzzy Syst. 4(4): 403-417 (1996) - [c51]Jean-Michel Karam, Bernard Courtois, András Poppe
, Klaus Hofmann, Márta Rencz, Manfred Glesner, Vladimír Székely:
Applied design and analysis of microsystems. ED&TC 1996: 528-532 - [c50]Ulrike Ober, Hans-Jürgen Herpel, Manfred Glesner:
CAPpartx: Computer Aided Prototyping Partitioning for Xilinx FPGAs, a Hierarchical Partitioning Tool for Rapid Prototyping. FPL 1996: 106-115 - [c49]Alexander Steudel, Manfred Glesner:
Image coding with fuzzy region-growing segmentation. ICIP (2) 1996: 955-958 - [c48]Radu Dogaru, A. T. Murgan, Stefan Ortmann, Manfred Glesner:
Searching for robust chaos in discrete time neural networks using weight space exploration. ICNN 1996: 688-693 - [c47]Michael Münch, Manfred Glesner, Norbert Wehn:
An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions. ISSS 1996: 45-50 - [c46]Michael Gasteier, Manfred Glesner:
Bus-Based Communication Synthesis on System-Level. ISSS 1996: 65-70 - [c45]Andreas Kirschbaum, Frank-Michael Renner, Alexander Wilmes, Manfred Glesner:
Rapid-Prototyping of a CAN-Bus Controller: A Case Study. RSP 1996: 146-151 - [e1]Reiner W. Hartenstein, Manfred Glesner:
Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 6th International Workshop on Field-Programmable Logic, FPL '96, Darmstadt, Germany, September 23-25, 1996, Proceedings. Lecture Notes in Computer Science 1142, Springer 1996, ISBN 3-540-61730-2 [contents] - 1995
- [j5]Saman K. Halgamuge
, Werner Pöchmüller, Manfred Glesner:
An alternative approach for generation of membership functions and fuzzy rules based on radial and cubic basis function networks. Int. J. Approx. Reason. 12(3-4): 279-298 (1995) - [j4]Saman K. Halgamuge
, Manfred Glesner:
Fuzzy neural networks: between functional equivalence and applicability. Int. J. Neural Syst. 6(2): 185-196 (1995) - [j3]Andreas König, Peter Windirsch, Michael Gasteier, Manfred Glesner:
Visual inspection in industrial manufacturing. IEEE Micro 15(3): 26-31 (1995) - [c44]Ulrike Ober, Manfred Glesner:
Multiway netlist partitioning onto FPGA-based board architecture. EURO-DAC 1995: 150-155 - [c43]U. Zahm, Thomas Hollstein, Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner:
Advanced Method for Industry Related Education with an FPGA Design Self-Learning Kit. FPL 1995: 241-250 - [c42]Hans-Jürgen Herpel, Ulrike Ober, Manfred Glesner:
Prototype Generation of Application-Specific Embedded Controllers for Microsystems. FPL 1995: 341-351 - [c41]Hans-Jürgen Herpel, Manfred Glesner, Horst Eggert, Wolfgang Süß, Martina Gorges-Schleuter, Wilfried Jakob:
Rapid prototyping in microsystems development. RSP 1995: 48-53 - [c40]Saman K. Halgamuge
, Christoph Grimm, Manfred Glesner:
A sub Bayesian nearest prototype neural network with fuzzy interpretability for diagnosis problems. SAC 1995: 445-449 - [c39]Thomas A. Runkler
, Manfred Glesner:
Multidimensional defuzzification - fast algorithms for the determination of crisp characteristic subsets. SAC 1995: 575-579 - [c38]Saman K. Halgamuge, Alain Brichard, Manfred Glesner:
Comparison of a heuristic method with a genetic algorithm for generation of compact rule based classifiers. SAC 1995: 580-585 - 1994
- [c37]Andreas König, Olaf Bulmahn, Manfred Glesner:
Systematic Methods for Multivariate Data Visualization and Numerical Assessment of Class Separability and Overlap in Automated Visual Industrial Quality Control. BMVC 1994: 1-10 - [c36]Michael Held, Manfred Glesner:
Generating compilers for generated datapaths. EURO-DAC 1994: 532-537 - [c35]Wolfgang Ecker, Manfred Glesner, Andreas Vombach:
Protocol merging: a VHDL-based method for clock cycle minimizing and protocol preserving scheduling of IO-operations. EURO-DAC 1994: 624-629 - [c34]Thomas Hollstein, Saman K. Halgamuge, Andreas Kirschbaum, Manfred Glesner:
Rapid-Prototyping von anwendungsspezifischen Fuzzy Controllern mit Field Programmable Gate Arrays. Fuzzy Days 1994: 8-14 - [c33]Hans-Jürgen Herpel, Michael Held, Manfred Glesner:
A Design Methodology for the Conceptual Design of Application Specific Digital Processors in Mechatronic Systems. HICSS (1) 1994: 78-86 - [c32]Hans-Jürgen Herpel, Michael Held, Manfred Glesner:
MCEMS Toolbox - A Hardware-in-the-Loop Simulation Environment for Mechatronic Systems. MASCOTS 1994: 356-357 - [c31]Saman K. Halgamuge, Manfred Glesner:
Fuzzy neural fusion techniques for industrial applications. SAC 1994: 136-141 - [c30]Thomas A. Runkler
, Manfred Glesner:
DECADE - fast centroid approximation defuzzification for real time fuzzy control applications. SAC 1994: 161-165 - [c29]Harald Genther, Manfred Glesner:
Automatic generation of a fuzzy classification system using fuzzy clustering methods. SAC 1994: 180-183 - 1993
- [c28]Hans-Jürgen Herpel, Michael Held, Manfred Glesner:
Real-Time System Prototyping Based on a Heterogeneous Multi-Processor Environment. RTS 1993: 62-67 - [c27]Peter Poechmueller, Manfred Glesner, Fang Longsen:
High-level synthesis transformations for programmable architectures. EURO-DAC 1993: 8-13 - [c26]Michael Gasteier, Norbert Wehn, Manfred Glesner:
Synthesis of complex VHDL operators. EURO-DAC 1993: 566-571 - [c25]Thomas A. Runkler, Manfred Glesner:
Approximative Synthese von Fuzzy - Controllern. Fuzzy Days 1993: 22-31 - [c24]Saman K. Halgamuge, Hans-Jürgen Herpel, Manfred Glesner:
Echtzeit Fahrbahnzustandserkennung mit Fuzzy-Neuronalen Netzen. Fuzzy Days 1993: 204-211 - [c23]Saman K. Halgamuge
, Werner Pöchmüller, Manfred Glesner:
A rule based prototype system for automatic classification in industrial quality control. ICNN 1993: 238-243 - [c22]Werner Pöchmüller, Manfred Glesner, H. Juergs:
Is LVQ really good for classification?-an interesting alternative. ICNN 1993: 1207-1212 - [c21]Andreas König, Harald Genther, Manfred Glesner:
Neural and associative modules in a hybrid dynamic system for visual industrial quality control. ICNN 1993: 1510-1515 - [c20]Norbert Wehn, Manfred Glesner, C. Vielhauer:
Estimating lower hardware bounds in high-level synthesis. VLSI 1993: 261-270 - 1992
- [c19]Werner Pöchmüller, Andreas König, Manfred Glesner:
Associative information processing: algorithms and system. ASAP 1992: 538-550 - [c18]Norbert Wehn, Hans-Jürgen Herpel, Thomas Hollstein, Peter Poechmueller, Manfred Glesner:
High-level synthesis in a rapid-prototype environment for mechatronic systems. EURO-DAC 1992: 188-193 - [c17]Peter Windirsch, Hans-Jürgen Herpel, A. Laudenbach, Manfred Glesner:
Application-specific microelectronics for mechatronic systems. EURO-DAC 1992: 194-199 - [c16]Peter Poechmueller, Hans-Jürgen Herpel, Manfred Glesner, Fang Longsen:
High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment. FPL 1992: 96-105 - 1991
- [c15]Norbert Wehn, Manfred Glesner:
A new approach to timing driven partitioning of combinational logic. Great Lakes Symposium on VLSI 1991: 96-101 - [c14]Peter Poechmueller, G. K. Sharma, Manfred Glesner:
A CAD tool for designing large, fault-tolerant VLSI arrays. Great Lakes Symposium on VLSI 1991: 132-137 - [c13]Hans-Jürgen Herpel, Peter Windirsch, Manfred Glesner, J. Führer, J. Busshardt:
A VLSI implementation of a state variable filter algorithm. Great Lakes Symposium on VLSI 1991: 138-143 - [c12]Peter Poechmueller, Manfred Glesner:
An approach for multilevel logic cell optimization in module generators. Great Lakes Symposium on VLSI 1991: 284-289 - [c11]Peter Poechmueller, Michael Held, Norbert Wehn, Manfred Glesner:
HADES-high-level architecture development and exploration system. Great Lakes Symposium on VLSI 1991: 342-343 - [c10]Peter Poechmueller, Manfred Glesner:
A New Approach for Designing Fault-Tolerant Array Processors. Fault-Tolerant Computing Systems 1991: 324-331 - [c9]Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner:
RAMSES-a rapid prototyping environment for embedded control applications. RSP 1991: 27-33 - [c8]Hans-Jürgen Herpel, Norbert Wehn, Manfred Glesner:
Verifikation mikroelektronischer Systeme zur Prozeßsteuerung durch schnelle Prototypenrealisierung. ASIM 1991: 567-572 - [c7]A. Laudenbach, Manfred Glesner, Norbert Wehn:
A VLSI System Design for the Control of High Performance Combustion Engines. VLSI 1991: 247-256 - 1990
- [j2]Werner Pöchmüller, Manfred Glesner:
Evaluation of state-of-the-art neural network customized hardware. Neurocomputing 2(5): 209-231 (1990) - [c6]Werner Pöchmüller, Manfred Glesner:
Handwritten pattern recognition with a binary associative memory. IJCNN 1990: 873-878 - [c5]Norbert Wehn, Manfred Glesner, A. Kister, S. Kastner:
Timing Driven Partitioning of Combinational Logic. Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme 1990: 42-51
1980 – 1989
- 1988
- [c4]Norbert Wehn, Manfred Glesner, K. Caesar, P. Mann, A. Roth:
A Defect-Tolerant and Fully Testable PLA. DAC 1988: 22-33 - [c3]Manfred Glesner, M. Huch, Peter A. Ivey, T. Midwinter, Gabriele Saucier, Jacques Trilhe:
Entwurf eines systolischen Arrays in Wafer Scale Technik für die digitale Signalverarbeitung. GI Jahrestagung (2) 1988: 75-91 - 1987
- [c2]Johannes Schuck, Norbert Wehn, Manfred Glesner, G. Kamp:
The ALGIC Silicon Compiler System: Implementation, Design Experience and Results. DAC 1987: 370-375 - 1986
- [j1]Norbert Wehn, Manfred Glesner:
Statische und dynamische CMOS-Schaltungstechniken im Vergleich. it Inf. Technol. 28(3): 142-149 (1986) - [c1]Manfred Glesner, Johannes Schuck, R. B. Steck:
SCAT - a new statistical timing verifier in a silicon compiler system. DAC 1986: 220-226
Coauthor Index
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