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ORCIDRolf Drechsler
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- affiliation: University of Bremen, Institute of Computer Science
- affiliation: German Research Centre for Artificial Intelligence (DFKI), Bremen
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2020 – today
- 2024
[j157]Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Arithmetic Circuits. Found. Trends Electron. Des. Autom. 14(3): 171-244 (2024)- [j156]Sajjad Parvin
, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Lower the RISC: Designing optical-probing-attack-resistant cores. Microprocess. Microsystems 111: 105121 (2024) - [j155]Sana Hassan Imam, Christopher A. Metz, Lars Hornuf, Rolf Drechsler:
Determining the Effect of Feedback Quality on User Engagement on Online Idea Crowdsourcing Platforms Using an AI model. Proc. ACM Hum. Comput. Interact. 8(CSCW2): 1-26 (2024) - [j154]Chandan Kumar Jha, Muhammad Hassan, Rolf Drechsler:
cecApprox: Enabling Automated Combinational Equivalence Checking for Approximate Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 71(7): 3282-3293 (2024) - [j153]Chandan Kumar Jha, Khushboo Qayyum, Kemal Çaglar Coskun, Simranjeet Singh, Muhammad Hassan, Rainer Leupers, Farhad Merchant, Rolf Drechsler:
veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 71(9): 4169-4179 (2024) - [j152]Mehran Goli, Rolf Drechsler:
Early SoCs Information Flow Policies Validation Using SystemC-Based Virtual Prototypes at the ESL. ACM Trans. Embed. Comput. Syst. 23(5): 67:1-67:20 (2024) - [j151]Kousik Bhunia, Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler:
ReSG: A Data Structure for Verification of Majority-based In-memory Computing on ReRAM Crossbars. ACM Trans. Embed. Comput. Syst. 23(6): 90:1-90:24 (2024) - [c745]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. ASPDAC 2024: 282-287 - [c744]Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler:
Security Coverage Metrics for Information Flow at the System Level. ASPDAC 2024: 945-950 - [c743]Christina Plump, Daniel Christopher Hoinkiss, Jörn Huber, Bernhard J. Berger, Matthias Günther, Christoph Lüth, Rolf Drechsler:
Finding the perfect MRI sequence for your patient - Towards an optimisation workflow for MRI-sequences. CEC 2024: 1-9 - [c742]Kemal Çaglar Coskun, Muhammad Hassan, Lars Hedrich, Rolf Drechsler:
Efficient Equivalence Checking of Nonlinear Analog Circuits using Gradient Ascent. DAC 2024: 51:1-51:6 - [c741]Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler:
Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. DAC 2024: 349:1-349:2 - [c740]Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler:
LLM-Guided Formal Verification Coupled with Mutation Testing. DATE 2024: 1-2 - [c739]Caroline Dominik, Rolf Drechsler:
Polynomial Formal Verification of Sequential Circuits. DATE 2024: 1-6 - [c738]Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler:
Dynamic Realization of Multiple Control Toffoli Gate. DATE 2024: 1-6 - [c737]Sajjad Parvin, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Hidden Cost of Circuit Design with RFETs. DATE 2024: 1-2 - [c736]Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler:
Complete and Efficient Verification for a RISC-V Processor Using Formal Verification. DATE 2024: 1-6 - [c735]Jan Zielasko, Rune Krauss, Marcel Merten, Rolf Drechsler:
Improving Virtual Prototype Driven Hardware Optimization by Merging Instruction Sequences. DDECS 2024: 73-78 - [c734]Luca Müller, Rolf Drechsler:
SAT can Ensure Polynomial Bounds for the Verification of Circuits with Limited Cutwidth. DSD 2024: 57-64 - [c733]Payam Habiby, Fatemeh Shirinzadeh, Sebastian Huhn, Rolf Drechsler:
A Multi-Objective Evolutionary Approach for Test Network Design. ETS 2024: 1-4 - [c732]Mohamed A. Nadeem, Chandan Kumar Jha, Rolf Drechsler:
Polynomial Formal Verification of Approximate Adders with Constant Cutwidth. ETS 2024: 1-6 - [c731]Bernhard Johannes Berger, Christina Plump, Lauren Paul, Rolf Drechsler:
EvoAl - Codeless Domain-Optimisation. GECCO Companion 2024: 1640-1648 - [c730]Helen Pfuhl, Lena Steinmann, Dirk Nowotka, Rolf Drechsler:
Aufbau einer überregionalen Data-Science-Community. INFORMATIK 2024: 2197-2203 - [c729]Khushboo Qayyum, Abhoy Kole, Kamalika Datta, Muhammad Hassan, Rolf Drechsler:
Exploring the Potential of Decision Diagrams for Efficient In-Memory Design Verification. ACM Great Lakes Symposium on VLSI 2024: 502-506 - [c728]Mohamed A. Nadeem, Rolf Drechsler:
Polynomial Formal Verification of Multi-Valued Logic Circuits within Constant Cutwidth Architectures. ISMVL 2024: 149-154 - [c727]Abhoy Kole, Kamalika Datta, Rolf Drechsler:
Design Automation Challenges and Benefits of Dynamic Quantum Circuit in Present NISQ Era and Beyond: (Invited Paper). ISVLSI 2024: 601-606 - [c726]Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li:
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. MLCAD 2024: 18:1-18:10 - [c725]Mohammad Reza Heidari Iman, Sallar Ahmadi-Pour, Rolf Drechsler, Tara Ghasempouri:
Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study. NorCAS 2024: 1-7 - [c724]Liam Hurwitz, Kamalika Datta, Abhoy Kole, Rolf Drechsler:
Is Simulation the only Alternative for Effective Verification of Dynamic Quantum Circuits? RC 2024: 201-217 - [c723]Abhoy Kole, Kamalika Datta, Rolf Drechsler:
Exploring the Potential of Dynamic Quantum Circuit for Improving Device Scalability. SOCC 2024: 1-5 - [c722]Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. VLSI-SoC 2024: 1-6 - [c721]Sneha Lahiri, Megha Kesh, Rupsa Mandal, Anirban Bhattacharjee, Sovan Bhattacharya, Dola Sinha, Chandan Bandyopadhyay, Laxmidhar Biswal, Robert Wille, Rolf Drechsler:
A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D. VLSID 2024: 306-311 - [c720]Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler:
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. VLSID 2024: 384-389 - [c719]Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana:
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. VLSID 2024: 565-570 - [c718]Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler:
Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic. VLSID 2024: 577-582 - [i30]Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler:
BinSym: Binary-Level Symbolic Execution using Formal Descriptions of Instruction Semantics. CoRR abs/2404.04132 (2024) - [i29]Simranjeet Singh, Ankit Bende, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Sachin B. Patkar, Farhad Merchant:
In-Memory Mirroring: Cloning Without Reading. CoRR abs/2407.02921 (2024) - [i28]Ruidi Qiu, Grace Li Zhang, Rolf Drechsler, Ulf Schlichtmann, Bing Li:
AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design. CoRR abs/2407.03891 (2024) - [i27]Bernhard J. Berger, Christina Plump, Rolf Drechsler:
EvoAl2048. CoRR abs/2408.16780 (2024) - [i26]Abhoy Kole, Mohammed E. Djeridane, Lennart Weingarten, Kamalika Datta, Rolf Drechsler:
qSAT: Design of an Efficient Quantum Satisfiability Solver for Hardware Equivalence Checking. CoRR abs/2409.03917 (2024) - 2023
- [j150]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. IEEE Embed. Syst. Lett. 15(4): 230-233 (2023) - [j149]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Specification-Based Symbolic Execution for Stateful Network Protocol Implementations in IoT. IEEE Internet Things J. 10(11): 9544-9555 (2023) - [j148]Kamalika Datta, Arighna Deb, Abhoy Kole, Rolf Drechsler:
Impact of sneak paths on in-memory logic design in memristive crossbars. it Inf. Technol. 65(1-2): 29-39 (2023) - [j147]Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler:
MARADIV: Library of MAGIC-Based Approximate Restoring Array Divider Benchmark Circuits for In-Memory Computing Using Memristors. IEEE Trans. Circuits Syst. II Express Briefs 70(7): 2635-2639 (2023) - [c717]Arighna Deb, Kamalika Datta, Muhammad Hassan, Saeideh Shirinzadeh, Rolf Drechsler:
Automated Equivalence Checking Method for Majority Based In-Memory Computing on ReRAM Crossbars. ASP-DAC 2023: 19-25 - [c716]Rune Krauss, Mehran Goli, Rolf Drechsler:
EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation. ASP-DAC 2023: 423-428 - [c715]Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler:
Trojan-D2: Post-Layout Design and Detection of Stealthy Hardware Trojans - A RISC-V Case Study. ASP-DAC 2023: 683-689 - [c714]Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Complex Circuits Using a Hybrid Proof Engine. Applicable Formal Methods for Safe Industrial Products 2023: 308-319 - [c713]Bernhard J. Berger, Christina Plump, Rolf Drechsler:
EVOAL: A Domain-Specific Language-Based Approach to Optimisation. CEC 2023: 1-10 - [c712]Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres, Rolf Drechsler:
Lo-RISK: Design of a Low Optical Leakage and High Performance RISC-V Core. COINS 2023: 1-4 - [c711]Niklas Bruns, Vladimir Herdt, Rolf Drechsler:
Processor Verification using Symbolic Execution: A RISC-V Case-Study. DATE 2023: 1-6 - [c710]Kemal Çaglar Coskun, Muhammad Hassan, Rolf Drechsler:
Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear Circuits. DATE 2023: 1-6 - [c709]Rolf Drechsler, Alireza Mahzoon:
Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex Circuits. DATE 2023: 1-2 - [c708]Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Floating Point Adders. DATE 2023: 1-2 - [c707]Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler:
Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network. DATE 2023: 1-6 - [c706]Sajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler:
FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical Probing. DATE 2023: 1-2 - [c705]Jens Trommer, Niladri Bhattacharjee, Thomas Mikolajick, Sebastian Huhn, Marcel Merten, Mohammed E. Djeridane, Muhammad Hassan, Rolf Drechsler, Shubham Rai, Nima Kavand, Armin Darjani, Akash Kumar, V. Sessi, M. Drescher, S. Kolodinski, M. Wiatr:
Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable Transistors. DATE 2023: 1-6 - [c704]Rune Krauss, Mehran Goli, Rolf Drechsler:
Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes. DDECS 2023: 73-78 - [c703]Marcel Merten, Muhammad Hassan, Rolf Drechsler:
Quality Assessment of Logic Locking Mechanisms using Pseudo-Boolean Optimization Techniques. DDECS 2023: 105-110 - [c702]Payam Habiby, Sebastian Huhn, Rolf Drechsler:
RC-IJTAG: A Methodology for Designing Remotely-Controlled IEEE 1687 Scan Networks. DFT 2023: 1-6 - [c701]Weiyan Zhang, Mehran Goli, Muhammad Hassan, Rolf Drechsler:
Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors. DSD 2023: 693-699 - [c700]Payam Habiby, Natalia Lylina, Chih-Hao Wang, Hans-Joachim Wunderlich, Sebastian Huhn, Rolf Drechsler:
Synthesis of IJTAG Networks for Multi-Power Domain Systems on Chips. ETS 2023: 1-6 - [c699]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
Increasing SAT-Resilience of Logic Locking Mechanisms using Formal Methods. ETS 2023: 1-6 - [c698]Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. FDL 2023: 1-8 - [c697]Christopher A. Metz, Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Hybrid PTX Analysis for GPU accelerated CNN inferencing aiding Computer Architecture Design. FDL 2023: 1-8 - [c696]Sören Tempel, Tobias Brandt, Christoph Lüth, Rolf Drechsler:
Minimally Invasive Generation of RISC-V Instruction Set Simulators from Formal ISA Models. FDL 2023: 1-8 - [c695]Jan Zielasko, Rolf Drechsler:
Virtual Prototype Driven Application Specific Hardware Optimization. FDL 2023: 1-8 - [c694]Marcel Merten, Rune Krauss, Rolf Drechsler:
Scalable Neuroevolution of Ensemble Learners. GECCO Companion 2023: 667-670 - [c693]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Repetitive Processes and Their Surrogate-Model Congruent Encoding for Evolutionary Algorithms - A Theoretic Proposal. GECCO Companion 2023: 2289-2296 - [c692]Lena Steinmann, Dirk Nowotka, Lea Oberländer, Helen Pfuhl, Heiner Stuckenschmidt, Rolf Drechsler:
Workshop: "Aktuelle Entwicklungen und Perspektiven (an Hochschulen) im Bereich Data Science". GI-Jahrestagung 2023: 73-80 - [c691]Tim Meywerk, Vladimir Herdt, Rolf Drechsler:
Coverage-Guided Fuzzing for Plan-Based Robotics. ICAART (2) 2023: 106-114 - [c690]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Fast and Accurate: Machine Learning Techniques for Performance Estimation of CNNs for GPGPUs. IPDPS Workshops 2023: 754-760 - [c689]Rolf Drechsler, Alireza Mahzoon:
Towards Polynomial Formal Verification of AI-Generated Arithmetic Circuits. ISDCS 2023: 1-4 - [c688]Rolf Drechsler, Martha Schnieber:
Automated Polynomial Formal Verification: Human-Readable Proof Generation. iSES 2023: 1-3 - [c687]Kamalika Datta, Rolf Drechsler:
Memristors: Device Modeling, Design and Verification. iSES 2023: 254-259 - [c686]Ece Nur Demirhan Coskun, Muhammad Hassan, Mehran Goli, Rolf Drechsler:
VAST: Validation of VP-based Heterogeneous Systems against Availability Security Properties using Static Information Flow Tracking. ISQED 2023: 1-8 - [c685]Lennart Weingarten, Alireza Mahzoon, Mehran Goli, Rolf Drechsler:
Polynomial Formal Verification of a Processor: A RISC-V Case Study. ISQED 2023: 1-7 - [c684]Sajjad Parvin, Mehran Goli, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler:
LAT-UP: Exposing Layout-Level Analog Hardware Trojans Using Contactless Optical Probing. ISVLSI 2023: 1-6 - [c683]Sana Hassan Imam, Christopher A. Metz, Lars Hornuf, Rolf Drechsler:
Classifying Crowdsouring Platform Users' Engagement Behaviour using Machine Learning and XAI. MuC (Workshopband) 2023 - [c682]Martha Schnieber, Rolf Drechsler:
Polynomial Formal Verification of KFDD Circuits. MEMOCODE 2023: 82-89 - [c681]Rolf Drechsler, Martha Schnieber:
Next-Generation Automatic Human-Readable Proofs Enabling Polynomial Formal Verification. MEMOCODE 2023: 122-125 - [c680]Lennart Weingarten, Kamalika Datta, Rolf Drechsler:
PolyMiR: Polynomial Formal Verification of the MicroRV32 Processor. NANOARCH 2023: 24:1-24:6 - [c679]Kamalika Datta, Arighna Deb, Fatemeh Shirinzadeh, Abhoy Kole, Saeideh Shirinzadeh, Rolf Drechsler:
Verification of In-Memory Logic Design using ReRAM Crossbars. NEWCAS 2023: 1-5 - [c678]Chandan Kumar Jha, Rolf Drechsler:
Benchmarking Multiplier Architectures for MAGIC Based In-Memory Computing. NEWCAS 2023: 1-5 - [c677]Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant:
Finite State Automata Design using 1T1R ReRAM Crossbar. NEWCAS 2023: 1-5 - [c676]Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler:
Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture. RC 2023: 218-231 - [c675]Abhoy Kole, Kamalika Datta, Philipp Niemann, Indranil Sengupta, Rolf Drechsler:
Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures. RC 2023: 232-244 - [c674]Mohamed A. Nadeem, Jan Kleinekathöfer, Rolf Drechsler:
Polynomial Formal Verification exploiting Constant Cutwidth. RSP 2023: 03:1-03:7 - [d3]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the IEEE Internet of Things Journal Publication: Specification-based Symbolic Execution for Stateful Network Protocol Implementations in the IoT. Zenodo, 2023
- [i25]Simranjeet Singh, Omar Ghazal, Chandan Kumar Jha, Vikas Rana, Rolf Drechsler, Rishad A. Shafik, Alex Yakovlev, Sachin B. Patkar, Farhad Merchant:
Finite State Automata Design using 1T1R ReRAM Crossbar. CoRR abs/2304.13552 (2023) - [i24]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Phrangboklang Lyngton Thangkhiew, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
Should We Even Optimize for Execution Energy? Rethinking Mapping for MAGIC Design Style. CoRR abs/2307.03669 (2023) - [i23]Simranjeet Singh, Chandan Kumar Jha, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant:
MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory. CoRR abs/2309.04868 (2023) - [i22]Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana:
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. CoRR abs/2310.10460 (2023) - [i21]Sallar Ahmadi-Pour, Pascal Pieper, Rolf Drechsler:
Virtual-Peripheral-in-the-Loop : A Hardware-in-the-Loop Strategy to Bridge the VP/RTL Design-Gap. CoRR abs/2311.00442 (2023) - 2022
- [j146]Vladimir Herdt, Rolf Drechsler:
Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges. Sci. China Inf. Sci. 65(1) (2022) - [j145]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Towards Quantification and Visualization of the Effects of Concretization During Concolic Testing. IEEE Embed. Syst. Lett. 14(4): 195-198 (2022) - [j144]Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta:
FAMCroNA: Fault Analysis in Memristive Crossbars for Neuromorphic Applications. J. Electron. Test. 38(2): 145-163 (2022) - [j143]Saman Fröhlich, Rolf Drechsler:
Unlocking approximation for in-memory computing with Cartesian genetic programming and computer algebra for arithmetic circuits. it Inf. Technol. 64(3): 99-107 (2022) - [j142]Robert Wille, Rolf Drechsler:
Introduction to the Special Issue on Design Automation for Quantum Computing. ACM J. Emerg. Technol. Comput. Syst. 18(1): 10:1-10:2 (2022) - [j141]Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler:
Parallel Computing of Graph-based Functions in ReRAM. ACM J. Emerg. Technol. Comput. Syst. 18(2): 41:1-41:24 (2022) - [j140]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
SymEx-VP: An open source virtual prototype for OS-agnostic concolic testing of IoT firmware. J. Syst. Archit. 126: 102456 (2022) - [j139]F. Lalchhandama, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta:
CoMIC: Complementary Memristor based in-memory computing in 3D architecture. J. Syst. Archit. 126: 102480 (2022) - [j138]Dev Narayan Yadav, Phrangboklang Lyngton Thangkhiew, Kamalika Datta, Sandip Chakraborty, Rolf Drechsler, Indranil Sengupta:
Feed-Forward learning algorithm for resistive memories. J. Syst. Archit. 131: 102730 (2022) - [j137]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
The MicroRV32 framework: An accessible and configurable open source RISC-V cross-level platform for education and research. J. Syst. Archit. 133: 102757 (2022) - [j136]Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler:
Template-based mapping of reversible circuits to IBM quantum computers. Microprocess. Microsystems 90: 104487 (2022) - [j135]Mehran Goli, Rolf Drechsler:
Through the Looking Glass: Automated Design Understanding of SystemC-Based VPs at the ESL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(4): 1181-1185 (2022) - [j134]Alireza Mahzoon, Daniel Große, Rolf Drechsler:
RevSCA-2.0: SCA-Based Formal Verification of Nontrivial Multipliers Using Reverse Engineering and Local Vanishing Removal. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1573-1586 (2022) - [c673]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Automated Detection of Spatial Memory Safety Violations for Constrained Devices. ASP-DAC 2022: 160-165 - [c672]Sajjad Parvin, Thilo Krachenfels, Shahin Tajik, Jean-Pierre Seifert, Frank Sill Torres, Rolf Drechsler:
Toward Optical Probing Resistant Circuits: A Comparison of Logic Styles and Circuit Design Techniques. ASP-DAC 2022: 429-435 - [c671]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. ATVA 2022: 77-82 - [c670]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Using density of training data to improve evolutionary algorithms with approximative fitness functions. CEC 2022: 1-10 - [c669]Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. DAC 2022: 1177-1182 - [c668]Alireza Mahzoon, Daniel Große, Christoph Scholl, Alexander Konrad, Rolf Drechsler:
Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiability. DAC 2022: 1183-1188 - [c667]Wolfgang Ecker, Peer Adelt, Wolfgang Müller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grüttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jörg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz:
The Scale4Edge RISC-V Ecosystem. DATE 2022: 808-813 - [c666]Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler:
Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging. DATE 2022: 1123-1126 - [c665]Saman Fröhlich, Rolf Drechsler:
LiM-HDL: HDL-Based Synthesis for In-Memory Computing. DATE 2022: 1395-1400 - [c664]Rolf Drechsler, Alireza Mahzoon, Mehran Goli:
Towards Polynomial Formal Verification of Complex Arithmetic Circuits. DDECS 2022: 1-6 - [c663]Milan Funck, Vladimir Herdt, Rolf Drechsler:
Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. DDECS 2022: 14-19 - [c662]Weiyan Zhang, Mehran Goli, Rolf Drechsler:
Early Performance Estimation of Embedded Software on RISC-V Processor using Linear Regression. DDECS 2022: 20-25 - [c661]Kemal Çaglar Coskun, Muhammad Hassan, Rolf Drechsler:
Equivalence Checking of System-Level and SPICE-Level Models of Linear Analog Filters. DDECS 2022: 160-165 - [c660]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
ML-based Power Estimation of Convolutional Neural Networks on GPGPUs. DDECS 2022: 166-171 - [c659]Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier:
Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. DSD 2022: 134-141 - [c658]Martha Schnieber, Saman Fröhlich, Rolf Drechsler:
Polynomial Formal Verification of Approximate Adders. DSD 2022: 761-768 - [c657]Abhoy Kole, Kamalika Datta, Indranil Sengupta, Rolf Drechsler:
SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library. DSD 2022: 769-776 - [c656]Kamalika Datta, Saeideh Shirinzadeh, Phrangboklang Lyngton Thangkhiew, Indranil Sengupta, Rolf Drechsler:
Unlocking Sneak Path Analysis in Memristor Based Logic Design Styles. DSD 2022: 793-800 - [c655]Saman Fröhlich, Rolf Drechsler:
Generation of Verified Programs for In-Memory Computing. DSD 2022: 815-820 - [c654]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
Quality Assessment of RFET-based Logic Locking Protection Mechanisms using Formal Methods. ETS 2022: 1-2 - [c653]Niklas Bruns, Vladimir Herdt, Rolf Drechsler:
Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification. FDL 2022: 1-8 - [c652]Alexander Fratzer, Vladimir Herdt, Christoph Lüth, Rolf Drechsler:
Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device. FDL 2022: 1-6 - [c651]Jan Zielasko, Sören Tempel, Vladimir Herdt, Rolf Drechsler:
3D Visualization of Symbolic Execution Traces. FDL 2022: 1-8 - [c650]Alexander Konrad, Christoph Scholl, Alireza Mahzoon, Daniel Große, Rolf Drechsler:
Divider Verification Using Symbolic Computer Algebra and Delayed Don't Care Optimization. FMCAD 2022: 1-10 - [c649]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Adapting mutation and recombination operators to range-aware relations in real-world application data. GECCO Companion 2022: 755-758 - [c648]Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler:
Mapping Quantum Circuits to 2-Dimensional Quantum Architectures. GI-Jahrestagung 2022: 1109-1120 - [c647]Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing. ACM Great Lakes Symposium on VLSI 2022: 97-103 - [c646]Pascal Pieper, Vladimir Herdt, Rolf Drechsler:
Advanced Environment Modeling and Interaction in an Open Source RISC-V Virtual Prototype. ACM Great Lakes Symposium on VLSI 2022: 193-197 - [c645]Rolf Drechsler, Alireza Mahzoon:
Polynomial Formal Verification: Ensuring Correctness under Resource Constraints. ICCAD 2022: 70:1-70:9 - [c644]Philipp Niemann, Rolf Drechsler:
Polynomial-Time Formal Verification of Adder Circuits for Multiple-Valued Logic. ISMVL 2022: 9-14 - [c643]Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler:
Nearest Neighbor Mapping of Quantum Circuits to Two-Dimensional Hexagonal Qubit Architecture. ISMVL 2022: 35-42 - [c642]Martha Schnieber, Saman Fröhlich, Rolf Drechsler:
Polynomial Formal Verification of Approximate Functions. ISVLSI 2022: 92-97 - [c641]Sebastian Huhn, Rolf Drechsler:
Next Generation Design For Testability, Debug and Reliability Using Formal Techniques. ITC 2022: 609-618 - [c640]Rolf Drechsler:
Fast and Exact is Doable: Polynomial Algorithms in Test and Verification. LATS 2022: 1-2 - [c639]Mehran Goli, Rolf Drechsler:
Simulation-based Verification of SystemC-based VPs at the ESL. MBMV 2022: 1-4 - [c638]Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Complex Multipliers. MBMV 2022: 1-4 - [c637]Tim Meywerk, Arthur Niedzwiecki, Vladimir Herdt, Rolf Drechsler:
Simulation-Based Debugging of Formal Environment Models. MED 2022: 890-895 - [c636]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Towards Neural Hardware Search: Power Estimation of CNNs for GPGPUs with Dynamic Frequency Scaling. MLCAD 2022: 103-109 - [c635]Görschwin Fey, Martin Fränzle, Rolf Drechsler:
Self-Explanation in Systems of Systems. RE Workshops 2022: 85-91 - [c634]Weiyan Zhang, Mehran Goli, Alireza Mahzoon, Rolf Drechsler:
ANN-based Performance Estimation of Embedded Software for RISC-V Processors. RSP 2022: 22-28 - [c633]Kamalika Datta, Saman Fröhlich, Saeideh Shirinzadeh, Dev Narayan Yadav, Indranil Sengupta, Rolf Drechsler:
Unlocking High Resolution Arithmetic Operations within Memristive Crossbars for Error Tolerant Applications. VLSI-SoC 2022: 1-6 - [c632]Rolf Drechsler, Alireza Mahzoon:
Preserving Design Hierarchy Information for Polynomial Formal Verification. VLSI-SoC 2022: 1-7 - [c631]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
A Hardware-based Evolutionary Algorithm with Multi-Objective Optimization Operators for On-Chip Transient Fault Detection. VTS 2022: 1-7 - [p5]Serge Autexier, Christoph Lüth, Rolf Drechsler:
Das Bremen Ambient Assisted Living Lab und darüber hinaus - Intelligente Umgebungen, smarte Services und Künstliche Intelligenz in der Medizin für den Menschen. Künstliche Intelligenz im Gesundheitswesen 2022: 835-850 - [d2]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the 2022 ATVA Paper: SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. Zenodo, 2022 - [i20]Mehran Goli, Rolf Drechsler:
Simulation-based Verification of SystemC-based VPs at the ESL. CoRR abs/2202.08046 (2022) - [i19]Jan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler:
Lower Bound Proof for the Size of BDDs representing a Shifted Addition. CoRR abs/2209.12477 (2022) - 2021
- [j133]Niklas Bruns, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Toward RISC-V CSR Compliance Testing. IEEE Embed. Syst. Lett. 13(4): 202-205 (2021) - [j132]Anirban Bhattacharjee, Chandan Bandyopadhyay, Philipp Niemann, Bappaditya Mondal, Rolf Drechsler, Hafizur Rahaman:
An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture. Integr. 76: 40-54 (2021) - [j131]Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
An ant colony based mapping of quantum circuits to nearest neighbor architectures. Integr. 78: 11-24 (2021) - [j130]Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler:
Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. 116: 102135 (2021) - [c630]Vladimir Herdt, Sören Tempel, Daniel Große, Rolf Drechsler:
Mutation-based Compliance Testing for RISC-V. ASP-DAC 2021: 55-60 - [c629]Mehran Goli, Rolf Drechsler:
ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs. ASP-DAC 2021: 67-72 - [c628]Marcel Walter, Winston Haaswijk, Robert Wille, Frank Sill Torres, Rolf Drechsler:
One-pass Synthesis for Field-coupled Nanocomputing Technologies. ASP-DAC 2021: 574-580 - [c627]Muhammad Hassan, Daniel Große, Rolf Drechsler:
System-Level Verification of Linear and Non-Linear Behaviors of RF Amplifiers using Metamorphic Relations. ASP-DAC 2021: 761-766 - [c626]Alireza Mahzoon, Rolf Drechsler:
Polynomial Formal Verification of Prefix Adders. ATS 2021: 85-90 - [c625]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Improving Evolutionary Algorithms by Enhancing an Approximative Fitness Function through Prediction Intervals. CEC 2021: 127-135 - [c624]Christina Plump, Bernhard J. Berger, Rolf Drechsler:
Domain-driven Correlation-aware Recombination and Mutation Operators for Complex Real-world Applications. CEC 2021: 540-548 - [c623]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Early power estimation of CUDA-based CNNs on GPGPUs: work-in-progress. CODES+ISSS 2021: 29-30 - [c622]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. DAC 2021: 667-672 - [c621]Alireza Mahzoon, Rolf Drechsler:
Late Breaking Results: Polynomial Formal Verification of Fast Adders. DAC 2021: 1376-1377 - [c620]Philipp Niemann, Chandan Bandyopadhyay, Rolf Drechsler:
Combining SWAPs and Remote Toffoli Gates in the Mapping to IBM QX Architectures. DATE 2021: 200-205 - [c619]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. DATE 2021: 218-221 - [c618]Christoph Scholl, Alexander Konrad, Alireza Mahzoon, Daniel Große, Rolf Drechsler:
Verifying Dividers Using Symbolic Computer Algebra and Don't Care Optimization. DATE 2021: 1110-1115 - [c617]Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer:
Nano Security: From Nano-Electronics to Secure Systems. DATE 2021: 1334-1339 - [c616]Muhammad Hassan, Daniel Große, Rolf Drechsler:
System Level Verification of Phase-Locked Loop using Metamorphic Relations. DATE 2021: 1378-1381 - [c615]Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar:
Vertical IP Protection of the Next-Generation Devices: Quo Vadis? DATE 2021: 1905-1914 - [c614]Rolf Drechsler:
PolyAdd: Polynomial Formal Verification of Adder Circuits. DDECS 2021: 99-104 - [c613]Marcel Merten, Sebastian Huhn, Rolf Drechsler:
A Codeword-based Compactor for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Networks. DFT 2021: 1-6 - [c612]Philipp Niemann, Luca Müller, Rolf Drechsler:
Combining SWAPs and Remote CNOT Gates for Quantum Circuit Transformation. DSD 2021: 495-501 - [c611]Mehran Goli, Alireza Mahzoon, Rolf Drechsler:
Automated Debugging-Aware Visualization Technique for SystemC HLS Designs. DSD 2021: 519-526 - [c610]Payam Habiby, Sebastian Huhn, Rolf Drechsler:
Optimization-based Test Scheduling for IEEE 1687 Multi-Power Domain Networks Using Boolean Satisfiability. DTIS 2021: 1-4 - [c609]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. FDL 2021: 1-7 - [c608]Mehran Goli, Rolf Drechsler:
VIP-VP: Early Validation of SoCs Information Flow Policies using SystemC-based Virtual Prototypes. FDL 2021: 1-8 - [c607]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. FDL 2021: 1-7 - [c606]Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler:
ALF: a fitness-based artificial life form for evolving large-scale neural networks. GECCO Companion 2021: 225-226 - [c605]Pascal Pieper, Ralf Wimmer, Gerhard Angst, Rolf Drechsler:
Minimally Invasive HW/SW Co-debug Live Visualization on Architecture Level. ACM Great Lakes Symposium on VLSI 2021: 321-326 - [c604]Mehran Goli, Rolf Drechsler:
Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs. ICCAD 2021: 1-8 - [c603]Lucas Klemmer, Saman Fröhlich, Rolf Drechsler, Daniel Große:
XbNN: Enabling CNNs on Edge Devices by Approximate On-Chip Dot Product Encoding. ISCAS 2021: 1-5 - [c602]Philipp Niemann, Rolf Drechsler:
Synthesis of Asymptotically Optimal Adders for Multiple-Valued Logic. ISMVL 2021: 178-182 - [c601]Martha Schnieber, Saman Fröhlich, Rolf Drechsler:
Depth Optimized Synthesis of Symmetric Boolean Functions. ISVLSI 2021: 61-66 - [c600]Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler:
Constrained Random Verification for RISC-V: Overview, Evaluation and Discussion. MBMV 2021: 1-8 - [c599]Mohammed Barhoush, Alireza Mahzoon, Rolf Drechsler:
Polynomial word-level verification of arithmetic circuits. MEMOCODE 2021: 1-9 - [c598]Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler:
Performance Aspects of Correctness-oriented Synthesis Flows. MODELSWARD 2021: 76-86 - [c597]Philipp Niemann, Luca Müller, Rolf Drechsler:
Finding Optimal Implementations of Non-native CNOT Gates Using SAT. RC 2021: 242-255 - [c596]Frank Riese, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Metamorphic Testing for Processor Verification: A RISC-V Case Study at the Instruction Level. VLSI-SoC 2021: 1-6 - [p4]Rolf Drechsler, Tommi A. Junttila, Ilkka Niemelä:
Non-Clausal SAT and ATPG. Handbook of Satisfiability 2021: 1047-1086 - [d1]Sören Tempel, Vladimir Herdt, Rolf Drechsler:
Artifacts for the FDL21 Paper: In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. Zenodo, 2021 - [i18]Christopher A. Metz, Mehran Goli, Rolf Drechsler:
Pick the Right Edge Device: Towards Power and Performance Estimation of CUDA-based CNNs on GPGPUs. CoRR abs/2102.02645 (2021) - [i17]Rolf Drechsler:
Polynomial Circuit Verification using BDDs. CoRR abs/2104.03024 (2021) - [i16]Rune Krauss, Marcel Merten, Mirco Bockholt, Rolf Drechsler:
ALF - A Fitness-Based Artificial Life Form for Evolving Large-Scale Neural Networks. CoRR abs/2104.08252 (2021) - 2020
- [j129]Frank Sill Torres, Philipp Niemann, Robert Wille, Rolf Drechsler:
Near Zero-Energy Computation Using Quantum-Dot Cellular Automata. ACM J. Emerg. Technol. Comput. Syst. 16(1): 11:1-11:16 (2020) - [j128]Vladimir Herdt, Daniel Große, Pascal Pieper, Rolf Drechsler:
RISC-V based virtual prototype: An extensible and configurable platform for the system-level. J. Syst. Archit. 109: 101756 (2020) - [j127]Frank Sill Torres, Pedro Arthur Silva, Geraldo Fontes, Marcel Walter, José Augusto Miranda Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Robert Wille, Philipp Niemann, Daniel Große, Rolf Drechsler:
On the impact of the synchronization constraint and interconnections in quantum-dot cellular automata. Microprocess. Microsystems 76: 103109 (2020) - [j126]Philipp Niemann, Robert Wille, Rolf Drechsler:
Advanced exact synthesis of Clifford+T circuits. Quantum Inf. Process. 19(1) (2020) - [j125]Mehran Goli, Jannis Stoppe, Rolf Drechsler:
Automated Nonintrusive Analysis of Electronic System Level Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(2): 492-505 (2020) - [j124]Philipp Niemann, Alwin Zulehner, Rolf Drechsler, Robert Wille:
Overcoming the Tradeoff Between Accuracy and Compactness in Decision Diagrams for Quantum Computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4657-4668 (2020) - [j123]Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Kaijie Wu, Rolf Drechsler, Ramesh Karri:
On the Difficulty of Inserting Trojans in Reversible Computing Architectures. IEEE Trans. Emerg. Top. Comput. 8(4): 960-972 (2020) - [j122]Mehran Goli, Rolf Drechsler:
PREASC: Automatic Portion Resilience Evaluation for Approximating SystemC-based Designs Using Regression Analysis Techniques. ACM Trans. Design Autom. Electr. Syst. 25(5): 40:1-40:28 (2020) - [c595]Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler:
Towards Automatic Hardware Synthesis from Formal Specification to Implementation. ASP-DAC 2020: 375-380 - [c594]Vladimir Herdt, Daniel Große, Rolf Drechsler:
RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. ATVA 2020: 543-549 - [c593]Vladimir Herdt, Daniel Große, Rolf Drechsler:
Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side*. DAC 2020: 1-6 - [c592]Pascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. DAC 2020: 1-6 - [c591]Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler:
Verification for Field-coupled Nanocomputing Circuits. DAC 2020: 1-6 - [c590]Alireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler:
Towards Formal Verification of Optimized and Industrial Multipliers. DATE 2020: 544-549 - [c589]Vladimir Herdt, Daniel Große, Rolf Drechsler:
Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes*. DATE 2020: 618-621 - [c588]Martin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler:
Verification Runtime Analysis: Get the Most Out of Partial Verification. DATE 2020: 873-878 - [c587]Vladimir Herdt, Daniel Große, Rolf Drechsler:
Towards Specification and Testing of RISC-V ISA Compliance⋆. DATE 2020: 995-998 - [c586]David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler:
Towards Generation of a Programmable Power Management Unit at the Electronic System Level. DDECS 2020: 1-6 - [c585]Payam Habiby, Sebastian Huhn, Rolf Drechsler:
Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains. DFT 2020: 1-6 - [c584]Philipp Niemann, Alexandre A. A. de Almeida, Gerhard W. Dueck, Rolf Drechsler:
Design Space Exploration in the Mapping of Reversible Circuits to IBM Quantum Computers. DSD 2020: 401-407 - [c583]Umberto Garlando, Marcel Walter, Robert Wille, Fabrizio Riente, Frank Sill Torres, Rolf Drechsler:
ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing. DSD 2020: 408-415 - [c582]Rolf Drechsler, Sebastian Huhn, Christina Plump:
Combining Machine Learning and Formal Techniques for Small Data Applications - A Framework to Explore New Structural Materials. DSD 2020: 518-525 - [c581]Vladimir Herdt, Daniel Große, Eyck Jentzsch, Rolf Drechsler:
Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. FDL 2020: 1-7 - [c580]Rune Krauss, Marcel Merten, Mirco Bockholt, Saman Fröhlich, Rolf Drechsler:
Efficient machine learning through evolving combined deep neural networks. GECCO Companion 2020: 215-216 - [c579]Vladimir Herdt, Daniel Große, Jonas Wloka, Tim Güneysu, Rolf Drechsler:
Verification of Embedded Binaries using Coverage-guided Fuzzing with SystemC-based Virtual Prototypes. ACM Great Lakes Symposium on VLSI 2020: 101-106 - [c578]Niklas Bruns, Daniel Große, Rolf Drechsler:
Early Verification of ISA Extension Specifications using Deep Reinforcement Learning. ACM Great Lakes Symposium on VLSI 2020: 297-302 - [c577]Mehran Goli, Alireza Mahzoon, Rolf Drechsler:
ASCHyRO: Automatic Fault Localization of SystemC HLS Designs Using a Hybrid Accurate Rank Ordering Technique. ICCD 2020: 179-186 - [c576]Vladimir Herdt, Daniel Große, Sören Tempel, Rolf Drechsler:
Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. ICCD 2020: 312-315 - [c575]Tim Meywerk, Marcel Walter, Daniel Große, Rolf Drechsler:
Clustering-Guided SMT($\mathcal {L\!R\!A}$) Learning. IFM 2020: 41-59 - [c574]Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler:
Multiply-Accumulate Enhanced BDD-Based Logic Synthesis on RRAM Crossbars. ISCAS 2020: 1-5 - [c573]Oliver Keszöcze, Robert Wille, Rolf Drechsler:
One-pass Synthesis for Digital Microfluidic Biochips: A Survey. ISDCS 2020: 1-6 - [c572]Anirban Bhattacharjee, Chandan Bandyopadhyay, Angshu Mukherjee, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm. ISMVL 2020: 40-45 - [c571]Saman Fröhlich, Lucas Klemmer, Daniel Große, Rolf Drechsler:
ASNet: Introducing Approximate Hardware to High-Level Synthesis of Neural Networks. ISMVL 2020: 64-69 - [c570]Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathöfer, Daniel Große, Rolf Drechsler:
Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. ISoLA (3) 2020: 326-347 - [c569]Marcel Walter, Robert Wille, Frank Sill Torres, Rolf Drechsler:
Bail on Balancing: An Alternative Approach to the Physical Design of Field-Coupled Nanocomputing Circuits. ISVLSI 2020: 66-71 - [c568]Marcel Walter, Rolf Drechsler:
Design Automation for Field-Coupled Nanotechnologies. ISVLSI 2020: 176-181 - [c567]Vladimir Herdt, Rolf Drechsler:
Efficient Techniques to Strongly Enhance the Virtual Prototype Based Design Flow. ISVLSI 2020: 182-187 - [c566]Mehran Goli, Rolf Drechsler:
Automated Design Understanding of SystemC-Based Virtual Prototypes: Data Extraction, Analysis and Visualization. ISVLSI 2020: 188-193 - [c565]Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler:
Safety First: About the Detection of Arithmetic Overflows in Hardware Design Specifications. MODELSWARD (Revised Selected Papers) 2020: 26-48 - [c564]Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler:
Integer Overflow Detection in Hardware Designs at the Specification Level. MODELSWARD 2020: 41-48 - [c563]Mazyar Seraj, Eva-Sophie Katterfeldt, Serge Autexier, Rolf Drechsler:
Impacts of Creating Smart Everyday Objects on Young Female Students' Programming Skills and Attitudes. SIGCSE 2020: 1234-1240 - [c562]Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Post Synthesis-Optimization of Reversible Circuit using Template Matching. VDAT 2020: 1-4 - [i15]Rolf Drechsler:
PolyAdd: Polynomial Formal Verification of Adder Circuits. CoRR abs/2009.03242 (2020)
2010 – 2019
- 2019
- [j121]Florian Bache, Christina Plump, Jonas Wloka, Tim Güneysu, Rolf Drechsler:
Evaluation of (power) side-channels in cryptographic implementations. it Inf. Technol. 61(1): 15-28 (2019) - [j120]Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler:
Security validation of VP-based SoCs using dynamic information flow tracking. it Inf. Technol. 61(1): 45-58 (2019) - [j119]Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler:
Placement and Routing for Tile-based Field-coupled Nanocomputing Circuits Is NP-complete (Research Note). ACM J. Emerg. Technol. Comput. Syst. 15(3): 29:1-29:10 (2019) - [j118]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Combining sequentialization-based verification of multi-threaded C programs with symbolic Partial Order Reduction. Int. J. Softw. Tools Technol. Transf. 21(5): 545-565 (2019) - [j117]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Verifying SystemC Using Intermediate Verification Language and Stateful Symbolic Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(7): 1359-1372 (2019) - [j116]Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark M. Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber:
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 253-280 (2019) - [j115]Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler:
Determining Application-Specific Knowledge for Improving Robustness of Sequential Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(4): 875-887 (2019) - [j114]Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Ramesh Karri:
Reversible Circuits: IC/IP Piracy Attacks and Countermeasures. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2523-2535 (2019) - [c561]Mazyar Seraj, Cornelia S. Große, Serge Autexier, Rolf Drechsler:
Smart Homes Programming: Development and Evaluation of an Educational Programming Application for Young Learners. IDC 2019: 146-152 - [c560]Kenneth Schmitz, Buse Ustaoglu, Daniel Große, Rolf Drechsler:
(ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-Based Countermeasures on FPGAs. ARC 2019: 112-126 - [c559]Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler:
Scalable design for field-coupled nanocomputing circuits. ASP-DAC 2019: 197-202 - [c558]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Maximizing power state cross coverage in firmware-based power management. ASP-DAC 2019: 335-340 - [c557]Rolf Drechsler, Daniel Große:
Ensuring Correctness of Next Generation Devices: From Reconfigurable to Self-Learning Systems. ATS 2019: 159-164 - [c556]Alireza Mahzoon, Daniel Große, Rolf Drechsler:
RevSCA: Using Reverse Engineering to Bring Light into Backward Rewriting for Big and Dirty Multipliers. DAC 2019: 185 - [c555]Rehab Massoud, Hoang M. Le, Peter Chini, Prakash Saivasan, Roland Meyer, Rolf Drechsler:
Temporal Tracing of On-Chip Signals using Timeprints. DAC 2019: 186 - [c554]Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler:
Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. DAC 2019: 188 - [c553]Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille:
Accuracy and Compactness in Decision Diagrams for Quantum Computation. DATE 2019: 280-283 - [c552]Saman Fröhlich, Daniel Große, Rolf Drechsler:
One Method - All Error-Metrics: A Three-Stage Approach for Error-Metric Evaluation in Approximate Computing. DATE 2019: 284-287 - [c551]Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler:
Verifying Instruction Set Simulators using Coverage-guided Fuzzing*. DATE 2019: 360-365 - [c550]Muhammad Hassan, Daniel Große, Hoang M. Le, Rolf Drechsler:
Data Flow Testing for SystemC-AMS Timed Data Flow Models. DATE 2019: 366-371 - [c549]Hoang M. Le, Daniel Große, Niklas Bruns, Rolf Drechsler:
Detection of Hardware Trojans in SystemC HLS Designs via Coverage-guided Fuzzing. DATE 2019: 602-605 - [c548]Martin Ring, Fritjof Bornebusch, Christoph Lüth, Robert Wille, Rolf Drechsler:
Better Late Than Never : Verification of Embedded Systems After Deployment. DATE 2019: 890-895 - [c547]Rolf Drechsler, Christoph Lüth:
Code is Ethics - Formal Techniques for a Better World. DSD 2019: 1-3 - [c546]Buse Ustaoglu, Sebastian Huhn, Frank Sill Torres, Daniel Große, Rolf Drechsler:
SAT-Hard: A Learning-Based Hardware SAT-Solver. DSD 2019: 74-81 - [c545]Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. DSD 2019: 129-136 - [c544]Mehran Goli, Rolf Drechsler:
Scalable Simulation-Based Verification of SystemC-Based Virtual Prototypes. DSD 2019: 522-529 - [c543]Sebastian Huhn, Daniel Tille, Rolf Drechsler:
Hybrid Architecture for Embedded Test Compression to Process Rejected Test Patterns. ETS 2019: 1-2 - [c542]Harshad Dhotre, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler:
Machine Learning-based Prediction of Test Power. ETS 2019: 1-6 - [c541]Muhammad Hassan, Daniel Große, Thilo Vörtler, Karsten Einwich, Rolf Drechsler:
Functional Coverage-Driven Characterization of RF Amplifiers. FDL 2019: 1-8 - [c540]Vladimir Herdt, Daniel Große, Rolf Drechsler, Christoph Gerum, Alexander Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz:
Systematic RISC-V based Firmware Design⋆. FDL 2019: 1-8 - [c539]Rehab Massoud, Hoang M. Le, Rolf Drechsler:
Property-Driven Timestamps Encoding for Timeprints-Based Tracing and Monitoring. FORMATS 2019: 41-58 - [c538]Mehran Goli, Muhammad Hassan, Daniel Große, Rolf Drechsler:
Automated Analysis of Virtual Prototypes at Electronic System Level. ACM Great Lakes Symposium on VLSI 2019: 307-310 - [c537]Mazyar Seraj, Cornelia S. Große, Serge Autexier, Rolf Drechsler:
Look what I can do: acquisition of programming skills in the context of living labs. ICSE (SEET) 2019: 197-207 - [c536]Frank Sill Torres, Hussam Amrouch, Jörg Henkel, Rolf Drechsler:
Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation. IRPS 2019: 1-6 - [c535]Frank Sill Torres, Alberto García Ortiz, Rolf Drechsler:
HotAging - Impact of Power Dissipation on Hardware Degradation. ISCAS 2019: 1-5 - [c534]Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille:
One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits. ISMVL 2019: 1-6 - [c533]Philipp Niemann, Anshu Gupta, Rolf Drechsler:
T-depth Optimization for Fault-Tolerant Quantum Circuits. ISMVL 2019: 108-113 - [c532]Saman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler:
Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits. ISVLSI 2019: 431-436 - [c531]Robert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler:
Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies. ISVLSI 2019: 651-656 - [c530]Sebastian Huhn, Daniel Tille, Rolf Drechsler:
A Hybrid Embedded Multichannel Test Compression Architecture for Low-Pin Count Test Environments in Safety-Critical Systems. ITC-Asia 2019: 115-120 - [c529]Mazyar Seraj, Eva-Sophie Katterfeldt, Kerstin Bub, Serge Autexier, Rolf Drechsler:
Scratch and Google Blockly: How Girls' Programming Skills and Attitudes are Influenced. Koli Calling 2019: 23:1-23:10 - [c528]Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler:
Cluster-based Localization of IR-drop in Test Application considering Parasitic Elements. LATS 2019: 1-4 - [c527]Görschwin Fey, Rolf Drechsler:
Self-Explaining Digital Systems - Some Technical Steps. MBMV 2019: 1-8 - [c526]Steffen Frerix, Saeideh Shirinzadeh, Saman Fröhlich, Rolf Drechsler:
ComPRIMe: A Compiler for Parallel and Scalable ReRAM-based In-Memory Computing. NANOARCH 2019: 1-6 - [c525]Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits. VLSID 2019: 203-208 - [p3]Saman Fröhlich, Daniel Große, Rolf Drechsler:
Approximate Hardware Generation Using Formal Techniques. Approximate Circuits 2019: 155-174 - [i14]Marcel Walter, Robert Wille, Frank Sill Torres, Daniel Große, Rolf Drechsler:
fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits. CoRR abs/1905.02477 (2019) - [i13]Alwin Zulehner, Philipp Niemann, Rolf Drechsler, Robert Wille:
One Additional Qubit is Enough: Encoded Embeddings for Boolean Components in Quantum Circuits. CoRR abs/1906.02352 (2019) - 2018
- [b14]Nils Przigoda, Robert Wille, Judith Przigoda, Rolf Drechsler:
Automated Validation & Verification of UML/OCL Models Using Satisfiability Solvers. Springer 2018, ISBN 978-3-319-72813-1 - [j113]Nils Przigoda, Philipp Niemann, Jonas Gomes Filho, Robert Wille, Rolf Drechsler:
Frame conditions in the automatic validation and verification of UML/OCL models: A symbolic formulation of modifies only statements. Comput. Lang. Syst. Struct. 54: 512-527 (2018) - [j112]Oliver Keszöcze, Mathias Soeken, Rolf Drechsler:
The complexity of error metrics. Inf. Process. Lett. 139: 1-7 (2018) - [j111]Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Daniel Große, Rolf Drechsler:
Behaviour Driven Development for Hardware Design. IPSJ Trans. Syst. LSI Des. Methodol. 11: 29-45 (2018) - [j110]Chandan Bandyopadhyay, Rakesh Das, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams. Microelectron. J. 71: 19-29 (2018) - [j109]Oliver Keszöcze, Philipp Niemann, Arved Friedemann, Rolf Drechsler:
On the complexity of design tasks for Digital Microfluidic Biochips. Microelectron. J. 78: 35-45 (2018) - [j108]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler:
Logic Synthesis for RRAM-Based In-Memory Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1422-1435 (2018) - [j107]Frank Sill Torres, Robert Wille, Philipp Niemann, Rolf Drechsler:
An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3031-3041 (2018) - [c524]Arun Chandrasekharan, Stephan Eggersglüß, Daniel Große, Rolf Drechsler:
Approximation-aware testing for approximate circuits. ASP-DAC 2018: 239-244 - [c523]Marcel Walter, Robert Wille, Daniel Große, Frank Sill Torres, Rolf Drechsler:
An exact method for design exploration of quantum-dot cellular automata. DATE 2018: 503-508 - [c522]Philipp Niemann, Robert Wille, Rolf Drechsler:
Improved synthesis of Clifford+T quantum functionality. DATE 2018: 597-600 - [c521]Hoang M. Le, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Resilience evaluation via symbolic fault injection on intermediate code. DATE 2018: 845-850 - [c520]Muhammad Hassan, Daniel Große, Hoang M. Le, Thilo Vörtler, Karsten Einwich, Rolf Drechsler:
Testbench qualification for SystemC-AMS timed data flow models. DATE 2018: 857-860 - [c519]Saman Fröhlich, Daniel Große, Rolf Drechsler:
Approximate hardware generation using symbolic computer algebra employing grobner basis. DATE 2018: 889-892 - [c518]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards fully automated TLM-to-RTL property refinement. DATE 2018: 1508-1511 - [c517]Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler, Mehdi Dehbashi, Ulrike Pfannkuchen:
Constraint-Based Pattern Retargeting for Reducing Localized Power Activity During Testing. DDECS 2018: 79-84 - [c516]David Lemma, Daniel Große, Rolf Drechsler:
Natural Language Based Power Domain Partitioning. DDECS 2018: 101-106 - [c515]Frank Sill Torres, Pedro Arthur Silva, Geraldo Fontes, José Augusto Miranda Nacif, Ricardo Santos Ferreira, Omar Paranaiba Vilela Neto, Jeferson F. Chaves, Rolf Drechsler:
Exploration of the Synchronization Constraint in Quantum-dot Cellular Automata. DSD 2018: 642-648 - [c514]Frank Sill Torres, Robert Wille, Marcel Walter, Philipp Niemann, Daniel Große, Rolf Drechsler:
Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata. DSD 2018: 649-656 - [c513]Saman Fröhlich, Daniel Große, Rolf Drechsler:
Towards Reversed Approximate Hardware Design. DSD 2018: 665-671 - [c512]Vladimir Herdt, Daniel Große, Hoang M. Le, Rolf Drechsler:
Extensible and Configurable RISC-V Based Virtual Prototype. FDL 2018: 5-16 - [c511]Robert Wille, Bing Li, Rolf Drechsler, Ulf Schlichtmann:
Automatic Design of Microfluidic Devices. FDL 2018: 5-16 - [c510]Buse Ustaoglu, Sebastian Huhn, Daniel Große, Rolf Drechsler:
SAT-Lancer: A Hardware SAT-Solver for Self-Verification. ACM Great Lakes Symposium on VLSI 2018: 479-482 - [c509]Samah Mohamed Saeed, Xiaotong Cui, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri:
IC/IP piracy assessment of reversible logic. ICCAD 2018: 5 - [c508]Alireza Mahzoon, Daniel Große, Rolf Drechsler:
PolyCleaner: clean your polynomials before backward rewriting to verify million-gate multipliers. ICCAD 2018: 129 - [c507]Robert Schmidt, Rehab Massoud, Jaan Raik, Alberto García Ortiz, Rolf Drechsler:
Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling. IOLTS 2018: 247-250 - [c506]Zaid Al-Wardi, Robert Wille, Rolf Drechsler:
Synthesis of Reversible Circuits Using Conventional Hardware Description Languages. ISMVL 2018: 97-102 - [c505]Saeideh Shirinzadeh, Kamalika Datta, Rolf Drechsler:
Logic Design Using Memristors: An Emerging Technology. ISMVL 2018: 121-126 - [c504]Anirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits. ISVLSI 2018: 305-310 - [c503]Alireza Mahzoon, Daniel Große, Rolf Drechsler:
Combining Symbolic Computer Algebra and Boolean Satisfiability for Automatic Debugging and Fixing of Complex Multipliers. ISVLSI 2018: 351-356 - [c502]Saeideh Shirinzadeh, Rolf Drechsler:
Logic Synthesis for In-memory Computing Using Resistive Memories. ISVLSI 2018: 375-380 - [c501]Kenneth Schmitz, Oliver Keszöcze, Jurij Schmidt, Daniel Große, Rolf Drechsler:
Towards Dynamic Execution Environment for System Security Protection Against Hardware Flaws. ISVLSI 2018: 557-562 - [c500]Rolf Drechsler, Christoph Lüth, Görschwin Fey, Tim Güneysu:
Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation. IVSW 2018: 1-6 - [c499]Rolf Drechsler:
Keynotes: Towards Self-Explaining Digital Systems: A Design Methodology for the Next Generation. IVSW 2018: i-iii - [c498]Jannis Stoppe, Christina Plump, Sebastian Huhn, Rolf Drechsler:
Building Fast Multi Agent Systems Using Hardware Design Languages for High-Throughput Systems. LDIC 2018: 400-405 - [c497]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards Automated Refinement of TLM Properties to RTL. MBMV 2018 - [c496]Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler:
Analyzing Frame Conditions in UML/OCL Models - Consistency Equivalence and Independence. MODELSWARD 2018: 139-151 - [c495]Philipp Niemann, Nils Przigoda, Robert Wille, Rolf Drechsler:
Generation and Validation of Frame Conditions in Formal Models. MODELSWARD (Revised Selected Papers) 2018: 259-283 - [c494]David Lemma, Mehran Goli, Daniel Große, Rolf Drechsler:
Power Intent from Initial ESL Prototypes: Extracting Power Management Parameters*. NORCAS 2018: 1-6 - [c493]Moein Sarvaghad-Moghaddam, Philipp Niemann, Rolf Drechsler:
Multi-objective Synthesis of Quantum Circuits Using Genetic Programming. RC 2018: 220-227 - [c492]Mehran Goli, Jannis Stoppe, Rolf Drechsler:
Resilience Evaluation for Approximating SystemC Designs Using Machine Learning Techniques. RSP 2018: 97-103 - [c491]Oliver Keszöcze, Mohamed Ibrahim, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler:
Exact Synthesis of Biomolecular Protocols for Multiple Sample Pathways on Digital Microfluidic Biochips. VLSID 2018: 121-126 - [p2]Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler, Priyank Kalla:
Emerging Circuit Technologies: An Overview on the Next Generation of Circuits. Advanced Logic Synthesis 2018: 43-67 - [e15]André Inácio Reis, Rolf Drechsler:
Advanced Logic Synthesis. Springer 2018, ISBN 978-3-319-67294-6 [contents] - [i12]Frank Sill Torres, Philipp Niemann, Robert Wille, Rolf Drechsler:
Breaking Landauer's Limit\\Using Quantum-dot Cellular Automata. CoRR abs/1811.03894 (2018) - 2017
- [j106]Mathias Soeken, Pierre-Emmanuel Gaillardon, Saeideh Shirinzadeh, Rolf Drechsler, Giovanni De Micheli:
A PLiM Computer for the Internet of Things. Computer 50(6): 35-40 (2017) - [j105]Arighna Deb, Robert Wille, Oliver Keszöcze, Saeideh Shirinzadeh, Rolf Drechsler:
Synthesis of optical circuits using binary decision diagrams. Integr. 59: 42-51 (2017) - [j104]Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler:
An Automated Approach for Generating and Checking Control Logic for Reversible Hardware Description Language-Based Designs. J. Low Power Electron. 13(4): 633-641 (2017) - [j103]Heinz Riener, Finn Haedicke, Stefan Frehse, Mathias Soeken, Daniel Große, Rolf Drechsler, Görschwin Fey:
metaSMT: focus on your application and not on solver integration. Int. J. Softw. Tools Technol. Transf. 19(5): 605-621 (2017) - [j102]Pablo González de Aledo, Nils Przigoda, Robert Wille, Rolf Drechsler, Pablo Sánchez Espeso:
Towards a Verification Flow Across Abstraction Levels Verifying Implementations Against Their Formal Specification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(3): 475-488 (2017) - [c490]Kenneth Schmitz, Arun Chandrasekharan, Jonas Gomes Filho, Daniel Große, Rolf Drechsler:
Trust is good, control is better: Hardware-based instruction-replacement for reliable processor-IPs. ASP-DAC 2017: 57-62 - [c489]Sebastian Huhn, Stefan Frehse, Robert Wille, Rolf Drechsler:
Enhancing robustness of sequential circuits using application-specific knowledge and formal methods. ASP-DAC 2017: 182-187 - [c488]Oliver Keszöcze, Zipeng Li, Andreas Grimmer, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler:
Exact routing for micro-electrode-dot-array digital microfluidic biochips. ASP-DAC 2017: 708-713 - [c487]Harshad Dhotre, Stephan Eggersglüß, Rolf Drechsler:
Identification of Efficient Clustering Techniques for Test Power Activity on the Layout. ATS 2017: 108-113 - [c486]Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Große, Rolf Drechsler:
Data flow testing for virtual prototypes. DATE 2017: 380-385 - [c485]Sebastian Huhn, Stephan Eggersglüß, Krishnendu Chakrabarty, Rolf Drechsler:
Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression. DATE 2017: 578-583 - [c484]Mehran Goli, Jannis Stoppe, Rolf Drechsler:
Automatic equivalence checking for SystemC-TLM 2.0 models against their formal specifications. DATE 2017: 630-633 - [c483]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler:
Endurance management for resistive Logic-In-Memory computing architectures. DATE 2017: 1092-1097 - [c482]Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler:
Effects of cell shapes on the routability of Digital Microfluidic Biochips. DATE 2017: 1627-1630 - [c481]Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler:
Machine learning based test pattern analysis for localizing critical power activity areas. DFT 2017: 1-6 - [c480]Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler:
Reconfigurable TAP controllers with embedded compression for large test data volume. DFT 2017: 1-6 - [c479]Frank Sill Torres, Pedro Fausto Rodrigues Leite, Rolf Drechsler:
Unintrusive aging analysis based on offline learning. DFT 2017: 1-4 - [c478]Maria K. Michael, Rolf Drechsler, Stephan Eggersglüß, Haralampos-G. D. Stratigopoulos, Sybille Hellebrand, Rob Aitken:
Foreword. ETS 2017: 1-2 - [c477]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. FDL 2017: 1-8 - [c476]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. FDL (Selected Papers) 2017: 25-44 - [c475]Rehab Massoud, Jannis Stoppe, Daniel Große, Rolf Drechsler:
Semi-formal Cycle-Accurate Temporal Execution Traces Reconstruction. FORMATS 2017: 335-351 - [c474]Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler:
An adaptive prioritized ε-preferred evolutionary algorithm for approximate BDD optimization. GECCO 2017: 1232-1239 - [c473]Arun Chandrasekharan, Daniel Große, Rolf Drechsler:
ProACt: A Processor for High Performance On-demand Approximate Computing. ACM Great Lakes Symposium on VLSI 2017: 463-466 - [c472]Arighna Deb, Robert Wille, Rolf Drechsler:
Dedicated synthesis for MZI-based optical circuits based on AND-inverter graphs. ICCAD 2017: 233-238 - [c471]Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Early SoC security validation by VP-based static information flow analysis. ICCAD 2017: 400-407 - [c470]Mehran Goli, Jannis Stoppe, Rolf Drechsler:
Automatic Protocol Compliance Checking of SystemC TLM-2.0 Simulation Behavior Using Timed Automata. ICCD 2017: 377-384 - [c469]Fritjof Bornebusch, Robert Wille, Rolf Drechsler:
Towards lightweight satisfiability solvers for self-verification. ISED 2017: 1-5 - [c468]Abhoy Kole, P. Mercy Nesa Rani, Kamalika Datta, Indranil Sengupta, Rolf Drechsler:
Exact Synthesis of Ternary Reversible Functions Using Ternary Toffoli Gates. ISMVL 2017: 179-184 - [c467]Zaid Al-Wardi, Robert Wille, Rolf Drechsler:
Extensions to the Reversible Hardware Description Language SyReC. ISMVL 2017: 185-190 - [c466]Saman Fröhlich, Daniel Große, Rolf Drechsler:
Error Bounded Exact BDD Minimization in Approximate Computing. ISMVL 2017: 254-259 - [c465]Arighna Deb, Robert Wille, Rolf Drechsler:
OR-Inverter Graphs for the Synthesis of Optical Circuits. ISMVL 2017: 278-283 - [c464]Jannis Stoppe, Oliver Keszöcze, Maximilian Luenert, Robert Wille, Rolf Drechsler:
BioViz: An Interactive Visualization Engine for the Design of Digital Microfluidic Biochips. ISVLSI 2017: 170-175 - [c463]Saman Fröhlich, Daniel Große, Rolf Drechsler:
Exakte BDD Minimierung mit Fehlerschranke für den Einsatz im Approximate Computing. MBMV 2017: 27-38 - [c462]Leonard Schneider, Oliver Keszöcze, Jannis Stoppe, Rolf Drechsler:
Einfluss von Zellformen auf das Routing von Digital Microfluidic Biochips. MBMV 2017: 75-78 - [c461]Nils Przigoda, Philipp Niemann, Judith Peters, Frank Hilken, Robert Wille, Rolf Drechsler:
More than true or false: native support of irregular values in the automatic validation & verification of UML/OCL models. MEMOCODE 2017: 77-86 - [c460]Arun Chandrasekharan, Daniel Große, Rolf Drechsler:
Yise - a novel framework for boolean networks using y-inverter graphs. MEMOCODE 2017: 114-117 - [c459]Zaid Al-Wardi, Robert Wille, Rolf Drechsler:
Towards VHDL-Based Design of Reversible Circuits - Work in Progress Report. RC 2017: 102-108 - [c458]Philipp Niemann, Alwin Zulehner, Robert Wille, Rolf Drechsler:
Efficient Construction of QMDDs for Irreversible, Reversible, and Quantum Functions. RC 2017: 214-231 - [c457]Sebastian Huhn, Heike Sonnenberg, Stephan Eggersglüß, Brigitte Clausen, Rolf Drechsler:
Revealing properties of structural materials by combining regression-based algorithms and nano indentation measurements. SSCI 2017: 1-6 - [e14]Daniel Große, Rolf Drechsler:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2017, Bremen, Germany, February 8-9, 2017. Shaker Verlag 2017, ISBN 978-3-8440-4996-1 [contents] - [i11]Samah Mohamed Saeed, Xiaotong Cui, Robert Wille, Alwin Zulehner, Kaijie Wu, Rolf Drechsler, Ramesh Karri:
Towards Reverse Engineering Reversible Logic. CoRR abs/1704.08397 (2017) - [i10]Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Kaijie Wu, Ramesh Karri:
On the Difficulty of Inserting Trojans in Reversible Computing Architectures. CoRR abs/1705.00767 (2017) - 2016
- [j101]Nils Przigoda, Mathias Soeken, Robert Wille, Rolf Drechsler:
Verifying the structure and behavior in UML/OCL models using satisfiability solvers. IET Cyper-Phys. Syst.: Theory & Appl. 1(1): 49-59 (2016) - [j100]Robert Wille, Eleonora Schönborn, Mathias Soeken, Rolf Drechsler:
SyReC: A hardware description language for the specification and synthesis of reversible circuits. Integr. 53: 39-53 (2016) - [j99]Nils Przigoda, Robert Wille, Rolf Drechsler:
Analyzing Inconsistencies in UML/OCL Models. J. Circuits Syst. Comput. 25(3): 1640021:1-1640021:21 (2016) - [j98]Arighna Deb, Debesh K. Das, Hafizur Rahaman, Robert Wille, Rolf Drechsler, Bhargab B. Bhattacharya:
Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. ACM J. Emerg. Technol. Comput. Syst. 12(4): 34:1-34:29 (2016) - [j97]Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler:
Embedding of Large Boolean Functions for Reversible Logic. ACM J. Emerg. Technol. Comput. Syst. 12(4): 41:1-41:26 (2016) - [j96]Arighna Deb, Robert Wille, Oliver Keszöcze, Stefan Hillmich, Rolf Drechsler:
Gates vs. Splitters: Contradictory Optimization Objectives in the Synthesis of Optical Circuits. ACM J. Emerg. Technol. Comput. Syst. 13(1): 11:1-11:13 (2016) - [j95]Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler:
Ancilla-free synthesis of large reversible functions using binary decision diagrams. J. Symb. Comput. 73: 1-26 (2016) - [j94]Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler:
QMDDs: Efficient Quantum Function Representation and Manipulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 86-99 (2016) - [j93]Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler:
On Optimization-Based ATPG and Its Application for Highly Compacted Test Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(12): 2104-2117 (2016) - [j92]Nabila Abdessaied, Matthew Amy, Rolf Drechsler, Mathias Soeken:
Complexity of reversible circuits and their quantum implementations. Theor. Comput. Sci. 618: 85-106 (2016) - [c456]Robert Wille, Oliver Keszöcze, Marcel Walter, Patrick Rohrs, Anupam Chattopadhyay, Rolf Drechsler:
Look-ahead schemes for nearest neighbor optimization of 1D and 2D quantum circuits. ASP-DAC 2016: 292-297 - [c455]Mathias Soeken, Daniel Große, Arun Chandrasekharan, Rolf Drechsler:
BDD minimization for approximate computing. ASP-DAC 2016: 474-479 - [c454]Vladimir Herdt, Hoang Minh Le, Daniel Große, Rolf Drechsler:
ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. CAV (2) 2016: 177-183 - [c453]Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli:
An MIG-based compiler for programmable logic-in-memory architectures. DAC 2016: 117:1-117:6 - [c452]Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler:
Precise error determination of approximated components in sequential circuits with model checking. DAC 2016: 129:1-129:6 - [c451]Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große, Rolf Drechsler:
Quantitative timing analysis of UML activity diagrams using statistical model checking. DATE 2016: 780-785 - [c450]Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Rolf Drechsler:
Fast logic synthesis for RRAM-based in-memory computing using Majority-Inverter Graphs. DATE 2016: 948-953 - [c449]Amr A. R. Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken, Rolf Drechsler:
Formal verification of integer multipliers by combining Gröbner basis with logic reduction. DATE 2016: 1048-1053 - [c448]Hoang Minh Le, Vladimir Herdt, Daniel Große, Rolf Drechsler:
Towards formal verification of real-world SystemC TLM peripheral models - a case study. DATE 2016: 1160-1163 - [c447]Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler:
Multi-objective BDD optimization for RRAM based circuit design. DDECS 2016: 46-51 - [c446]Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler:
VecTHOR: Low-cost compression architecture for IEEE 1149-compliant TAP controllers. ETS 2016: 1-6 - [c445]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. FDL 2016: 1-8 - [c444]Martin Ring, Jannis Stoppe, Christoph Lüth, Rolf Drechsler:
Change impact analysis for hardware designs from natural language to system level. FDL 2016: 1-7 - [c443]Amr A. R. Sayed-Ahmed, Daniel Große, Mathias Soeken, Rolf Drechsler:
Equivalence checking using Gröbner bases. FMCAD 2016: 169-176 - [c442]Saeideh Shirinzadeh, Mathias Soeken, Daniel Große, Rolf Drechsler:
Approximate BDD Optimization with Prioritized ε-Preferred Evolutionary Algorithm. GECCO (Companion) 2016: 79-80 - [c441]Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Compiled symbolic simulation for systemC. ICCAD 2016: 52 - [c440]Arun Chandrasekharan, Mathias Soeken, Daniel Große, Rolf Drechsler:
Approximation-aware rewriting of AIGs for error tolerant applications. ICCAD 2016: 83 - [c439]Robert Wille, Bing Li, Ulf Schlichtmann, Rolf Drechsler:
From biochips to quantum circuits: computer-aided design for emerging technologies. ICCAD 2016: 132 - [c438]Mehran Goli, Jannis Stoppe, Rolf Drechsler:
AIBA: An Automated Intra-cycle Behavioral Analysis for SystemC-based design exploration. ICCD 2016: 360-363 - [c437]Daniel Große, Hoang M. Le, Muhammad Hassan, Rolf Drechsler:
Guided lightweight Software test qualification for IP integration using Virtual Prototypes. ICCD 2016: 606-613 - [c436]Shuchishman Burman, Kamalika Datta, Robert Wille, Indranil Sengupta, Rolf Drechsler:
An improved gate library for logic synthesis of optical circuits. ISED 2016: 1-6 - [c435]Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler:
Generating and checking control logic in the HDL-based design of reversible circuits. ISED 2016: 7-12 - [c434]Rolf Drechsler, Stephan Eggersglüß, Nils Ellendt, Sebastian Huhn, Lutz Mädler:
Exploring superior structural materials using multi-objective optimization and formal techniques. ISED 2016: 13-17 - [c433]Jonas Gomes Filho, Nils Przigoda, Robert Wille, Rolf Drechsler:
Towards a model-based verification methodology for Complex Swarm Systems (Invited paper). ISED 2016: 18-23 - [c432]Zaid Al-Wardi, Robert Wille, Rolf Drechsler:
Re-Writing HDL Descriptions for Line-Aware Synthesis of Reversible Circuits. ISMVL 2016: 31-36 - [c431]Nils Przigoda, Gerhard W. Dueck, Robert Wille, Rolf Drechsler:
Fault Detection in Parity Preserving Reversible Circuits. ISMVL 2016: 44-49 - [c430]Nabila Abdessaied, Matthew Amy, Mathias Soeken, Rolf Drechsler:
Technology Mapping of Reversible Circuits to Clifford+T Quantum Circuits. ISMVL 2016: 150-155 - [c429]Laxmidhar Biswal, Chandan Bandyopadhyay, Anupam Chattopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation. ISMVL 2016: 156-161 - [c428]Rolf Drechsler, Serge Autexier, Christoph Lüth:
Model-Based Specification and Refinement for Cyber-Physical Systems. LDIC 2016: 3-17 - [c427]Arun Chandrasekharan, Daniel Große, Mathias Soeken, Rolf Drechsler:
Symbolic Error Metric Determination for Approximate Computing. MBMV 2016: 75-76 - [c426]Nils Przigoda, Jonas Gomes Filho, Philipp Niemann, Robert Wille, Rolf Drechsler:
Frame conditions in symbolic representations of UML/OCL models. MEMOCODE 2016: 65-70 - [c425]Judith Peters, Nils Przigoda, Robert Wille, Rolf Drechsler:
Clocks vs. instants relations: Verifying CCSL time constraints in UML/MARTE models. MEMOCODE 2016: 78-84 - [c424]Nils Przigoda, Frank Hilken, Judith Peters, Robert Wille, Martin Gogolla, Rolf Drechsler:
Integrating an SMT-Based ModelFinder into USE. MoDeVVa@MoDELS 2016: 40-45 - [c423]Nils Przigoda, Robert Wille, Rolf Drechsler:
Ground setting properties for an efficient translation of OCL in SMT-based model finding. MoDELS 2016: 261-271 - [c422]Robert Wille, Oliver Keszöcze, Lars Othmer, Michael Kirkedal Thomsen, Rolf Drechsler:
Initial Ideas for Automatic Design and Verification of Control Logic in Reversible HDLs - Work in Progress Report. RC 2016: 160-166 - [c421]Robert Wille, Anupam Chattopadhyay, Rolf Drechsler:
From reversible logic to quantum circuits: Logic design for an emerging technology. SAMOS 2016: 268-274 - [c420]Rolf Drechsler, Jannis Stoppe:
Hardware/Software Co-Visualization on the Electronic System Level Using SystemC. VLSID 2016: 44-49 - [c419]Laxmidhar Biswal, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman:
Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library. VLSID 2016: 573-574 - [e13]Rolf Drechsler, Robert Wille:
2016 Forum on Specification and Design Languages, FDL 2016, Bremen, Germany, September 14-16, 2016. IEEE 2016, ISBN 979-10-92279-17-7 [contents] - 2015
- [b13]Mathias Soeken, Rolf Drechsler:
Formal Specification Level - Concepts, Methods, and Algorithms. Springer 2015, ISBN 978-3-319-08698-9, pp. I-VIII, 1-138 - [j91]Cornelia S. Große, Lisa Jungmann, Rolf Drechsler:
Benefits of illustrations and videos for technical documentations. Comput. Hum. Behav. 45: 109-120 (2015) - [j90]Robert Wille, Oliver Keszöcze, Rolf Drechsler, Tobias Boehnisch, Alexander Kroker:
Scalable One-Pass Synthesis for Digital Microfluidic Biochips. IEEE Des. Test 32(6): 41-50 (2015) - [j89]Nicole Drechsler, André Sülflow, Rolf Drechsler:
Incorporating user preferences in many-objective optimization using relation ε-preferred. Nat. Comput. 14(3): 469-483 (2015) - [j88]Jannis Stoppe, Rolf Drechsler:
Analyzing SystemC Designs: SystemC Analysis Approaches for Varying Applications. Sensors 15(5): 10399-10421 (2015) - [c418]Robert Wille, Oliver Keszöcze, Clemens Hopfmuller, Rolf Drechsler:
Reverse BDD-based synthesis for splitter-free optical circuits. ASP-DAC 2015: 172-177 - [c417]Aaron Lye, Robert Wille, Rolf Drechsler:
Determining the minimal number of swap gates for multi-dimensional nearest neighbor quantum circuits. ASP-DAC 2015: 178-183 - [c416]Vladimir Herdt, Hoang Minh Le, Daniel Große, Rolf Drechsler:
Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. ATVA 2015: 228-233 - [c415]Vladimir Herdt, Hoang Minh Le, Rolf Drechsler:
Verifying SystemC using stateful symbolic simulation. DAC 2015: 49:1-49:6 - [c414]Judith Peters, Robert Wille, Nils Przigoda, Ulrich Kühne, Rolf Drechsler:
A generic representation of CCSL time constraints for UML/MARTE models. DAC 2015: 122:1-122:6 - [c413]Jannis Stoppe, Robert Wille, Rolf Drechsler:
Automated feature localization for dynamically generated SystemC designs. DATE 2015: 277-280 - [c412]Nils Przigoda, Robert Wille, Rolf Drechsler:
Contradiction Analysis for Inconsistent Formal Models. DDECS 2015: 171-176 - [c411]Arman Allahyari-Abhari, Mathias Soeken, Rolf Drechsler:
Requirement Phrasing Assistance Using Automatic Quality Assessment. DDECS 2015: 183-188 - [c410]Nils Przigoda, Robert Wille, Rolf Drechsler:
Leveraging the Analysis for Invariant Independence in Formal System Models. DSD 2015: 359-366 - [c409]Nils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler:
Verification-Driven Design Across Abstraction Levels: A Case Study. DSD 2015: 375-382 - [c408]Mathias Soeken, Baruch Sterin, Rolf Drechsler, Robert K. Brayton:
Simulation Graphs for Reverse Engineering. FMCAD 2015: 152-159 - [c407]Saeideh Shirinzadeh, Mathias Soeken, Rolf Drechsler:
Multi-Objective BDD Optimization with Evolutionary Algorithms. GECCO 2015: 751-758 - [c406]Rolf Drechsler, Robert Wille:
Reversible computation. IGSC 2015: 1-5 - [c405]Robert Wille, Rolf Drechsler:
Formal Methods for Emerging Technologies. ICCAD 2015: 65-70 - [c404]Oliver Keszöcze, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler:
A General and Exact Routing Methodology for Digital Microfluidic Biochips. ICCAD 2015: 874-881 - [c403]Arighna Deb, Robert Wille, Rolf Drechsler, Debesh K. Das:
An Efficient Reduction of Common Control Lines for Reversible Circuit Optimization. ISMVL 2015: 14-19 - [c402]Arman Allahyari-Abhari, Robert Wille, Rolf Drechsler:
An Examination of the NCV-|u1 > Quantum Library Based on Minimal Circuits. ISMVL 2015: 42-47 - [c401]Amr A. R. Sayed-Ahmed, Ulrich Kühne, Daniel Große, Rolf Drechsler:
Recurrence Relations Revisited: Scalable Verification of Bit Level Multiplier Circuits. ISVLSI 2015: 1-6 - [c400]Nils Przigoda, Robert Wille, Rolf Drechsler:
Verbesserung der Fehlersuche in inkonsistenten formalen Modellen (Erweiterte Zusammenfassung). MBMV 2015: 165-172 - [c399]Nils Przigoda, Judith Peters, Mathias Soeken, Robert Wille, Rolf Drechsler:
Towards an Automatic Approach for Restricting UML/OCL Invariability Clauses. MoDeVVa@MoDELS 2015: 44-47 - [c398]Nils Przigoda, Christoph Hilken, Robert Wille, Jan Peleska, Rolf Drechsler:
Checking concurrent behavior in UML/OCL models. MoDELS 2015: 176-185 - [c397]Nabila Abdessaied, Mathias Soeken, Rolf Drechsler:
Technology Mapping for Single Target Gate Based Circuits Using Boolean Functional Decomposition. RC 2015: 219-232 - [c396]Zaid Al-Wardi, Robert Wille, Rolf Drechsler:
Towards Line-Aware Realizations of Expressions for HDL-Based Synthesis of Reversible Circuits. RC 2015: 233-247 - [c395]Rolf Drechsler, Martin Fränzle, Robert Wille:
Envisioning self-verification of electronic systems. ReCoSoC 2015: 1-6 - [c394]Arun Chandrasekharan, Kenneth Schmitz, Ulrich Kühne, Rolf Drechsler:
Ensuring safety and reliability of IP-based system design - A container approach. RSP 2015: 76-82 - [c393]Melanie Diepenbeck, Rolf Drechsler:
Behavior Driven Development for Tests and Verification. SyDe Summer School 2015: 275-277 - [c392]Judith Peters, Rolf Drechsler:
Analyzing and Simulating Time Descriptions from UML/MARTE CCSL. SyDe Summer School 2015: 293-295 - [c391]Eleonora Schönborn, Rolf Drechsler:
Design and Synthesis of Reversible Circuits using Hardware Description Languages. SyDe Summer School 2015: 296-298 - [c390]Julia Seiter, Rolf Drechsler:
Development of Consistent Formal Models. SyDe Summer School 2015: 302-304 - [c389]Mathias Soeken, Julia Seiter, Rolf Drechsler:
Coverage of OCL Operation Specifications and Invariants. TAP@STAF 2015: 191-207 - [c388]Nabila Abdessaied, Mathias Soeken, Gerhard W. Dueck, Rolf Drechsler:
Reversible circuit rewriting with simulated annealing. VLSI-SoC 2015: 286-291 - [c387]Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits. VLSID 2015: 435-440 - [e12]Rolf Drechsler, Ulrich Kühne:
Formal Modeling and Verification of Cyber-Physical Systems, 1st International Summer School on Methods and Tools for the Design of Digital Systems, Bremen, Germany, September 2015. Springer 2015, ISBN 978-3-658-09993-0 [contents] - 2014
- [j87]Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler:
Trading off circuit lines and gate costs in the synthesis of reversible logic. Integr. 47(2): 284-294 (2014) - [j86]Nabila Abdessaied, Mathias Soeken, Michael Kirkedal Thomsen, Rolf Drechsler:
Upper bounds for reversible circuits based on Young subgroups. Inf. Process. Lett. 114(6): 282-286 (2014) - [j85]Rolf Drechsler:
Testing integrated circuits. it Inf. Technol. 56(4): 148-149 (2014) - [j84]Stephan Eggersglüß, Rolf Drechsler:
An effective fault ordering heuristic for SAT-based dynamic test compaction techniques. it Inf. Technol. 56(4): 157-164 (2014) - [j83]Robert Wille, Rolf Drechsler, Mehdi Baradaran Tahoori:
Introduction to the Special Issue on Reversible Computation. ACM J. Emerg. Technol. Comput. Syst. 11(2): 8:1-8:2 (2014) - [j82]Robert Wille, Aaron Lye, Rolf Drechsler:
Considering nearest neighbor constraints of quantum circuits at the reversible circuit level. Quantum Inf. Process. 13(2): 185-199 (2014) - [j81]Robert Wille, Aaron Lye, Rolf Drechsler:
Exact Reordering of Circuit Lines for Nearest Neighbor Quantum Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1818-1831 (2014) - [j80]Kamalika Datta, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
An Approach to Reversible Logic Synthesis Using Input and Output Permutations. Trans. Comput. Sci. 24: 92-110 (2014) - [j79]Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler:
Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic. Trans. Comput. Sci. 24: 129-146 (2014) - [c386]Philipp Niemann, Robert Wille, Rolf Drechsler:
Efficient synthesis of quantum circuits implementing clifford group operations. ASP-DAC 2014: 483-488 - [c385]Robert Wille, Aaron Lye, Rolf Drechsler:
Optimal SWAP gate insertion for nearest neighbor quantum circuits. ASP-DAC 2014: 489-494 - [c384]Marc Herbstritt, Rolf Drechsler:
Der h2-lndex: Zur vermessenen Vermessung der wissenschaftlichen Welt. Aspekte der Technischen Informatik 2014: 35-50 - [c383]Jan-Hendrik Oetjens, Nico Bannow, Markus Becker, Oliver Bringmann, Andreas Burger, Moomen Chaari, Samarjit Chakraborty, Rolf Drechsler, Wolfgang Ecker, Kim Grüttner, Thomas Kruse, Christoph Kuznik, Hoang Minh Le, Andreas Mauderer, Wolfgang Müller, Daniel Müller-Gritschneder, Frank Poppen, Hendrik Post, Sebastian Reiter, Wolfgang Rosenstiel, S. Roth, Ulf Schlichtmann, Andreas von Schwerin, Bogdan-Andrei Tabacaru, Alexander Viehl:
Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges. DAC 2014: 113:1-113:6 - [c382]Oliver Keszöcze, Robert Wille, Tsung-Yi Ho, Rolf Drechsler:
Exact One-pass Synthesis of Digital Microfluidic Biochips. DAC 2014: 142:1-142:6 - [c381]Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev:
Panel: Future SoC verification methodology: UVM evolution or revolution? DATE 2014: 1-5 - [c380]Hoang Minh Le, Rolf Drechsler:
Towards verifying determinism of SystemC designs. DATE 2014: 1-4 - [c379]Eleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
Optimizing DD-based synthesis of reversible circuits using negative control lines. DDECS 2014: 129-134 - [c378]Shuo Yang, Robert Wille, Rolf Drechsler:
Improving Coverage of Simulation-Based Verification by Dedicated Stimuli Generation. DSD 2014: 599-606 - [c377]Bernd Becker, Rolf Drechsler, Stephan Eggersglüß, Matthias Sauer:
Recent advances in SAT-based ATPG: Non-standard fault models, multi constraints and optimization. DTIS 2014: 1-10 - [c376]Stephan Eggersglüß, Kenneth Schmitz, Rene Krenz-Baath, Rolf Drechsler:
Optimization-based multiple target test generation for highly compacted test sets. ETS 2014: 1-6 - [c375]Christoph Hilken, Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler:
Verifying consistency between activity diagrams and their corresponding OCL contracts. FDL 2014: 1-7 - [c374]Heinz Riener, Mathias Soeken, Clemens Werther, Görschwin Fey, Rolf Drechsler:
MetaSMT: a unified interface to SMT-LIB2. FDL 2014: 1-6 - [c373]Julia Seiter, Robert Wille, Ulrich Kühne, Rolf Drechsler:
Automatic refinement checking for formal system models. FDL 2014: 1-8 - [c372]Mathias Soeken, Christopher B. Harris, Nabila Abdessaied, Ian G. Harris, Rolf Drechsler:
Automating the translation of assertions using natural language processing techniques. FDL 2014: 1-8 - [c371]Oliver Keszöcze, Robert Wille, Rolf Drechsler:
Exact routing for digital microfluidic biochips with temporary blockages. ICCAD 2014: 405-410 - [c370]Rolf Drechsler, Mathias Soeken, Robert Wille:
Automated and quality-driven requirements engineering. ICCAD 2014: 586-590 - [c369]Judith Peters, Robert Wille, Rolf Drechsler:
Generating SystemC Implementations for Clock Constraints Specified in UML/MARTE CCSL. ICECCS 2014: 116-125 - [c368]Stefan A. Wiesner, Christian Gorldt, Mathias Soeken, Klaus-Dieter Thoben, Rolf Drechsler:
Requirements Engineering for Cyber-Physical Systems - Challenges in the Context of "Industrie 4.0". APMS (1) 2014: 281-288 - [c367]Rolf Drechsler, Ulrich Kühne:
Safe IP Integration Using Container Modules. ISED 2014: 1-4 - [c366]Chandan Bandyopadhyay, Hafizur Rahaman, Rolf Drechsler:
A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit. ISMVL 2014: 109-114 - [c365]Aljoscha Windhorst, Hoang Minh Le, Daniel Große, Rolf Drechsler:
Funktionale Abdeckungsanalyse von C-Programmen. MBMV 2014: 201-204 - [c364]Mathias Soeken, Max Nitze, Rolf Drechsler:
Formale Methoden für Alle. MBMV 2014: 213-216 - [c363]Heinz Riener, Oliver Keszöcze, Rolf Drechsler, Görschwin Fey:
A Logic for Cardinality Constraints (Extended Abstract). MBMV 2014: 217-220 - [c362]Robert Wille, Jannis Stoppe, Eleonora Schönborn, Kamalika Datta, Rolf Drechsler:
RevVis: Visualization of Structures and Properties in Reversible Circuits. RC 2014: 111-124 - [c361]Nabila Abdessaied, Mathias Soeken, Rolf Drechsler:
Quantum Circuit Optimization by Hadamard Gate Reduction. RC 2014: 149-162 - [c360]D. Michael Miller, Mathias Soeken, Rolf Drechsler:
Mapping NCV Circuits to Optimized Clifford+T Circuits. RC 2014: 163-175 - [c359]Philipp Niemann, Robert Wille, Rolf Drechsler:
Equivalence Checking in Multi-level Quantum Systems. RC 2014: 201-215 - [c358]Shuo Yang, Robert Wille, Rolf Drechsler:
Determining Cases of Scenarios to Improve Coverage in Simulation-based Verification. SBCCI 2014: 11:1-11:7 - [c357]Jannis Stoppe, Robert Wille, Rolf Drechsler:
Validating SystemC Implementations Against Their Formal Specifications. SBCCI 2014: 13:1-13:8 - [c356]Rolf Drechsler, Hoang Minh Le, Mathias Soeken:
Self-Verification as the Key Technology for Next Generation Electronic Systems. SBCCI 2014: 15:1-15:4 - [c355]Fritjof Bornebusch, Glaucia Cancino, Melanie Diepenbeck, Rolf Drechsler, Smith Djomkam, Alvine Nzeungang Fanseu, Maryam Jalali, Marc Michael, Jamal Mohsen, Max Nitze, Christina Plump, Mathias Soeken, Hubert Fred Tchambo, Toni, Henning Ziegler:
iTac: Aspect Based Sentiment Analysis using Sentiment Trees and Dictionaries. SemEval@COLING 2014: 351-355 - [c354]Melanie Diepenbeck, Ulrich Kühne, Mathias Soeken, Rolf Drechsler:
Behaviour Driven Development for Tests and Verification. TAP@STAF 2014: 61-77 - [e11]Rolf Drechsler:
Aspekte der Technischen Informatik - Festschrift zum 60. Geburtstag von Bernd Becker. MV-Wissenschaft 2014, ISBN 978-3-9564523-5-2 [contents] - [i9]Mathias Soeken, Nabila Abdessaied, Rolf Drechsler:
A framework for reversible circuit complexity. CoRR abs/1407.5878 (2014) - [i8]Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler:
Embedding of Large Boolean Functions for Reversible Logic. CoRR abs/1408.3586 (2014) - [i7]Mathias Soeken, Laura Tague, Gerhard W. Dueck, Rolf Drechsler:
Ancilla-free synthesis of large reversible functions using binary decision diagrams. CoRR abs/1408.3955 (2014) - 2013
- [j78]Daniel Große, Görschwin Fey, Rolf Drechsler:
Enhanced Formal Verification Flow for Circuits Integrating Debugging and Coverage Analysis. Electron. Commun. Eur. Assoc. Softw. Sci. Technol. 62 (2013) - [j77]Elsa Andrea Kirchner, Rolf Drechsler:
A formal model for embedded brain reading. Ind. Robot 40(6): 530-540 (2013) - [j76]Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler:
Effect of Negative Control Lines on the Exact Synthesis of Reversible Circuits. J. Multiple Valued Log. Soft Comput. 21(5-6): 627-640 (2013) - [c353]Robert Wille, Nils Przigoda, Rolf Drechsler:
A compact and efficient SAT encoding for quantum circuits. AFRICON 2013: 1-6 - [c352]Robert Wille, Simon Stelter, Rolf Drechsler:
Exploiting reversibility in the complete simulation of reversible circuits. AFRICON 2013: 1-6 - [c351]Robert Wille, Mathias Soeken, Christian Otterstedt, Rolf Drechsler:
Improving the mapping of reversible circuits to quantum circuits using multiple target lines. ASP-DAC 2013: 145-150 - [c350]Hoang Minh Le, Daniel Große, Vladimir Herdt, Rolf Drechsler:
Verifying SystemC using an intermediate verification language and symbolic simulation. DAC 2013: 116:1-116:6 - [c349]Hoang Minh Le, Daniel Große, Rolf Drechsler:
Scalable fault localization for SystemC TLM designs. DATE 2013: 35-38 - [c348]Julia Seiter, Robert Wille, Mathias Soeken, Rolf Drechsler:
Determining relevant model elements for the verification of UML/OCL specifications. DATE 2013: 1189-1192 - [c347]Robert Wille, Martin Gogolla, Mathias Soeken, Mirco Kuhlmann, Rolf Drechsler:
Towards a generic verification methodology for system models. DATE 2013: 1193-1196 - [c346]Rolf Drechsler, Mathias Soeken:
Hardware-Software Co-Visualization: Developing systems in the holodeck. DDECS 2013: 1-4 - [c345]Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler:
Minimal Stimuli Generation in Simulation-Based Verification. DSD 2013: 439-444 - [c344]Jannis Stoppe, Robert Wille, Rolf Drechsler:
Cone of Influence Analysis at the Electronic System Level Using Machine Learning. DSD 2013: 582-587 - [c343]Rolf Drechsler, Mathias Soeken, Robert Wille:
Text statt C++: Automatisierung des Systementwurfs mit Hilfe natürlicher Sprachverarbeitung. GI-Jahrestagung 2013: 151 - [c342]Stephan Eggersglüß, Robert Wille, Rolf Drechsler:
Improved SAT-based ATPG: more constraints, better compaction. ICCAD 2013: 85-90 - [c341]Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler:
Towards automatic scenario generation from coverage information. AST 2013: 82-88 - [c340]Kamalika Datta, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
An evolutionary approach to reversible logic synthesis using output permutation. IDT 2013: 1-6 - [c339]Mathias Soeken, Rolf Drechsler:
Grammar-based program generation based on model finding. IDT 2013: 1-5 - [c338]Nicole Drechsler, André Sülflow, Rolf Drechsler:
Incorporating User Preferences in Many-Objective Optimization using Relation Epsilon-Preferred. IJCCI 2013: 67-74 - [c337]Robert Wille, Hongyan Zhang, Rolf Drechsler:
Fault Ordering for Automatic Test Pattern Generation of Reversible Circuits. ISMVL 2013: 29-34 - [c336]Laura Tague, Mathias Soeken, Shin-ichi Minato, Rolf Drechsler:
Debugging of Reversible Circuits Using pDDs. ISMVL 2013: 316-321 - [c335]Nabila Abdessaied, Mathias Soeken, Robert Wille, Rolf Drechsler:
Exact Template Matching Using Boolean Satisfiability. ISMVL 2013: 328-333 - [c334]Jannis Stoppe, Robert Wille, Rolf Drechsler:
Data extraction from SystemC designs using debug symbols and the SystemC API. ISVLSI 2013: 26-31 - [c333]Rolf Drechsler, Melanie Diepenbeck, Stephan Eggersglüß, Robert Wille:
PASSAT 2.0: A multi-functional SAT-based testing framework. LATW 2013: 1 - [c332]Mathias Soeken, Robert Wille, Eugen Kuksa, Rolf Drechsler:
Generierung von OCL-Ausdrücken aus natürlichsprachlichen Beschreibungen. MBMV 2013: 99-103 - [c331]Robert Wille, Rolf Drechsler:
The SyReC hardware description language: Enabling scalable synthesis of reversible circuits. MWSCAS 2013: 1063-1066 - [c330]Philipp Niemann, Robert Wille, Rolf Drechsler:
On the "Q" in QMDDs: Efficient Representation of Quantum Functionality in the QMDD Data-Structure. RC 2013: 125-140 - [c329]Arighna Deb, Debesh K. Das, Hafizur Rahaman, Bhargab B. Bhattacharya, Robert Wille, Rolf Drechsler:
Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. RC 2013: 182-195 - [c328]Kamalika Datta, Gaurav Rathi, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler:
Exploiting Negative Control Lines in the Optimization of Reversible Circuits. RC 2013: 209-220 - [c327]Nabila Abdessaied, Robert Wille, Mathias Soeken, Rolf Drechsler:
Reducing the Depth of Quantum Circuits Using Additional Circuit Lines. RC 2013: 221-233 - [i6]Mathias Soeken, D. Michael Miller, Rolf Drechsler:
On quantum circuits employing roots of the Pauli matrices. CoRR abs/1308.2493 (2013) - 2012
- [b12]Stephan Eggersglüß, Rolf Drechsler:
High Quality Test Pattern Generation and Boolean Satisfiability. Springer 2012, ISBN 978-1-4419-9975-7, pp. I-XVIII, 1-193 - [j75]Stephan Eggersglüß, Rolf Drechsler:
A Highly Fault-Efficient SAT-Based ATPG Flow. IEEE Des. Test Comput. 29(4): 63-70 (2012) - [j74]Rolf Drechsler, Irek Ulidowski, Robert Wille:
Foreword: Special Issue on Reversible Computation. J. Multiple Valued Log. Soft Comput. 18(1): 1-3 (2012) - [j73]Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler:
RevKit: A Toolkit for Reversible Circuit Design. J. Multiple Valued Log. Soft Comput. 18(1): 55-65 (2012) - [j72]D. Michael Miller, Robert Wille, Rolf Drechsler:
Reducing Reversible Circuit Cost by Adding Lines. J. Multiple Valued Log. Soft Comput. 19(1-3): 185-201 (2012) - [j71]Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler:
Equivalence Checking of Reversible Circuits. J. Multiple Valued Log. Soft Comput. 19(4): 361-378 (2012) - [j70]Hoang Minh Le, Daniel Große, Rolf Drechsler:
Automatic TLM Fault Localization for SystemC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(8): 1249-1262 (2012) - [c326]Mathias Soeken, Robert Wille, Christoph Hilken, Nils Przigoda, Rolf Drechsler:
Synthesis of reversible circuits with minimal lines for large functions. ASP-DAC 2012: 85-92 - [c325]Marcio Ferreira da Silva Oliveira, Christoph Kuznik, Hoang Minh Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, Volkan Esen:
The system verification methodology for advanced TLM verification. CODES+ISSS 2012: 313-322 - [c324]Finn Haedicke, Daniel Große, Rolf Drechsler:
A guiding coverage metric for formal verification. DATE 2012: 617-622 - [c323]Robert Wille, Rolf Drechsler, Christof Osewold, Alberto García Ortiz:
Automatic design of low-power encoders using reversible circuit synthesis. DATE 2012: 1036-1041 - [c322]Robert Wille, Mathias Soeken, Rolf Drechsler:
Debugging of inconsistent UML/OCL models. DATE 2012: 1078-1083 - [c321]Mathias Soeken, Robert Wille, Rolf Drechsler:
Eliminating invariants in UML/OCL models. DATE 2012: 1142-1145 - [c320]Stephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler:
A new SAT-based ATPG for generating highly compacted test sets. DDECS 2012: 230-235 - [c319]Shuo Yang, Robert Wille, Daniel Große, Rolf Drechsler:
Coverage-Driven Stimuli Generation. DSD 2012: 525-528 - [c318]Rolf Drechsler, Mathias Soeken, Robert Wille:
Formal Specification Level. FDL (Selected Papers) 2012: 37-52 - [c317]Rolf Drechsler, Mathias Soeken, Robert Wille:
Formal Specification Level: Towards verification-driven design based on natural language processing. FDL 2012: 53-58 - [c316]Marc Michael, Daniel Große, Rolf Drechsler:
Localizing features of ESL models for design understanding. FDL 2012: 120-125 - [c315]Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler:
Complete and effective robustness checking by means of interpolation. FMCAD 2012: 82-90 - [c314]Rolf Drechsler, Melanie Diepenbeck, Daniel Große, Ulrich Kühne, Hoang Minh Le, Julia Seiter, Mathias Soeken, Robert Wille:
Completeness-Driven Development. ICGT 2012: 38-50 - [c313]Melanie Diepenbeck, Mathias Soeken, Daniel Große, Rolf Drechsler:
Behavior Driven Development for circuit design and verification. HLDVT 2012: 9-16 - [c312]Rolf Drechsler, Ian G. Harris, Robert Wille:
Generating formal system models from natural language descriptions. HLDVT 2012: 164-165 - [c311]Roderick Bloem, Rolf Drechsler, Görschwin Fey, Alexander Finder, Georg Hofferek, Robert Könighofer, Jaan Raik, Urmas Repinski, André Sülflow:
FoREnSiC- An Automatic Debugging Environment for C Programs. Haifa Verification Conference 2012: 260-265 - [c310]Rolf Drechsler, Robert Wille:
Synthesis of Reversible Circuits Using Decision Diagrams. ISED 2012: 1-5 - [c309]Hoang M. Le, Daniel Große, Rolf Drechsler:
From Requirements and Scenarios to ESL Design in SystemC. ISED 2012: 183-187 - [c308]Robert Wille, Mathias Soeken, Nils Przigoda, Rolf Drechsler:
Exact Synthesis of Toffoli Gate Circuits with Negative Control Lines. ISMVL 2012: 69-74 - [c307]Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler:
Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. ISMVL 2012: 173-178 - [c306]Mathias Soeken, Robert Wille, Christian Otterstedt, Rolf Drechsler:
A Synthesis Flow for Sequential Reversible Circuits. ISMVL 2012: 299-304 - [c305]Finn Haedicke, Hoang Minh Le, Daniel Große, Rolf Drechsler:
CRAVE: An advanced constrained random verification environment for SystemC. ISSoC 2012: 1-7 - [c304]Robert Wille, Mathias Soeken, Eleonora Schönborn, Rolf Drechsler:
Circuit Line Minimization in the HDL-Based Synthesis of Reversible Logic. ISVLSI 2012: 213-218 - [c303]Finn Haedicke, Hoang Minh Le, Daniel Große, Rolf Drechsler:
CRAVE: An Advanced Constrained RAndom Verification Environment for SystemC. MBMV 2012: 37-48 - [c302]Julia Seiter, Mathias Soeken, Robert Wille, Rolf Drechsler:
Property Checking of Quantum Circuits Using Quantum Multiple-Valued Decision Diagrams. RC 2012: 183-196 - [c301]Mathias Soeken, Robert Wille, Shin-ichi Minato, Rolf Drechsler:
Using πDDs in the Design of Reversible Circuits. RC 2012: 197-203 - [c300]Mathias Soeken, Robert Wille, Rolf Drechsler:
Assisted Behavior Driven Development Using Natural Language Processing. TOOLS (50) 2012: 269-287 - [c299]Rolf Drechsler, Robert Wille:
Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper). VDAT 2012: 383-392 - [e10]Cecilia Di Chio, Alexandros Agapitos, Stefano Cagnoni, Carlos Cotta, Francisco Fernández de Vega, Gianni A. Di Caro, Rolf Drechsler, Anikó Ekárt, Anna Isabel Esparcia-Alcázar, Muddassar Farooq, William B. Langdon, Juan Julián Merelo Guervós, Mike Preuss, Hendrik Richter, Sara Silva, Anabela Simões, Giovanni Squillero, Ernesto Tarantino, Andrea Tettamanzi, Julian Togelius, Neil Urquhart, Sima Uyar, Georgios N. Yannakakis:
Applications of Evolutionary Computation - EvoApplications 2012: EvoCOMNET, EvoCOMPLEX, EvoFIN, EvoGAMES, EvoHOT, EvoIASP, EvoNUM, EvoPAR, EvoRISK, EvoSTIM, and EvoSTOC, Málaga, Spain, April 11-13, 2012, Proceedings. Lecture Notes in Computer Science 7248, Springer 2012, ISBN 978-3-642-29177-7 [contents] - 2011
- [j69]Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler:
Debugging reversible circuits. Integr. 44(1): 51-61 (2011) - [j68]Mehdi Saeedi, Robert Wille, Rolf Drechsler:
Synthesis of quantum circuits for linear nearest neighbor architectures. Quantum Inf. Process. 10(3): 355-377 (2011) - [j67]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Effective Robustness Analysis Using Bounded Model Checking Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(8): 1239-1252 (2011) - [j66]Stephan Eggersglüß, Rolf Drechsler:
Efficient Data Structures and Methodologies for SAT-Based ATPG Providing High Fault Coverage in Industrial Application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(9): 1411-1415 (2011) - [c298]Hongyan Zhang, Stefan Frehse, Robert Wille, Rolf Drechsler:
Determining minimal testsets for reversible circuits using Boolean satisfiability. AFRICON 2011: 1-6 - [c297]Hongyan Zhang, Robert Wille, Rolf Drechsler:
Improved Fault Diagnosis for Reversible Circuits. Asian Test Symposium 2011: 207-212 - [c296]Mathias Soeken, Robert Wille, Rolf Drechsler:
Verifying dynamic aspects of UML models. DATE 2011: 1077-1082 - [c295]Robert Wille, Oliver Keszöcze, Rolf Drechsler:
Determining the minimal number of lines for large reversible circuits. DATE 2011: 1204-1207 - [c294]Stephan Eggersglüß, Rolf Drechsler:
As-Robust-As-Possible test generation in the presence of small delay defects using pseudo-Boolean optimization. DATE 2011: 1291-1296 - [c293]Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler:
Automatic property generation for the formal verification of bus bridges. DDECS 2011: 417-422 - [c292]Mohamed Bawadekji, Daniel Große, Rolf Drechsler:
TLM protocol compliance checking at the Electronic System Level. DDECS 2011: 435-440 - [c291]Rolf Drechsler, Alexander Finder, Robert Wille:
Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms. EvoApplications (2) 2011: 151-161 - [c290]Marc Michael, Daniel Große, Rolf Drechsler:
Analyzing dependability measures at the Electronic System Level. FDL 2011: 1-8 - [c289]Sebastian Offermann, Robert Wille, Rolf Drechsler:
Efficient realization of control logic in reversible circuits. FDL 2011: 1-7 - [c288]Finn Haedicke, Stefan Frehse, Görschwin Fey, Daniel Große, Rolf Drechsler:
metaSMT: Focus on Your Application not on Solver Integration. DIFTS@FMCAD 2011 - [c287]Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler:
Simulation-based equivalence checking between SystemC models at different levels of abstraction. ACM Great Lakes Symposium on VLSI 2011: 223-228 - [c286]Rolf Drechsler, Robert Wille:
From Truth Tables to Programming Languages: Progress in the Design of Reversible Circuits. ISMVL 2011: 78-85 - [c285]Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler:
Designing a RISC CPU in Reversible Logic. ISMVL 2011: 170-175 - [c284]Kim Grüttner, Andreas Herrholz, Ulrich Kühne, Daniel Große, Achim Rettberg, Wolfgang Nebel, Rolf Drechsler:
Towards Dependability-Aware Design of Hardware Systems Using Extended Program State Machines. ISORC Workshops 2011: 181-188 - [c283]Robert Wille, Hongyan Zhang, Rolf Drechsler:
ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization. ISVLSI 2011: 120-125 - [c282]Mathias Soeken, Ulrich Kühne, Martin Freibothe, Görschwin Fey, Rolf Drechsler:
Towards Automatic Property Generation for the Formal Verification of Bus Bridges. MBMV 2011: 183-192 - [c281]Robert Wille, Mathias Soeken, Daniel Große, Eleonora Schönborn, Rolf Drechsler:
Designing a RISC CPU in Reversible Logic. MBMV 2011: 249-258 - [c280]Daniel Große, Markus Groß, Ulrich Kühne, Rolf Drechsler:
Simulation-based Equivalence Checking between SystemC Models at Different Levels of Abstraction. MBMV 2011: 269-278 - [c279]Mathias Soeken, Robert Wille, Rolf Drechsler:
Towards automatic determination of problem bounds for object instantiation in static model verification. MoDeVVa@MoDELS 2011: 2:1-2:4 - [c278]Mathias Soeken, Stefan Frehse, Robert Wille, Rolf Drechsler:
RevKit: An Open Source Toolkit for the Design of Reversible Circuits. RC 2011: 64-76 - [c277]Mathias Soeken, Robert Wille, Rolf Drechsler:
Encoding OCL Data Types for SAT-Based Verification of UML/OCL Models. TAP@TOOLS 2011: 152-170 - [e9]Cecilia Di Chio, Anthony Brabazon, Gianni A. Di Caro, Rolf Drechsler, Muddassar Farooq, Jörn Grahl, Gary Greenfield, Christian Prins, Juan Romero, Giovanni Squillero, Ernesto Tarantino, Andrea Tettamanzi, Neil Urquhart, A. Sima Etaner-Uyar:
Applications of Evolutionary Computation - EvoApplications 2011: EvoCOMNET, EvoFIN, EvoHOT, EvoMUSART, EvoSTIM, and EvoTRANSLOG, Torino, Italy, April 27-29, 2011, Proceedings, Part II. Lecture Notes in Computer Science 6625, Springer 2011, ISBN 978-3-642-20519-4 [contents] - [i5]Mehdi Saeedi, Robert Wille, Rolf Drechsler:
Synthesis of Quantum Circuits for Linear Nearest Neighbor Architectures. CoRR abs/1110.6412 (2011) - 2010
- [b11]Robert Wille, Rolf Drechsler:
Towards a Design Flow for Reversible Logic. Springer 2010, ISBN 978-90-481-9578-7, pp. I-XIII, 1-184 - [b10]Frank Rogin, Rolf Drechsler:
Debugging at the Electronic System Level. Springer 2010, ISBN 978-90-481-9254-0, pp. I-XIX, 1-199 - [b9]Daniel Große, Rolf Drechsler:
Quality-Driven SystemC Design. Springer 2010, ISBN 978-90-481-3630-8 - [j65]Ulrich Kühne, Daniel Große, Rolf Drechsler:
Towards Fully Automatic Synthesis of Embedded Software. IEEE Embed. Syst. Lett. 2(3): 53-57 (2010) - [j64]Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Rolf Drechsler:
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics. J. Electron. Test. 26(3): 307-322 (2010) - [j63]Robert Wille, Rolf Drechsler:
BDD-Based Synthesis of Reversible Logic. Int. J. Appl. Metaheuristic Comput. 1(4): 25-41 (2010) - [j62]Robert Wille, Rolf Drechsler:
Synthese reversibler Logik (Synthesizing Reversible Logic). it Inf. Technol. 52(1): 30-38 (2010) - [j61]Görschwin Fey, André Sülflow, Stefan Frehse, Rolf Drechsler:
Automatische formale Verifikation der Fehlertoleranz von Schaltkreisen (Automated Formal Verification of Fault Tolerance for Circuits). it Inf. Technol. 52(4): 216-223 (2010) - [j60]Daniel Tille, Stephan Eggersglüß, Rolf Drechsler:
Incremental Solving Techniques for SAT-based ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1125-1130 (2010) - [c276]Robert Wille, Mathias Soeken, Rolf Drechsler:
Reducing the number of lines in reversible circuits. DAC 2010: 647-652 - [c275]Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler:
Verifying UML/OCL models using Boolean satisfiability. DATE 2010: 1341-1344 - [c274]Rolf Drechsler, Görschwin Fey:
Formal verification meets robustness checking - Techniques and challenges. DDECS 2010: 4 - [c273]Stefan Frehse, Görschwin Fey, Rolf Drechsler:
A better-than-worst-case robustness measure. DDECS 2010: 78-83 - [c272]Sebastian Offermann, Robert Wille, Gerhard W. Dueck, Rolf Drechsler:
Synthesizing multiplier in reversible logic. DDECS 2010: 335-340 - [c271]Mathias Soeken, Robert Wille, Gerhard W. Dueck, Rolf Drechsler:
Window optimization of reversible and quantum circuits. DDECS 2010: 341-345 - [c270]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
RobuCheck: A Robustness Checker for Digital Circuits. DSD 2010: 226-231 - [c269]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
RobuCheck: a robustness checker for digital circuits. DYADEM-FTS@EDCC 2010: 37-38 - [c268]Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler:
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. ETS 2010: 176-181 - [c267]Robert Wille, Sebastian Offermann, Rolf Drechsler:
SyReC: A Programming Language for Synthesis of Reversible Circuits. FDL 2010: 184-189 - [c266]André Sülflow, Rolf Drechsler:
Automatic Fault Localization for Programmable Logic Controllers. FORMS/FORMAT 2010: 247-256 - [c265]Jean Christoph Jung, Stefan Frehse, Robert Wille, Rolf Drechsler:
Enhancing debugging of multiple missing control errors in reversible logic. ACM Great Lakes Symposium on VLSI 2010: 465-470 - [c264]Hoang Minh Le, Daniel Große, Rolf Drechsler:
Towards analyzing functional coverage in SystemC TLM property checking. HLDVT 2010: 67-74 - [c263]Finn Haedicke, Bijan Alizadeh, Görschwin Fey, Masahiro Fujita, Rolf Drechsler:
Polynomial datapath optimization using constraint solving and formal modelling. ICCAD 2010: 756-761 - [c262]Mathias Soeken, Robert Wille, Rolf Drechsler:
Hierarchical synthesis of reversible circuits using positive and negative Davio decomposition. IDT 2010: 143-148 - [c261]Hongyan Zhang, Robert Wille, Rolf Drechsler:
SAT-based ATPG for reversible circuits. IDT 2010: 149-154 - [c260]André Sülflow, Görschwin Fey, Rolf Drechsler:
Using QBF to increase accuracy of SAT-based debugging. ISCAS 2010: 641-644 - [c259]Stephan Eggersglüß, Daniel Tille, Rolf Drechsler:
Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation. ISCAS 2010: 649-652 - [c258]Alexander Finder, Rolf Drechsler:
An Evolutionary Algorithm for Optimization of Pseudo Kronecker Expressions. ISMVL 2010: 150-155 - [c257]Stefan Frehse, Robert Wille, Rolf Drechsler:
Efficient Simulation-Based Debugging of Reversible Logic. ISMVL 2010: 156-161 - [c256]D. Michael Miller, Robert Wille, Rolf Drechsler:
Reducing Reversible Circuit Cost by Adding Lines. ISMVL 2010: 217-222 - [c255]Robert Wille, Sebastian Offermann, Rolf Drechsler:
SyReC: A Programming Language for Synthesis of Reversible Circuits. MBMV 2010: 21-30 - [c254]Mathias Soeken, Robert Wille, Mirco Kuhlmann, Martin Gogolla, Rolf Drechsler:
Verifying UML/OCL Models Using Boolean Satisfiability. MBMV 2010: 57-66 - [c253]Daniel Große, Hoang Minh Le, Rolf Drechsler:
Proving transaction and system-level properties of untimed SystemC TLM designs. MEMOCODE 2010: 113-122 - [c252]Görschwin Fey, André Sülflow, Rolf Drechsler:
Towards Unifying Localization and Explanation for Automated Debugging. MTV 2010: 3-8 - [c251]Hoang Minh Le, Daniel Große, Rolf Drechsler:
Automatic Fault Localization for SystemC TLM Designs. MTV 2010: 35-40
2000 – 2009
- 2009
- [b8]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille:
Test Pattern Generation using Boolean Proof Engines. Springer 2009, ISBN 978-90-481-2359-9, pp. I-XII, 1-192 - [j59]Rüdiger Ebendt, Rolf Drechsler:
Weighted A* search - unifying view and application. Artif. Intell. 173(14): 1310-1342 (2009) - [j58]Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke:
Advanced verification by automatic property generation. IET Comput. Digit. Tech. 3(4): 338-353 (2009) - [j57]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Jürgen Schlöffel, Daniel Tille:
Effiziente Erfüllbarkeitsalgorithmen für die Generierung von Testmustern (Efficient Satisfiability Solving Algorithms for Test Pattern Generation). it Inf. Technol. 51(2): 102-111 (2009) - [j56]Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler:
Exact Synthesis of Elementary Quantum Gate Circuits. J. Multiple Valued Log. Soft Comput. 15(4): 283-300 (2009) - [j55]Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler:
Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 703-715 (2009) - [c250]Stephan Eggersglüß, Daniel Tille, Rolf Drechsler:
Speeding up SAT-Based ATPG Using Dynamic Clause Activation. Asian Test Symposium 2009: 177-182 - [c249]Görschwin Fey, André Sülflow, Rolf Drechsler:
Computing bounds for fault tolerance using formal techniques. DAC 2009: 190-195 - [c248]Robert Wille, Rolf Drechsler:
BDD-based synthesis of reversible logic for large functions. DAC 2009: 270-275 - [c247]Christian Genz, Rolf Drechsler:
Overcoming limitations of the SystemC data introspection. DATE 2009: 590-593 - [c246]Ulrich Kühne, Daniel Große, Rolf Drechsler:
Property analysis and design understanding. DATE 2009: 1246-1249 - [c245]Robert Wille, Daniel Große, Stefan Frehse, Gerhard W. Dueck, Rolf Drechsler:
Debugging of Toffoli networks. DATE 2009: 1284-1289 - [c244]André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler:
Increasing the accuracy of SAT-based debugging. DATE 2009: 1326-1331 - [c243]Daniel Tille, Rolf Drechsler:
A fast untestability proof for SAT-based ATPG. DDECS 2009: 38-43 - [c242]Stefan Frehse, Görschwin Fey, André Sülflow, Rolf Drechsler:
Robustness Check for Multiple Faults Using Formal Techniques. DSD 2009: 85-90 - [c241]Stephan Eggersglüß, Rolf Drechsler:
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques. ETS 2009: 81-86 - [c240]Robert Wille, Daniel Große, Finn Haedicke, Rolf Drechsler:
SMT-based stimuli generation in the SystemC Verification library. FDL 2009: 1-6 - [c239]Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler:
Contradictory antecedent debugging in bounded model checking. ACM Great Lakes Symposium on VLSI 2009: 173-176 - [c238]Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler:
Timing Arc based logic analysis for false noise reduction. ICCAD 2009: 225-230 - [c237]Rüdiger Ebendt, Rolf Drechsler:
Approximate BDD Minimization by Weighted A. ISCAS 2009: 2974-2977 - [c236]André Sülflow, Robert Wille, Görschwin Fey, Rolf Drechsler:
Evaluation of Cardinality Constraints on SMT-Based Debugging. ISMVL 2009: 298-303 - [c235]Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler:
Equivalence Checking of Reversible Circuits. ISMVL 2009: 324-330 - [c234]Marc Messing, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler:
Using a two-dimensional fault list for compact Automatic Test Pattern Generation. LATW 2009: 1-6 - [c233]André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler:
Increasing the Accuracy of SAT-based Debugging. MBMV 2009: 47-56 - [c232]Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler:
Equivalence Checking of Reversible Circuits. MBMV 2009: 67-76 - [c231]Daniel Große, Hoang Minh Le, Rolf Drechsler:
Induction-Based Formal Verification of SystemC TLM Designs. MTV 2009: 101-106 - [c230]André Sülflow, Ulrich Kühne, Görschwin Fey, Daniel Große, Rolf Drechsler:
WoLFram- A Word Level Framework for Formal Verification. IEEE International Workshop on Rapid System Prototyping 2009: 11-17 - [c229]Frank Rogin, Rolf Drechsler, Steffen Rülke:
Automatic debugging of System-on-a-Chip designs. SoCC 2009: 333-336 - [c228]Robert Wille, Daniel Große, Gerhard W. Dueck, Rolf Drechsler:
Reversible Logic Synthesis with Output Permutation. VLSI Design 2009: 189-194 - [c227]Robert Wille, Rolf Drechsler:
Effect of BDD Optimization on Synthesis of Reversible and Quantum Logic. RC@ETAPS 2009: 57-70 - [p1]Rolf Drechsler, Tommi A. Junttila, Ilkka Niemelä:
Non-Clausal SAT and ATPG. Handbook of Satisfiability 2009: 655-693 - [e8]Bernd Becker, V. Bertacoo, Rolf Drechsler, Masahiro Fujita:
Algorithms and Applications for Next Generation SAT Solvers, 08.11. - 13.11.2009. Dagstuhl Seminar Proceedings 09461, Schloss Dagstuhl - Leibniz-Zentrum für Informatik, Germany 2009 [contents] - [i4]Bernd Becker, Valeria Bertacco, Rolf Drechsler, Masahiro Fujita:
09461 Abstracts Collection - Algorithms and Applications for Next Generation SAT Solvers. Algorithms and Applications for Next Generation SAT Solvers 2009 - [i3]Daniel Große, Hoang Minh Le, Rolf Drechsler:
Formal Verification of Abstract SystemC Models. Algorithms and Applications for Next Generation SAT Solvers 2009 - [i2]Robert Wille, Jean Christoph Jung, André Sülflow, Rolf Drechsler:
SWORD - Module-based SAT Solving. Algorithms and Applications for Next Generation SAT Solvers 2009 - 2008
- [b7]Görschwin Fey, Rolf Drechsler:
Robustness and usability in modern design flows. Springer 2008, ISBN 978-1-4020-6535-4, pp. I-XIII, 1-166 - [j54]Sean Safarpour, Andreas G. Veneris, Rolf Drechsler:
Improved SAT-based Reachability Analysis with Observability Don't Cares. J. Satisf. Boolean Model. Comput. 5(1-4): 1-25 (2008) - [j53]Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler:
On the construction of small fully testable circuits with low depth. Microprocess. Microsystems 32(5-6): 263-269 (2008) - [j52]Sebastian Kinder, Rolf Drechsler:
Modeling and proving functional completeness in formal verification of counting heads. Int. J. Softw. Tools Technol. Transf. 10(6): 521-534 (2008) - [j51]Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler:
Automatic Fault Localization for Property Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(6): 1138-1149 (2008) - [j50]Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa:
Logic Minimization and Testability of 2-SPP Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1190-1202 (2008) - [j49]Daniel Große, Ulrich Kühne, Rolf Drechsler:
Analyzing Functional Coverage in Bounded Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1305-1314 (2008) - [j48]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille:
On Acceleration of SAT-Based ATPG for Industrial Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1329-1333 (2008) - [c226]Sujan Pandey, Rolf Drechsler:
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival. ASP-DAC 2008: 601-606 - [c225]Sujan Pandey, Rolf Drechsler:
Slack Allocation Based Co-Synthesis and Optimization of Bus and Memory Architectures for MPSoCs. DATE 2008: 206-211 - [c224]Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke:
Automatic Generation of Complex Properties for Hardware Designs. DATE 2008: 545-548 - [c223]Daniel Tille, Rolf Drechsler:
Incremental SAT Instance Generation for SAT-based ATPG. DDECS 2008: 68-73 - [c222]Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler:
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD 2008: 542-549 - [c221]Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler:
Contradiction Analysis for Constraint-based Random Simulation. FDL 2008: 130-135 - [c220]Daniel Große, Robert Wille, Robert Siegmund, Rolf Drechsler:
Debugging Contradictory Constraints in Constraint-Based Random Simulation. FDL (Selected Papers) 2008: 273-290 - [c219]André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler:
Using unsatisfiable cores to debug multiple design errors. ACM Great Lakes Symposium on VLSI 2008: 77-82 - [c218]Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner:
Process variations aware robust on-chip bus architecture synthesis for MPSoCs. ISCAS 2008: 2989-2992 - [c217]Doina Logofatu, Rolf Drechsler:
Comparative Study by Solving the Test Compaction Problem. ISMVL 2008: 44-49 - [c216]Stephan Eggersglüß, Rolf Drechsler:
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults. ISMVL 2008: 94-99 - [c215]Daniel Große, Robert Wille, Gerhard W. Dueck, Rolf Drechsler:
Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares. ISMVL 2008: 214-219 - [c214]Robert Wille, Daniel Große, Lisa Teuber, Gerhard W. Dueck, Rolf Drechsler:
RevLib: An Online Resource for Reversible Functions and Reversible Circuits. ISMVL 2008: 220-225 - [c213]Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler:
Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. ISQED 2008: 508-513 - [c212]Görschwin Fey, Rolf Drechsler:
A Basis for Formal Robustness Checking. ISQED 2008: 784-789 - [c211]Robert Wille, Daniel Große, Mathias Soeken, Rolf Drechsler:
Using Higher Levels of Abstraction for Solving Optimization Problems by Boolean Satisfiability. ISVLSI 2008: 411-416 - [c210]André Sülflow, Görschwin Fey, Roderick Bloem, Rolf Drechsler:
Debugging Design Errors by Using Unsatisfiable Cores. MBMV 2008: 159-168 - [c209]Daniel Große, Robert Wille, Ulrich Kühne, Rolf Drechsler:
Using Contradiction Analysis for Antecedent Debugging in Bounded Model Checking. MBMV 2008: 169-178 - [c208]Ulrich Kühne, Daniel Große, Rolf Drechsler:
Property Analysis and Design Understanding in a Quality-Driven Bounded Model Checking Flow. MTV 2008: 88-93 - [e7]Mario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Anikó Ekárt, Anna Esparcia-Alcázar, Muddassar Farooq, Andreas Fink, Jon McCormack, Michael O'Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Sima Uyar, Shengxiang Yang:
Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings. Lecture Notes in Computer Science 4974, Springer 2008, ISBN 978-3-540-78760-0 [contents] - [i1]Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Daniel Tille:
SAT-based Automatic Test Pattern Generation. Evolutionary Test Generation 2008 - 2007
- [j47]Beate Muranko, Rolf Drechsler:
Technische Dokumentation von Soft- und Hardware in Eingebetteten Systemen (Technical Documentation of Soft- and Hardware in Embedded Systems). it Inf. Technol. 49(2): 110- (2007) - [c207]Stephan Eggersglüß, Rolf Drechsler:
Improving Test Pattern Compactness in SAT-based ATPG. ATS 2007: 445-452 - [c206]Daniel Große, Ulrich Kühne, Rolf Drechsler:
Estimating functional coverage in bounded model checking. DATE 2007: 1176-1181 - [c205]Daniel Tille, Görschwin Fey, Rolf Drechsler:
Instance Generation for SAT-based ATPG. DDECS 2007: 153-156 - [c204]Sebastian Kinder, Rolf Drechsler:
Proving Completeness of Properties in Formal Verification of Counting Heads for Railways. DSD 2007: 396-403 - [c203]Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler:
On the Construction of Small Fully Testable Circuits with Low Depth. DSD 2007: 563-569 - [c202]André Sülflow, Nicole Drechsler, Rolf Drechsler:
Robust Multi-Objective Optimization in High Dimensional Spaces. EMO 2007: 715-726 - [c201]Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke:
An Integrated SystemC Debugging Environment. FDL 2007: 140-145 - [c200]Daniel Große, Hernan Peraza, Wolfgang Klingauf, Rolf Drechsler:
Measuring the Quality of a SystemC Testbench by using Code Coverage Techniques. FDL 2007: 146-151 - [c199]Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler:
Exact sat-based toffoli network synthesis. ACM Great Lakes Symposium on VLSI 2007: 96-101 - [c198]Daniel Große, Rüdiger Ebendt, Rolf Drechsler:
Improvements for constraint solving in the systemc verification library. ACM Great Lakes Symposium on VLSI 2007: 493-496 - [c197]Rolf Drechsler, Andreas Breiter:
Hardware Project Management - What we Can Learn from the Software Development Process for Hardware Design?. ICSOFT (SE) 2007: 409-416 - [c196]Christian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard:
Visualization of SystemC Designs. ISCAS 2007: 413-416 - [c195]Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler:
SAT-based ATPG for Path Delay Faults in Sequential Circuits. ISCAS 2007: 3671-3674 - [c194]Stephan Eggersglüß, Daniel Tille, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Experimental Studies on SAT-Based ATPG for Gate Delay Faults. ISMVL 2007: 6 - [c193]André Sülflow, Rolf Drechsler:
Modeling a Fully Scalable Reed-Solomon Encoder/Decoder over GF(p^{m}) in SystemC. ISMVL 2007: 42 - [c192]Mahsan Amoui, Daniel Große, Mitchell A. Thornton, Rolf Drechsler:
Evaluation of Toggle Coverage for MVL Circuits Specified in the SystemVerilog HDL. ISMVL 2007: 50 - [c191]Ulrich Kühne, Daniel Große, Rolf Drechsler:
Improving the Quality of Bounded Model Checking by Means of Coverage Estimation. ISVLSI 2007: 165-170 - [c190]Görschwin Fey, Daniel Große, Stephan Eggersglüß, Robert Wille, Rolf Drechsler:
Formal Verification on the Word Level using SAT-like Proof Techniques. MBMV 2007: 81-90 - [c189]André Sülflow, Görschwin Fey, Rolf Drechsler:
Verbesserte SAT basierte Fehlerdiagnose durch Widerspruchanalyse. MBMV 2007: 101-110 - [c188]Stephan Eggersglüß, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults. MEMOCODE 2007: 181-187 - [c187]Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler:
SWORD: A SAT like Prover Using Word Level Information. VLSI-SoC (Selected Papers) 2007: 1-17 - [c186]Robert Wille, Görschwin Fey, Daniel Große, Stephan Eggersglüß, Rolf Drechsler:
SWORD: A SAT like prover using word level information. VLSI-SoC 2007: 88-93 - [c185]Sujan Pandey, Christian Genz, Rolf Drechsler:
Co-synthesis of custom on-chip bus and memory for MPSoC architectures. VLSI-SoC 2007: 304-307 - [c184]Görschwin Fey, Tim Warode, Rolf Drechsler:
Reusing Learned Information in SAT-based ATPG. VLSI Design 2007: 69-76 - [c183]Sabine Glesner, Jens Knoop, Rolf Drechsler:
Preface. COCV@ETAPS 2007: 1-2 - [e6]Sabine Glesner, Jens Knoop, Rolf Drechsler:
Proceedings of the Workshop on Compiler Optimization meets Compiler Verification, COCV@ETAPS 2007, Braga, Portugal, March 25, 2007. Electronic Notes in Theoretical Computer Science 190(4), Elsevier 2007 [contents] - [e5]Mario Giacobini, Anthony Brabazon, Stefano Cagnoni, Gianni Di Caro, Rolf Drechsler, Muddassar Farooq, Andreas Fink, Evelyne Lutton, Penousal Machado, Stefan Minner, Michael O'Neill, Juan Romero, Franz Rothlauf, Giovanni Squillero, Hideyuki Takagi, Sima Uyar, Shengxiang Yang:
Applications of Evolutinary Computing, EvoWorkshops 2007: EvoCoMnet, EvoFIN, EvoIASP,EvoINTERACTION, EvoMUSART, EvoSTOC and EvoTransLog, Valencia, Spain, April11-13, 2007, Proceedings. Lecture Notes in Computer Science 4448, Springer 2007, ISBN 978-3-540-71804-8 [contents] - 2006
- [j46]Görschwin Fey, Rolf Drechsler:
Minimizing the number of paths in BDDs: Theory and algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 4-11 (2006) - [j45]Rüdiger Ebendt, Rolf Drechsler:
Effect of improved lower bounds in dynamic BDD reordering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 902-909 (2006) - [j44]Valentina Ciriani, Anna Bernasconi, Rolf Drechsler:
Testability of SPP Three-Level Logic Networks in Static Fault Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2241-2248 (2006) - [c182]Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler:
On the relation between simulation-based and SAT-based diagnosis. DATE 2006: 1139-1144 - [c181]Görschwin Fey, Daniel Große, Rolf Drechsler:
Avoiding false negatives in formal verification for protocol-driven blocks. DATE 2006: 1225-1226 - [c180]Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa:
Efficient minimization of fully testable 2-SPP networks. DATE 2006: 1300-1305 - [c179]Doina Logofatu, Rolf Drechsler:
Efficient Evolutionary Approaches for the Data Ordering Problem with Inversion. EvoWorkshops 2006: 320-331 - [c178]Daniel Große, Ulrich Kühne, Rolf Drechsler:
HW/SW co-verification of embedded systems using bounded model checking. ACM Great Lakes Symposium on VLSI 2006: 43-48 - [c177]Stefan Staber, Görschwin Fey, Roderick Bloem, Rolf Drechsler:
Automatic Fault Localization for Property Checking. Haifa Verification Conference 2006: 50-64 - [c176]Rüdiger Ebendt, Rolf Drechsler:
On the sensitivity of BDDs with respect to path-related objective functions. ISCAS 2006 - [c175]Sean Safarpour, Andreas G. Veneris, Rolf Drechsler:
Integrating observability don't cares in all-solution SAT solvers. ISCAS 2006 - [c174]Görschwin Fey, Junhao Shi, Rolf Drechsler:
Efficiency of Multi-Valued Encoding in SAT-based ATPG. ISMVL 2006: 25 - [c173]Christian Genz, Rolf Drechsler:
System Exploration of SystemC Designs. ISVLSI 2006: 335-342 - [c172]Rüdiger Ebendt, Rolf Drechsler:
A Framework for Quasi-exact Optimization Using Relaxed Best-First Search. KI 2006: 331-345 - [c171]Görschwin Fey, Rolf Drechsler:
SAT-based Calculation of Source Code Coverage for BMC. MBMV 2006: 163-170 - [c170]Beate Muranko, Rolf Drechsler:
Technische Dokumentation von Soft- und Hardware-Systemen: Die vergessene Welt. MBMV 2006: 227-231 - [c169]Rolf Drechsler, Görschwin Fey:
Automatic Test Pattern Generation. SFM 2006: 30-55 - [c168]Beate Muranko, Rolf Drechsler:
Technical Documentation of Software and Hardware in Embedded Systems. VLSI-SoC 2006: 261-266 - [c167]Rolf Drechsler, Görschwin Fey, Sebastian Kinder:
An Integrated Approach for Combining BDD and SAT Provers. VLSI Design 2006: 237-242 - [e4]Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, Ernesto Costa, Carlos Cotta, Rolf Drechsler, Evelyne Lutton, Penousal Machado, Jason H. Moore, Juan Romero, George D. Smith, Giovanni Squillero, Hideyuki Takagi:
Applications of Evolutionary Computing, EvoWorkshops 2006: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoINTERACTION, EvoMUSART, and EvoSTOC, Budapest, Hungary, April 10-12, 2006, Proceedings. Lecture Notes in Computer Science 3907, Springer 2006, ISBN 3-540-33237-5 [contents] - 2005
- [b6]Bernd Becker, Rolf Drechsler, Paul Molitor:
Technische Informatik - eine Einführung. Pearson Studium, Pearson Education 2005, ISBN 978-3-8273-7092-1, pp. 1-390 - [b5]Rüdiger Ebendt, Görschwin Fey, Rolf Drechsler:
Advanced BDD optimization. Springer 2005, ISBN 978-0-387-25453-1, pp. I-X, 1-222 - [j43]Rolf Drechsler, Dragan Jankovic, Radomir S. Stankovic:
Generic Implementation of Multi-Valued Logic Decision Diagram Packages. J. Multiple Valued Log. Soft Comput. 11(1-2): 1-18 (2005) - [j42]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
Combining ordered best-first search with branch and bound for exact BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10): 1515-1529 (2005) - [c166]Junhao Shi, Görschwin Fey, Rolf Drechsler:
Bridging fault testability of BDD circuits. ASP-DAC 2005: 188-191 - [c165]Rüdiger Ebendt, Rolf Drechsler:
Lower bounds for dynamic BDD reordering. ASP-DAC 2005: 579-582 - [c164]Daniel Große, Rolf Drechsler:
Acceleration of SAT-Based Iterative Property Checking. CHARME 2005: 349-353 - [c163]Daniel Große, Ulrich Kühne, Rolf Drechsler:
Formale Verifikation des Befehlssatzes eines SystemC Mikroprozessors. GI Jahrestagung (1) 2005: 308-312 - [c162]Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler:
Utilizing don't care states in SAT-based bounded sequential problems. ACM Great Lakes Symposium on VLSI 2005: 264-269 - [c161]Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler:
Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876 - [c160]Daniel Große, Rolf Drechsler:
CheckSyC: an efficient property checker for RTL SystemC designs. ISCAS (4) 2005: 4167-4170 - [c159]Sebastian Kinder, Görschwin Fey, Rolf Drechsler:
Controlling the Memory During Manipulation of Word-Level Decision Diagrams. ISMVL 2005: 250-255 - [c158]Rüdiger Ebendt, Rolf Drechsler:
Quasi-Exact BDD Minimization Using Relaxed Best-First Search. ISVLSI 2005: 59-64 - [c157]Junhao Shi, Görschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel:
PASSAT: Efficient SAT-Based Test Pattern Generation for Industrial Circuits. ISVLSI 2005: 212-217 - [c156]Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler:
Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47 - [c155]Daniel Große, Ulrich Kühne, Rolf Drechsler:
HW/SW Co-Verification of a RISC CPU using Bounded Model Checking. MTV 2005: 133-137 - [c154]Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große:
SyCE: An Integrated Environment for System Design in SystemC. IEEE International Workshop on Rapid System Prototyping 2005: 258-260 - [c153]Rüdiger Ebendt, Rolf Drechsler:
Exact BDD Minimization for Path-Related Objective Functions. VLSI-SoC 2005: 299-315 - [e3]Franz Rothlauf, Jürgen Branke, Stefano Cagnoni, David W. Corne, Rolf Drechsler, Yaochu Jin, Penousal Machado, Elena Marchiori, Juan Romero, George D. Smith, Giovanni Squillero:
Applications of Evolutionary Computing, EvoWorkshops 2005: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Lausanne, Switzerland, March 30 - April 1, 2005, Proceedings. Lecture Notes in Computer Science 3449, Springer 2005, ISBN 3-540-25396-3 [contents] - 2004
- [j41]Dragan Jankovic, Rolf Drechsler:
Method for Construction of Recursive Algorithms for Reed- Muller-Fourier Polarity Matrices Calculation. J. Multiple Valued Log. Soft Comput. 10(1): 29-50 (2004) - [j40]Rolf Drechsler, Junhao Shi, Görschwin Fey:
Synthesis of fully testable circuits from BDDs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(3): 440-443 (2004) - [c152]Görschwin Fey, Rolf Drechsler:
Improving simulation-based verification by means of formal methods. ASP-DAC 2004: 640-643 - [c151]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
Minimization of the expected path length in BDDs based on local changes. ASP-DAC 2004: 865-870 - [c150]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
Combining ordered best-first search with branch and bound for exact BDD minimization. ASP-DAC 2004: 875-878 - [c149]Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee:
Managing Don't Cares in Boolean Satisfiability. DATE 2004: 260-265 - [c148]Görschwin Fey, Junhao Shi, Rolf Drechsler:
BDD Circuit Optimization for Path Delay Fault Testability. DSD 2004: 168-172 - [c147]Nicole Drechsler, Mario Hilgemeier, Görschwin Fey, Rolf Drechsler:
Disjoint Sum of Product Minimization by Evolutionary Algorithms. EvoWorkshops 2004: 198-207 - [c146]Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir:
Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209 - [c145]Thomas Eschbach, Rolf Drechsler, Bernd Becker:
Placement and routing optimization for circuits derived from BDDs. ISCAS (5) 2004: 229-232 - [c144]Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler:
Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Propertie. ISMVL 2004: 223-228 - [c143]Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski:
Algorithms for Taylor Expansion Diagrams. ISMVL 2004: 235-240 - [c142]Rolf Drechsler:
Using Synthesis Techniques in SAT Solvers. MBMV 2004: 165-173 - [c141]Rüdiger Ebendt, Rolf Drechsler:
A Tight Lower Bound for Dynamic BDD Reordering. MBMV 2004: 233-242 - [c140]Rolf Drechsler, Wolfgang Günther, Burkhard Stubert:
Efficient (Non-)Reachability Analysis of Counterexamples. MBMV 2004: 250-259 - [c139]Daniel Große, Rolf Drechsler:
Checkers for SystemC designs. MEMOCODE 2004: 171-178 - [c138]Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Rolf Drechsler, Alexander Smith:
Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49 - [c137]Rolf Drechsler:
Towards Formal Verification on the System Level. IEEE International Workshop on Rapid System Prototyping 2004: 2-5 - [e2]Günther R. Raidl, Stefano Cagnoni, Jürgen Branke, David Corne, Rolf Drechsler, Yaochu Jin, Colin G. Johnson, Penousal Machado, Elena Marchiori, Franz Rothlauf, George D. Smith, Giovanni Squillero:
Applications of Evolutionary Computing, EvoWorkshops 2004: EvoBIO, EvoCOMNET, EvoHOT, EvoIASP, EvoMUSART, and EvoSTOC, Coimbra, Portugal, April 5-7, 2004, Proceedings. Lecture Notes in Computer Science 3005, Springer 2004, ISBN 3-540-21378-3 [contents] - 2003
- [j39]Martin Keim, Rolf Drechsler, Bernd Becker, Michael Martin, Paul Molitor:
Polynomial Formal Verification of Multipliers. Formal Methods Syst. Des. 22(1): 39-58 (2003) - [j38]Daniel Große, Rolf Drechsler:
Ein Ansatz zur formalen Verifikation von Schaltungsbeschreibungen in SystemC. it Inf. Technol. 45(4): 219-226 (2003) - [j37]Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst:
Recursive bi-partitioning of netlists for large number of partitions. J. Syst. Archit. 49(12-15): 521-528 (2003) - [j36]Frank Schmiedle, Rolf Drechsler, Bernd Becker:
Exact Routing with Search Space Reduction. IEEE Trans. Computers 52(6): 815-825 (2003) - [j35]Wolfgang Günther, Rolf Drechsler:
Efficient Minimization and Manipulation of Linearly Transformed Binary Decision Diagrams. IEEE Trans. Computers 52(9): 1196-1209 (2003) - [j34]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
An improved branch and bound algorithm for exact BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12): 1657-1663 (2003) - [c136]Rolf Drechsler, Nicole Drechsler:
Minimization of Transitions by Complementation and Resequencing using Evolutionary Algorithms. Applied Informatics 2003: 109-114 - [c135]Junhao Shi, Görschwin Fey, Rolf Drechsler:
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability. Asian Test Symposium 2003: 290-293 - [c134]Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler:
Minimizing the number of one-paths in BDDs by an evolutionary algorithm. IEEE Congress on Evolutionary Computation 2003: 1724-1731 - [c133]Rüdiger Ebendt, Wolfgang Günther, Rolf Drechsler:
Combination of Lower Bounds in Exact BDD Minimization. DATE 2003: 10758-10763 - [c132]Mario Hilgemeier, Nicole Drechsler, Rolf Drechsler:
Fast Heuristics for the Edge Coloring of Large Graphs. DSD 2003: 230-239 - [c131]Rolf Drechsler, Nicole Drechsler:
GAME-HDL: Implementation of Evolutionary Algorithms Using Hardware Description Languages. EvoWorkshops 2003: 378-387 - [c130]Daniel Große, Rolf Drechsler, Lothar Linhard, Gerhard Angst:
Efficient Automatic Visualization of SystemC Designs. FDL 2003: 646-658 - [c129]Rolf Drechsler, Junhao Shi, Görschwin Fey:
MuTaTe: an efficient design for testability technique for multiplexor based circuits. ACM Great Lakes Symposium on VLSI 2003: 80-83 - [c128]Daniel Große, Rolf Drechsler:
BDD-based verification of scalable designs. HLDVT 2003: 123-128 - [c127]Daniel Große, Rolf Drechsler:
Formal verification of LTL formulas for SystemC designs. ISCAS (5) 2003: 245-248 - [c126]Rolf Drechsler:
Synthesizing checkers for on-line verification of System-on-Chip designs. ISCAS (4) 2003: 748-751 - [c125]Denis V. Popel, Rolf Drechsler:
Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions. ISMVL 2003: 241-246 - [c124]Daniel Große, Görschwin Fey, Rolf Drechsler:
Modeling Multi-Valued Circuits in SystemC. ISMVL 2003: 281-286 - [c123]Görschwin Fey, Sebastian Kinder, Rolf Drechsler:
Using Games for Benchmarking and Representing the Complete Solution Space using Symbolic Techniques. ISMVL 2003: 361-366 - [c122]D. Michael Miller, Rolf Drechsler:
Augmented Sifting of Multiple-Valued Decision Diagrams. ISMVL 2003: 375-382 - [c121]Daniel Große, Rolf Drechsler:
Formale Verifikation von LTL-Formeln für SystemC-Beschreibungen. MBMV 2003: 229-238 - [c120]Görschwin Fey, Rolf Drechsler:
Finding Good Counter-Examples to Aid Design Verification. MEMOCODE 2003: 51- - [c119]Nicole Drechsler, Rolf Drechsler:
Exploration of Sequential Depth by Evolutionary Algorithms. VLSI-SoC (Selected Papers) 2003: 73-83 - [c118]Nicole Drechsler, Rolf Drechsler:
Exploration of Sequential Depth by Evolutionary Algorithms. VLSI-SOC 2003: 81-85 - [c117]Valentina Ciriani, Anna Bernasconi, Rolf Drechsler:
Stuck-At-Fault Testability of SPP Three-Level Logic Forms. VLSI-SoC (Selected Papers) 2003: 299-313 - [c116]Valentina Ciriani, Anna Bernasconi, Rolf Drechsler:
Testability of SPP Three-Level Logic Networks. VLSI-SOC 2003: 331-336 - [e1]Rolf Drechsler:
Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), Bremen, Germany, February 24-25, 2003. Shaker 2003 [contents] - 2002
- [j33]Frank Schmiedle, Nicole Drechsler, Daniel Große, Rolf Drechsler:
Heuristic Learning Based on Genetic Programming. Genet. Program. Evolvable Mach. 3(4): 363-388 (2002) - [j32]Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler:
A Genetic Algorithm for the Minimization of OPKFDDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2943-2945 (2002) - [j31]Wolfgang Günther, Rolf Drechsler:
Minimization of free BDDs. Integr. 32(1-2): 41-59 (2002) - [j30]Rolf Drechsler:
Verifying integrity of decision diagrams. Integr. 32(1-2): 61-75 (2002) - [j29]Rolf Drechsler, Wolfgang Günther, Stefan Höreth:
Minimization of Word-Level Decision Diagrams. Integr. 33(1-2): 39-70 (2002) - [j28]Marek A. Perkowski, Bogdan J. Falkowski, Malgorzata Chrzanowska-Jeske, Rolf Drechsler:
Efficient Algorithms for Creation of Linearly-independent Decision Diagrams and their Mapping to Regular Layouts. VLSI Design 14(1): 35-52 (2002) - [j27]Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther:
Logic Circuit Equivalence Checking Using Haar Spectral Coefficients and Partial BDDs. VLSI Design 14(1): 53-64 (2002) - [c115]Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst:
Recursive Bi-Partitioning of Netlists for Large Number of Partitions. DSD 2002: 38-44 - [c114]Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler:
Decision Diagram Optimization Using Copy Properties. DSD 2002: 236-243 - [c113]Rolf Drechsler, Daniel Große:
Reachability Analysis for Formal Verification of SystemC. DSD 2002: 337-340 - [c112]Thomas Eschbach, Wolfgang Günther, Rolf Drechsler, Bernd Becker:
Crossing Reduction by Windows Optimization. GD 2002: 285-294 - [c111]Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller:
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. ACM Great Lakes Symposium on VLSI 2002: 178-183 - [c110]Mikael Kerttu, Per Lindgren, Mitchell A. Thornton, Rolf Drechsler:
Switching activity estimation of finite state machines for low power synthesis. ISCAS (4) 2002: 65-68 - [c109]D. Michael Miller, Rolf Drechsler:
On the Construction of Multiple-Valued Decision Diagrams. ISMVL 2002: 245-253 - [c108]Rolf Drechsler:
Evaluation of Static Variable Ordering Heuristics for MDD Construction. ISMVL 2002: 254-260 - [c107]Sherief Reda, Rolf Drechsler, Alex Orailoglu:
On the Relation between SAT and BDDs for Equivalence Checking. ISQED 2002: 394-399 - [c106]Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller:
Multi-Output Timed Shannon Circuits. ISVLSI 2002: 47-52 - [c105]Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton:
Low Power Optimization Techniques for BDD Mapped Finite State Machines. IWLS 2002: 143-148 - [c104]Klaus-Jürgen Englert, Bernd Becker, Rolf Drechsler:
Symbolic Simulation of Algorithms Specified in HDL. MBMV 2002: 113-122 - [c103]Rolf Drechsler, Jochen Römmler:
Implementation and Visualization of a BDD Package in JAVA. MBMV 2002: 219-228 - [c102]Görschwin Fey, Rolf Drechsler:
Minimizing the Number of Paths in BDDs. SBCCI 2002: 359-364 - [c101]Raik Brinkmann, Rolf Drechsler:
RTL-Datapath Verification using Integer Linear Programming. ASP-DAC/VLSI Design 2002: 741-746 - 2001
- [b4]Mitchell Aaron Thornton, Rolf Drechsler, D. Michael Miller:
Spectral techniques in VLSI CAD. Kluwer 2001, ISBN 978-0-7923-7433-6, pp. I-XIII, 1-250 - [j26]Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker:
Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. J. Electron. Test. 17(1): 37-51 (2001) - [j25]Rolf Drechsler, Wolfgang Günther:
History-based dynamic BDD minimization. Integr. 31(1): 51-63 (2001) - [j24]Rolf Drechsler:
Äquivalenzvergleich digitaler Schaltungen im industriellen Umfeld (Equivalence Checking of Digital Circuits in an Industrial Environment). Informationstechnik Tech. Inform. 43(4): 200-205 (2001) - [j23]Rolf Drechsler, Detlef Sieling:
Binary decision diagrams in theory and practice. Int. J. Softw. Tools Technol. Transf. 3(2): 112-136 (2001) - [j22]Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler:
Decision Diagram Method for Calculation of Pruned Walsh Transform. IEEE Trans. Computers 50(2): 147-157 (2001) - [j21]Rolf Drechsler, Wolfgang Günther, Fabio Somenzi:
Using lower bounds during dynamic BDD minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 51-57 (2001) - [c100]Peer Johannsen, Rolf Drechsler:
Utilizing High-Level Information for Formal Hardware Verification. ACS 2001: 419-431 - [c99]Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler:
Tabular Techniques for MV Logic. ACS 2001: 433-448 - [c98]Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler:
Low power optimization technique for BDD mapped circuits. ASP-DAC 2001: 615-621 - [c97]Mitchell A. Thornton, Rolf Drechsler:
Spectral decision diagrams using graph transformations. DATE 2001: 713-719 - [c96]Bernd Becker, Thomas Eschbach, Rolf Drechsler, Wolfgang Günther:
Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement. DSD 2001: 54-61 - [c95]Migyoung Jung, Gueesang Lee, Sungju Park, Rolf Drechsler:
Minimization of OPKFDDs Using Genetic Algorithms. DSD 2001: 72-78 - [c94]Rolf Drechsler, Wolfgang Günther, Lothar Linhard, Gerhard Angst:
Level Assignment for Displaying Combinational Logic. DSD 2001: 148-151 - [c93]Nicole Drechsler, Rolf Drechsler, Bernd Becker:
Multi-objective Optimisation Based on Relation Favour. EMO 2001: 154-166 - [c92]Nicole Drechsler, Frank Schmiedle, Daniel Große, Rolf Drechsler:
Heuristic Learning Based on Genetic Programming. EuroGP 2001: 1-10 - [c91]Frank Schmiedle, Daniel Große, Rolf Drechsler, Bernd Becker:
Too Much Knowledge Hurts: Acceleration of Genetic Programs for Learning Heuristics. Fuzzy Days 2001: 479-491 - [c90]Peer Johannsen, Rolf Drechsler:
Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. VLSI-SOC 2001: 361-374 - [c89]Frank Schmiedle, Wolfgang Günther, Rolf Drechsler:
Selection of Efficient Re-Ordering Heuristics for MDD Construction. ISMVL 2001: 299-304 - [c88]Rolf Drechsler:
GateComp: Equivalence Checking in CVE. MBMV (1) 2001: 109-110 - [c87]Wolfgang Günther, Rolf Drechsler:
Implementation of Read- k-times BDDs on Top of Standard BDD Packages. VLSI Design 2001: 173-178 - [c86]Wolfgang Günther, Rolf Drechsler:
Performance Driven Optimization for MUX based FPGAs. VLSI Design 2001: 311-316 - 2000
- [j20]Rolf Drechsler, Bernd Becker, Nicole Drechsler:
OKFDD minimization by genetic algorithms with application to circuit design. Integr. 28(2): 121-139 (2000) - [j19]A. Zuzek, Rolf Drechsler, Mitchell A. Thornton:
Boolean function representation and spectral characterization using AND/OR graphs. Integr. 29(2): 101-116 (2000) - [j18]Wolfgang Günther, Rolf Drechsler:
On the computational power of linearly transformed BDDs. Inf. Process. Lett. 75(3): 119-125 (2000) - [j17]Wolfgang Günther, Rolf Drechsler:
ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs. J. Syst. Archit. 46(14): 1321-1334 (2000) - [j16]Rolf Drechsler, Nicole Drechsler, Wolfgang Günther:
Fast exact minimization of BDD's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3): 384-389 (2000) - [c85]Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker:
Verification of Designs Containing Black Boxes. EUROMICRO 2000: 1100-1105 - [c84]Wolfgang Günther, Rolf Drechsler:
ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs. EUROMICRO 2000: 1130-1137 - [c83]Rolf Drechsler, Wolfgang Günther, Bernd Becker:
Testability of Circuits Derived from Lattice Diagrams. EUROMICRO 2000: 1188-1192 - [c82]Rolf Drechsler, Nicole Drechsler, Elke Mackensen, Tobias Schubert, Bernd Becker:
Design Reuse by Modularity: A Scalable Dynamical (Re)Configurable Multiprocessor System. EUROMICRO 2000: 1425- - [c81]Wolfgang Günther, Rolf Drechsler:
Improving EAs for Sequencing Problems. GECCO 2000: 175-180 - [c80]Tobias Schubert, Elke Mackensen, Nicole Drechsler, Rolf Drechsler, Bernd Becker:
Specialized Hardware for Implementation of Evolutionary Algorithms. GECCO 2000: 369 - [c79]Rolf Drechsler, Wolfgang Günther:
Evolutionary Synthesis of Multiplexor Circuits under Hardware Constraints. GECCO 2000: 513-518 - [c78]Wolfgang Günther, Rolf Drechsler, Stefan Höreth:
Efficient Dynamic Minimization of Word-Level DDs Based on Lower Bound Computation. ICCD 2000: 383-388 - [c77]Per Lindgren, Rolf Drechsler, Bernd Becker:
Minimization of Ordered Pseudo Kronecker Decision Diagrams. ICCD 2000: 504-510 - [c76]Rolf Drechsler, Wolfgang Günther:
Optimization of sequential verification by history-based dynamic minimization of BDDs. ISCAS 2000: 737-740 - [c75]Rolf Drechsler, Mitchell A. Thornton, David Wessels:
MDD-Based Synthesis of Multi-Valued Logic Networks. ISMVL 2000: 41-46 - [c74]Rolf Drechsler, Mitchell A. Thornton:
Computation of Spectral Information from Logic Netlists. ISMVL 2000: 53-58 - [c73]Dragan Jankovic, Wolfgang Günther, Rolf Drechsler:
Lower Bound Sifting for MDDs. ISMVL 2000: 193-198 - [c72]Frank Schmiedle, Wolfgang Günther, Rolf Drechsler:
Dynamic Re-Encoding During MDD Minimization. ISMVL 2000: 239-244 - [c71]Mitchell A. Thornton, Rolf Drechsler, Wolfgang Günther:
A Method for Approximate Equivalence Checking. ISMVL 2000: 447-452 - [c70]Rolf Drechsler, Wolfgang Günther, Bernd Becker:
Testability of Circuits Derived from Lattice Diagrams. LATW 2000: 77-81 - [c69]Wolfgang Günther, Nicole Drechsler, Rolf Drechsler, Bernd Becker:
Verification of Designs Containing Black Boxes. MBMV 2000: 19-26
1990 – 1999
- 1999
- [j15]Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker:
Testability of 2-Level AND/EXOR Circuits. J. Electron. Test. 14(3): 219-225 (1999) - [j14]Rolf Drechsler:
Preudo-Kronecker Expressions for Symmetric Functions. IEEE Trans. Computers 48(9): 987-990 (1999) - [j13]Christoph Scholl, Dirk Möller, Paul Molitor, Rolf Drechsler:
BDD minimization using symmetries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(2): 81-100 (1999) - [j12]Rolf Drechsler:
Evolutionary Algorithms for VLSI CAD [book Review]. IEEE Trans. Evol. Comput. 3(3): 251-253 (1999) - [c68]Yibin Ye, Kaushik Roy, Rolf Drechsler:
Power Consumption in XOR-Based Circuits. ASP-DAC 1999: 299-302 - [c67]Rolf Drechsler, Nicole Drechsler:
Exploiting Don't Caers During Data Sequencing using Genetic Algorithms. ASP-DAC 1999: 303- - [c66]Wolfgang Günther, Rolf Drechsler:
Minimization of Free BDDs. ASP-DAC 1999: 323-326 - [c65]Rolf Drechsler, Wolfgang Günther:
Using Lower Bounds During Dynamic BDD Minimization. DAC 1999: 29-32 - [c64]Stefan Höreth, Rolf Drechsler:
Formal Verification of Word-Level Specifications. DATE 1999: 52-57 - [c63]Mitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler:
Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities. DATE 1999: 758-759 - [c62]Rolf Drechsler, Wolfgang Günther:
Generation of Optimal Universal Logic Modules. EUROMICRO 1999: 1080-1085 - [c61]Rolf Drechsler, Dragan Jankovic, Radomir S. Stankovic:
Generic Implementation of DD Packages in MVL. EUROMICRO 1999: 1352-1359 - [c60]Rolf Drechsler:
Checking Integrity During Dynamic Reordering in Decision Diagrams. EUROMICRO 1999: 1360-1367 - [c59]Nicole Drechsler, Wolfgang Günther, Rolf Drechsler:
Efficient Graph Coloring by Evolutionary Algorithms. Fuzzy Days 1999: 30-39 - [c58]Nicole Drechsler, Rolf Drechsler, Bernd Becker:
Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes. Fuzzy Days 1999: 108-117 - [c57]Wolfgang Günther, Rolf Drechsler:
Efficient manipulation algorithms for linearly transformed BDDs. ICCAD 1999: 50-54 - [c56]Per Lindgren, Rolf Drechsler, Bernd Becker:
Synthesis of Pseudo Kronecker Lattice Diagrams. ICCD 1999: 307-310 - [c55]Rolf Drechsler, Wolfgang Günther:
History-Based Dynamic Minimization During BDD Construction. VLSI 1999: 334-345 - [c54]Wolfgang Günther, Rolf Drechsler:
Minimization of BDDs using linear transformations based on evolutionary techniques. ISCAS (1) 1999: 387-390 - [c53]Frank Schmiedle, Rolf Drechsler, Bernd Becker:
Exact channel routing using symbolic representation. ISCAS (6) 1999: 394-397 - [c52]Rolf Drechsler, Marc Herbstritt, Bernd Becker:
Grouping heuristics for word-level decision diagrams. ISCAS (1) 1999: 411-414 - [c51]Franc Brglez, Rolf Drechsler:
Design of experiments in CAD: context and new data sets for ISCAS'99. ISCAS (6) 1999: 424-427 - [c50]Wolfgang Günther, Rolf Drechsler:
Creating hard problem instances in logic synthesis using exact minimization. ISCAS (6) 1999: 436-439 - [c49]Rolf Drechsler, Marc Herbstritt, Bernd Becker:
Grouping Heuristics for Word-Level Decision Diagrams. MBMV 1999: 41-50 - 1998
- [b3]Rolf Drechsler, Bernd Becker:
Graphenbasierte Funktionsdarstellung - Boolesche und Pseudo-Boolesche Funktionen. Leitfäden der Informatik, Teubner 1998, ISBN 978-3-519-02149-0, pp. 1-200 - [b2]Rolf Drechsler, Bernd Becker:
Binary Decision Diagrams - Theory and Implementation. Springer 1998, ISBN 978-0-7923-8193-8, pp. I-X, 1-200 - [j11]Rolf Drechsler, Bernd Becker, Andrea Jahnke:
On Variable Ordering and Decomposition Type Choice in OKFDDs. IEEE Trans. Computers 47(12): 1398-1403 (1998) - [j10]Rolf Drechsler, Martin Sauerhoff, Detlef Sieling:
The complexity of the inclusion operation on OFDD's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5): 457-459 (1998) - [j9]Rolf Drechsler, Bernd Becker:
Ordered Kronecker functional decision diagrams-a data structure for representation and manipulation of Boolean functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 965-973 (1998) - [c48]Gueesang Lee, Rolf Drechsler:
ETDD-Based Synthesis of Term-Based FPGAs for Incompletely Specified Boolean Functions. ASP-DAC 1998: 75-80 - [c47]Rolf Drechsler, Stefan Höreth:
Manipulation of *BMDs. ASP-DAC 1998: 433-438 - [c46]Rolf Drechsler, Nicole Drechsler, Wolfgang Günther:
Fast Exact Minimization of BDDs. DAC 1998: 200-205 - [c45]Stefan Höreth, Rolf Drechsler:
Dynamic Minimization of Word-Level Decision Diagrams. DATE 1998: 612-617 - [c44]Wolfgang Günther, Rolf Drechsler:
Linear Transformations and Exact Minimization of BDDs. Great Lakes Symposium on VLSI 1998: 325-330 - [c43]D. Michael Miller, Rolf Drechsler:
Implementing a Multiple-Valued Decision Diagram Package. ISMVL 1998: 52-57 - [c42]Per Lindgren, Rolf Drechsler, Bernd Becker:
Look-up Table FPGA Synthesis from Minimized Multi-Valued Pseudo Kronecker Expressions. ISMVL 1998: 95-101 - [c41]Martin Keim, Nicole Drechsler, Rolf Drechsler, Bernd Becker:
Test Generation for (Sequential) Multi-Valued Logic Networks based on Genetic Algorithm. ISMVL 1998: 215-221 - [c40]Rolf Drechsler:
Verifying Integrity of Decision Diagrams. SAFECOMP 1998: 380-389 - 1997
- [j8]Rolf Drechsler, Bernd Becker, Stefan Ruppertz:
The K*BMD: A Verification Data Structure. IEEE Des. Test Comput. 14(2): 51-59 (1997) - [j7]Bernd Becker, Rolf Drechsler, Michael Theobald:
On the Expressive Power of OKFDDs. Formal Methods Syst. Des. 11(1): 5-21 (1997) - [j6]Rolf Drechsler, Bernd Becker:
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 1-5 (1997) - [c39]Bernd Becker, Rolf Drechsler, Reinhard Enders:
On the representational power of bit-level and word-level decision diagrams. ASP-DAC 1997: 461-467 - [c38]Nicole Göckel, Rolf Drechsler, Bernd Becker:
Learning heuristics for OKFDD minimization by evolutionary algorithms. ASP-DAC 1997: 469-472 - [c37]Andreas Hett, Rolf Drechsler, Bernd Becker:
Fast and efficient construction of BDDs by reordering based synthesis. ED&TC 1997: 168-175 - [c36]Rolf Drechsler, Harry Hengster, Horst Schäfer, Joachim Hartmann, Bernd Becker:
Testability of 2-level AND/EXOR circuits. ED&TC 1997: 548-553 - [c35]Christoph Scholl, Rolf Drechsler, Bernd Becker:
Functional simulation using binary decision diagrams. ICCAD 1997: 8-12 - [c34]Craig M. Files, Rolf Drechsler, Marek A. Perkowski:
Functional Decomposition of MVL Functions Using Multi-Valued Decision Diagrams. ISMVL 1997: 27-34 - [c33]Rolf Drechsler, Martin Keim, Bernd Becker:
Sympathy-MV: Fast Exact Minimization of Fixed Polarity Multi-Valued Linear Expressions. ISMVL 1997: 66-74 - [c32]Rolf Drechsler, Martin Keim, Bernd Becker:
Fault Simulation in Sequential Multi-Valued Logic Networks. ISMVL 1997: 145-152 - [c31]Radomir S. Stankovic, Rolf Drechsler:
Circuit Design from Kronecker Galois Field Decision Diagrams for Multiple-Valued Functions. ISMVL 1997: 275-280 - [c30]Rolf Drechsler, Bernd Becker, Stefan Ruppertz:
Manipulation Algorithms for K*BMDs. TACAS 1997: 4-18 - [c29]Bernd Becker, Rolf Drechsler:
Decision Diagrams in Synthesis - Algorithms, Applications and Extensions. VLSI Design 1997: 46-50 - [c28]Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy:
(Quasi-) Linear Path Delay Fault Tests for Adders. VLSI Design 1997: 101-105 - [c27]Rolf Drechsler:
Pseudo Kronecker Expressions for Symmetric Functions. VLSI Design 1997: 511-513 - [c26]Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor:
Polynomial Formal Verification of Multipliers. VTS 1997: 150-157 - 1996
- [b1]Rolf Drechsler:
Ordered Kronecker functional decision diagrams und ihre Anwendung. Goethe University Frankfurt am Main, Modell-Verlag 1996, ISBN 3-9805033-0-5, pp. 1-117 - [j5]Rolf Drechsler, Michael Theobald, Bernd Becker:
Fast OFFD-Based Minimization of Fixed Polarity Reed-Muller Expressions. IEEE Trans. Computers 45(11): 1294-1299 (1996) - [c25]Harry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer:
AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. Asian Test Symposium 1996: 148- - [c24]Rolf Drechsler, Bernd Becker, Stefan Ruppertz:
K*BMDs: A New Data Structure for Verification. ED&TC 1996: 2-8 - [c23]Bernd Becker, Rolf Drechsler, Rolf Krieger, Sudhakar M. Reddy:
A Fast Optimal Robust Path Delay Fault Testable Adder. ED&TC 1996: 491-499 - [c22]Andreas Hett, Bernd Becker, Rolf Drechsler:
MORE: an alternative implementation of BDD packages by multi-operand synthesis. EURO-DAC 1996: 164-169 - [c21]Rolf Drechsler:
Verification of Multi-Valued Logic Networks. ISMVL 1996: 10-15 - [c20]Rolf Drechsler, Nicole Göckel, Bernd Becker:
Learning Heuristics for OBDD Minimization by Evolutionary Algorithms. PPSN 1996: 730-739 - 1995
- [j4]Harry Hengster, Rolf Drechsler, Bernd Becker:
On local transformations and path delay fault testability. J. Electron. Test. 7(3): 173-191 (1995) - [j3]Bernd Becker, Rolf Drechsler, Ralph Werchner:
On the Relation between BDDs and FDDs. Inf. Comput. 123(2): 185-197 (1995) - [j2]Rolf Drechsler, Bernd Becker, Nicole Göckel, Andrea Jahnke:
A Genetic Algorithm for Decomposition Type Choice in OKFDDs. Int. J. Artif. Intell. Tools 4(4): 525- (1995) - [j1]Bernd Becker, Rolf Drechsler, Paul Molitor:
On the generation of area-time optimal testable adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1049-1066 (1995) - [c19]Rolf Drechsler, Bernd Becker:
Learning heuristics by genetic algorithms. ASP-DAC 1995 - [c18]Rolf Drechsler, Bernd Becker:
Sympathy: fast exact minimization of fixed polarity Reed-Muller expressions for symmetric functions. ED&TC 1995: 91-99 - [c17]Bernd Becker, Rolf Drechsler:
How many decomposition types do we need? [decision diagrams]. ED&TC 1995: 438-443 - [c16]Bernd Becker, Rolf Drechsler:
Synthesis for testability: circuits derived from ordered Kronecker functional decision diagrams. ED&TC 1995: 592 - [c15]Bernd Becker, Rolf Drechsler, Michael Theobald:
OKFDDs versus OBDDs and OFDDs. ICALP 1995: 475-486 - [c14]Rolf Drechsler, Bernd Becker, Nicole Göckel:
A Genetic Algorithm for Minimization of Fixed Polarity Reed-Muller Expressions. ICANNGA 1995: 393-395 - [c13]Rolf Drechsler, Bernd Becker:
Dynamic minimization of OKFDDs. ICCD 1995: 602-607 - [c12]Rolf Drechsler, Rolf Krieger, Bernd Becker:
Random Pattern Fault Simulation in Multi-Valued Circuits. ISMVL 1995: 98-103 - [c11]Bernd Becker, Rolf Drechsler, Ralph Werchner:
On the Relation Betwen BDDs and FDDs. LATIN 1995: 72-83 - [c10]Harry Hengster, Rolf Drechsler, Bernd Becker:
On the application of local circuit transformations with special emphasis on path delay fault testability. VTS 1995: 387-392 - 1994
- [c9]Rolf Drechsler, Andisheh Sarabi, Michael Theobald, Bernd Becker, Marek A. Perkowski:
Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams. DAC 1994: 415-419 - [c8]Rolf Drechsler, Bernd Becker, Michael Theobald:
Fast OFDD based minimization of fixed polarity Reed-Muller expressions. EURO-DAC 1994: 2-7 - [c7]Rolf Drechsler:
BiTeS: a BDD based test pattern generator for strong robust path delay faults. EURO-DAC 1994: 322-327 - [c6]Bernd Becker, Rolf Drechsler:
Testability of Circuits Derived from Functional Decision Diagrams. EDAC-ETC-EUROASIC 1994: 667 - [c5]Bernd Becker, Rolf Drechsler:
OFDD Based Minimization of Fixed Polarity Reed-Muller Expressions Using Hybrid Genetic Algorithms. ICCD 1994: 106-110 - [c4]Bernd Becker, Rolf Drechsler:
Efficient Graph Based Representation of Multi-Valued Functions with an Application to Genetic Algorithms. ISMVL 1994: 65-72 - [c3]Harry Hengster, Rolf Drechsler, Bernd Becker:
Testability Properties of Local Circuit Transformations with Respect to the Robust Path-Delay-Fault Model. VLSI Design 1994: 123-126 - 1993
- [c2]Bernd Becker, Rolf Drechsler, Paul Molitor:
On the implementation of an efficient performance driven generator for conditional-sum-adders. EURO-DAC 1993: 402-407 - 1992
- [c1]Bernd Becker, Rolf Drechsler:
A time optimal robust path-delay-fault self-testable adder. EURO-DAC 1992: 376-381
Coauthor Index
[c667] [c377] [e8] [i4] [b6] [c145] [j39] [j36] [c112] [c104] [j26] [c96] [c93] [c91] [j20] [c85] [c83] [c82] [c80] [c77] [c70] [c69] [j15] [c58] [c56] [c53] [c52] [c49] [b3] [b2] [j11] [j9] [c42] [c41] [j8] [j7] [j6] [c39] [c38] [c37] [c36] [c35] [c33] [c32] [c30] [c29] [c28] [c26] [j5] [c25] [c24] [c23] [c22] [c20] [j4] [j3] [j2] [j1] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c6] [c5] [c4] [c3] [c2] [c1]
Bernhard J. Berger
aka: Bernhard Johannes Berger
aka: Bernhard Johannes Berger
Nicole Drechsler
aka: Nicole Göckel
aka: Nicole Göckel
[c635] [c527] [c500] [j103] [c374] [c363] [j78] [c315] [c311] [j67] [c293] [c288] [c282] [j64] [j61] [c274] [c273] [c270] [c269] [c263] [c260] [c252] [b8] [j58] [j57] [c249] [c244] [c242] [c236] [c233] [c230] [b7] [j53] [j51] [j48] [c224] [c222] [c219] [c212] [c210] [i1] [c205] [c203] [c195] [c194] [c190] [c189] [c188] [c187] [c186] [c184] [j46] [c182] [c181] [c177] [c174] [c171] [c169] [c167] [b5] [c166] [c162] [c159] [c157] [c154] [j40] [c152] [c148] [c147] [c143] [c135] [c129] [c124] [c123] [c120] [c102]
[j134] [c669] [c668] [c650] [c647] [j133] [j130] [c630] [c627] [c618] [c616] [c603] [c596] [j128] [j127] [c594] [c593] [c592] [c591] [c590] [c589] [c587] [c586] [c581] [c579] [c578] [c576] [c575] [c571] [c570] [j120] [j119] [j118] [j117] [c560] [c559] [c558] [c557] [c556] [c554] [c552] [c551] [c550] [c549] [c546] [c545] [c541] [c540] [c538] [c531] [p3] [i14] [j111] [c524] [c523] [c521] [c520] [c519] [c518] [c516] [c514] [c513] [c512] [c510] [c508] [c503] [c501] [c497] [c494] [j103] [c490] [c486] [c477] [c476] [c475] [c474] [c473] [c471] [c466] [c463] [c460] [e14] [c455] [c454] [c452] [c451] [c449] [c448] [c445] [c443] [c442] [c441] [c440] [c437] [c427] [c416] [c401] [c365] [j78] [c350] [c349] [c345] [c341] [j71] [j70] [c325] [c324] [c319] [c316] [c314] [c313] [c309] [c305] [c303] [j69] [c292] [c290] [c288] [c287] [c285] [c284] [c281] [c280] [b9] [j65] [c264] [c253] [c251] [j56] [j55] [c246] [c245] [c240] [c239] [c235] [c232] [c231] [c230] [c228] [i3] [j49] [c221] [c220] [c215] [c214] [c211] [c209] [c208] [c206] [c200] [c199] [c198] [c192] [c191] [c190] [c187] [c186] [c181] [c178] [c164] [c163] [c160] [c155] [c154] [c139] [j38] [c130] [c128] [c127] [c124] [c121] [j33] [c113] [c92] [c91]
[j149] [c711] [c698] [c691] [d3] [j146] [j145] [j140] [j137] [c673] [c671] [c669] [c667] [c666] [c663] [c659] [c653] [c652] [c651] [c647] [c646] [c637] [d2] [j133] [j130] [c630] [c622] [c619] [c615] [c609] [c607] [c600] [c596] [d1] [j128] [c594] [c593] [c592] [c589] [c587] [c581] [c579] [c576] [c570] [c567] [j118] [j117] [c558] [c554] [c551] [c545] [c540] [c521] [c518] [c512] [c497] [c486] [c477] [c476] [c471] [c454] [c448] [c445] [c441] [c416] [c415] [c350]
Hoang Minh Le 0001
aka: Hoang M. Le
aka: Hoang M. Le
Frank Sill
aka: Frank Sill Torres
aka: Frank Sill Torres
[j112] [j111] [j108] [j106] [j103] [c483] [c474] [j101] [j100] [j97] [j95] [j92] [c455] [c453] [c452] [c450] [c449] [c447] [c443] [c442] [c440] [c430] [c427] [b13] [c411] [c408] [c407] [c399] [c397] [c389] [c388] [j87] [j86] [c374] [c372] [c370] [c368] [c364] [c361] [c360] [c356] [c355] [c354] [i9] [i8] [i7] [j76] [c351] [c348] [c347] [c346] [c343] [c341] [c339] [c336] [c335] [c332] [c327] [i6] [j73] [c326] [c322] [c321] [c318] [c317] [c314] [c313] [c308] [c307] [c306] [c304] [c302] [c301] [c300] [c296] [c293] [c285] [c282] [c281] [c279] [c278] [c277] [c276] [c275] [c271] [c262] [c254] [c211]
Mitchell A. Thornton
aka: Mitchell Aaron Thornton
aka: Mitchell Aaron Thornton
[c721] [j142] [j131] [c628] [c598] [j129] [j127] [j126] [j124] [j123] [c595] [c591] [c588] [c583] [c573] [c572] [c569] [c565] [c564] [c562] [j119] [j115] [j114] [c559] [c553] [c548] [c534] [c531] [c525] [i14] [i13] [b14] [j113] [j110] [j107] [c523] [c522] [c514] [c511] [c509] [c506] [c504] [c496] [c495] [c491] [p2] [i12] [j105] [j104] [j102] [c489] [c488] [c472] [c469] [c467] [c465] [c464] [c461] [c459] [c458] [i11] [i10] [j101] [j100] [j99] [j98] [j97] [j96] [j94] [c456] [c439] [c436] [c435] [c433] [c432] [c431] [c429] [c426] [c425] [c424] [c423] [c422] [c421] [c419] [e13] [j90] [c418] [c417] [c414] [c413] [c412] [c410] [c409] [c406] [c405] [c404] [c403] [c402] [c400] [c399] [c398] [c396] [c395] [c387] [j87] [j83] [j82] [j81] [c386] [c385] [c382] [c379] [c378] [c375] [c373] [c371] [c370] [c369] [c362] [c359] [c358] [c357] [i8] [j76] [c353] [c352] [c351] [c348] [c347] [c345] [c344] [c343] [c342] [c337] [c335] [c334] [c333] [c332] [c331] [c330] [c329] [c328] [c327] [j74] [j73] [j72] [j71] [c326] [c323] [c322] [c321] [c319] [c318] [c317] [c314] [c312] [c310] [c308] [c307] [c306] [c304] [c302] [c301] [c300] [c299] [j69] [j68] [c298] [c297] [c296] [c295] [c291] [c289] [c286] [c285] [c283] [c281] [c279] [c278] [c277] [i5] [b11] [j63] [j62] [c276] [c275] [c272] [c271] [c267] [c265] [c262] [c261] [c257] [c256] [c255] [c254] [j56] [j55] [c248] [c245] [c240] [c239] [c236] [c235] [c232] [c228] [c227] [i2] [c222] [c221] [c220] [c215] [c214] [c211] [c209] [c190] [c187] [c186]
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