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ORCIDD. Michael Miller
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- affiliation: University of Victoria, Canada
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2020 – today
- 2021
[j34]D. Michael Miller
, Gerhard W. Dueck:
Function translations and search-based transformation for MVL reversible circuit synthesis. Sci. Comput. Program. 212: 102704 (2021)- [c58]D. Michael Miller, Gerhard W. Dueck:
Descending Order Transformation-based Synthesis of MVL Reversible Circuits. ISMVL 2021: 107-112 - 2020
- [j33]D. Michael Miller, Mathias Soeken:
A Spectral Algorithm for 3-valued Function Equivalence Classification. J. Multiple Valued Log. Soft Comput. 34(3-4): 203-221 (2020) - [c57]Kaitlin N. Smith, Mitchell A. Thornton, D. Michael Miller:
Fast Minimization of Polynomial Decomposition using Fixed-Polarity Pascal Transforms. ISMVL 2020: 259-264 - [c56]D. Michael Miller, Gerhard W. Dueck:
Search-Based Transformation Synthesis for 3-Valued Reversible Circuits. RC 2020: 218-236
2010 – 2019
- 2019
- [c55]Mathias Soeken, Eleonora Testa, D. Michael Miller:
A Hybrid Method for Spectral Translation Equivalent Boolean Functions. PACRIM 2019: 1-6 - 2018
- [c54]D. Michael Miller, Mathias Soeken:
A Spectral Algorithm for Ternary Function Classification. ISMVL 2018: 198-203 - 2016
- [j32]Chikatoshi Yamada, D. Michael Miller:
Using SPIN to Check Simulink Stateflow Models. Int. J. Networked Distributed Comput. 4(1): 65-74 (2016) - [j31]Chikatoshi Yamada, D. Michael Miller:
Using SPIN to Check Simulink Stateflow Models. Int. J. Networked Distributed Comput. 4(3): 193-202 (2016) - [j30]Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler:
Embedding of Large Boolean Functions for Reversible Logic. ACM J. Emerg. Technol. Comput. Syst. 12(4): 41:1-41:26 (2016) - [j29]Philipp Niemann, Robert Wille, D. Michael Miller, Mitchell A. Thornton, Rolf Drechsler:
QMDDs: Efficient Quantum Function Representation and Manipulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(1): 86-99 (2016) - [c53]Mathias Soeken, Gerhard W. Dueck, Md. Mazder Rahman, D. Michael Miller:
An extension of transformation-based reversible and quantum circuit synthesis. ISCAS 2016: 2290-2293 - [c52]Mathias Soeken, Gerhard W. Dueck, D. Michael Miller:
A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. RC 2016: 307-321 - 2015
- [c51]Chikatoshi Yamada, D. Michael Miller:
Using SPIN to check Simulink Stateflow models. ICIS 2015: 161-166 - [c50]Chikatoshi Yamada, D. Michael Miller:
Using SPIN to Check Nondeterministic Simulink Stateflow Models. ISMVL 2015: 145-151 - [c49]Radomir S. Stankovic, D. Michael Miller:
Using QMDD in Numerical Methods for Solving Linear Differential Equations via Walsh Functions. ISMVL 2015: 182-188 - [i4]Mathias Soeken, Michael Kirkedal Thomsen, Gerhard W. Dueck, D. Michael Miller:
Self-Inverse Functions and Palindromic Circuits. CoRR abs/1502.05825 (2015) - 2014
- [j28]Robert Wille, Mathias Soeken, D. Michael Miller, Rolf Drechsler:
Trading off circuit lines and gate costs in the synthesis of reversible logic. Integr. 47(2): 284-294 (2014) - [j27]Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller:
Reversible, Information-Preserving Logic and Its Application. J. Multiple Valued Log. Soft Comput. 23(3-4): 379-406 (2014) - [c48]D. Michael Miller, Mathias Soeken, Rolf Drechsler:
Mapping NCV Circuits to Optimized Clifford+T Circuits. RC 2014: 163-175 - [i3]Mathias Soeken, Robert Wille, Oliver Keszöcze, D. Michael Miller, Rolf Drechsler:
Embedding of Large Boolean Functions for Reversible Logic. CoRR abs/1408.3586 (2014) - 2013
- [e3]Gerhard W. Dueck, D. Michael Miller:
Reversible Computation - 5th International Conference, RC 2013, Victoria, BC, Canada, July 4-5, 2013. Proceedings. Lecture Notes in Computer Science 7948, Springer 2013, ISBN 978-3-642-38985-6 [contents] - [i2]Mathias Soeken, D. Michael Miller, Rolf Drechsler:
On quantum circuits employing roots of the Pauli matrices. CoRR abs/1308.2493 (2013) - [i1]Zahra Sasanian, Robert Wille, D. Michael Miller:
Clarification on the Mapping of Reversible Circuits to the NCV-v1 Library. CoRR abs/1309.1419 (2013) - 2012
- [j26]Zahra Sasanian, D. Michael Miller:
Mapping a Multiple-control Toffoli Gate Cascade to an Elementary Quantum Gate Circuit. J. Multiple Valued Log. Soft Comput. 18(1): 83-98 (2012) - [j25]Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller:
Synthesis of Semi-Classical Quantum Circuits. J. Multiple Valued Log. Soft Comput. 18(1): 99-114 (2012) - [j24]D. Michael Miller, Robert Wille, Rolf Drechsler:
Reducing Reversible Circuit Cost by Adding Lines. J. Multiple Valued Log. Soft Comput. 19(1-3): 185-201 (2012) - [j23]Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler:
Equivalence Checking of Reversible Circuits. J. Multiple Valued Log. Soft Comput. 19(4): 361-378 (2012) - [j22]Martin Lukac, Michitaka Kameyama, D. Michael Miller, Marek A. Perkowski:
High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation? J. Multiple Valued Log. Soft Comput. 20(1-2): 89-120 (2012) - [c47]Zahra Sasanian, Robert Wille, D. Michael Miller:
Realizing reversible circuits using a new class of quantum gates. DAC 2012: 36-41 - [c46]D. Michael Miller, Zahra Sasanian:
Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries. ISED 2012: 17-22 - [c45]Mathias Soeken, Zahra Sasanian, Robert Wille, D. Michael Miller, Rolf Drechsler:
Optimizing the Mapping of Reversible Circuits to Four-Valued Quantum Gate Circuits. ISMVL 2012: 173-178 - [c44]Zahra Sasanian, D. Michael Miller:
Reversible and Quantum Circuit Optimization: A Functional Approach. RC 2012: 112-124 - [e2]D. Michael Miller, Vincent C. Gaudet:
42nd IEEE International Symposium on Multiple-Valued Logic, ISMVL 2012, Victoria, BC, Canada, May 14-16, 2012. IEEE Computer Society 2012, ISBN 978-1-4673-0908-0 [contents] - 2011
- [c43]Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller:
Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation. ISMVL 2011: 131-138 - [c42]D. Michael Miller, Robert Wille, Zahra Sasanian:
Elementary Quantum Gate Realizations for Multiple-Control Toffoli Gates. ISMVL 2011: 288-293 - [c41]Zahra Sasanian, D. Michael Miller:
Transforming MCT Circuits to NCVW Circuits. RC 2011: 77-88 - 2010
- [c40]D. Michael Miller, Robert Wille, Rolf Drechsler:
Reducing Reversible Circuit Cost by Adding Lines. ISMVL 2010: 217-222 - [c39]Stanislav Stankovic, Jaakko Astola, D. Michael Miller, Radomir S. Stankovic:
Heterogeneous Decision Diagrams for Applications in Harmonic Analysis on Finite Non-Abelian Groups. ISMVL 2010: 307-312
2000 – 2009
- 2009
- [j21]David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller:
Minimization of Quantum Multiple-valued Decision Diagrams Using Data Structure Metrics. J. Multiple Valued Log. Soft Comput. 15(4): 361-377 (2009) - [c38]D. Michael Miller, Robert Wille, Gerhard W. Dueck:
Synthesizing Reversible Circuits for Irreversible Functions. DSD 2009: 749-756 - [c37]D. Michael Miller, Radomir S. Stankovic:
A Heterogeneous Decision Diagram Package. EUROCAST 2009: 540-547 - [c36]Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler:
Equivalence Checking of Reversible Circuits. ISMVL 2009: 324-330 - [c35]Robert Wille, Daniel Große, D. Michael Miller, Rolf Drechsler:
Equivalence Checking of Reversible Circuits. MBMV 2009: 67-76 - 2008
- [b3]D. Michael Miller, Mitchell Aaron Thornton:
Multiple Valued Logic - Concepts and Representations. Synthesis lectures on digital circuits and systems 12, Morgan & Claypool Publishers 2008, ISBN 978-1-59829-190-2, pp. I-XIII, 1-135 - [j20]Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller:
DDMF: An Efficient Decision Diagram Structure for Design Verification of Quantum Circuits under a Practical Restriction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3793-3802 (2008) - [j19]Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, Camille Negrevergne:
Quantum Circuit Simplification and Level Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 436-444 (2008) - [c34]Shigeru Yamashita, Shin-ichi Minato, D. Michael Miller:
An efficient verification of quantum circuits under a practical restriction. CIT 2008: 873-879 - [c33]David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller:
Partially Redundant Logic Detection Using Symbolic Equivalence Checking in Reversible and Irreversible Logic Circuits. DATE 2008: 1378-1381 - [c32]David Y. Feinstein, Mitchell A. Thornton, D. Michael Miller:
On the Data Structure Metrics of Quantum Multiple-Valued Decision Diagrams. ISMVL 2008: 138-143 - [c31]Mitchell A. Thornton, David W. Matula, Laura Spenner, D. Michael Miller:
Quantum Logic Implementation of Unary Arithmetic Operations. ISMVL 2008: 202-207 - 2007
- [b2]D. Michael Miller, Mitchell A. Thornton:
Multiple Valued Logic: Concepts and Representations. Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers 2007, ISBN 978-3-031-79778-1 - [j18]Dmitri Maslov, D. Michael Miller:
Comparison of the cost metrics through investigation of the relation between optimal NCV and optimal NCT three-qubit reversible circuits. IET Comput. Digit. Tech. 1(2): 98-104 (2007) - [j17]D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton:
QMDD Minimization Using Sifting for Variable Reordering. J. Multiple Valued Log. Soft Comput. 13(4-6): 537-552 (2007) - [j16]Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Design Autom. Electr. Syst. 12(4): 42 (2007) - [c30]D. Michael Miller, David Y. Feinstein, Mitchell A. Thornton:
Variable Reordering and Sifting for QMDD. ISMVL 2007: 10 - 2006
- [j15]D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck:
Synthesis of Quantum Multiple-Valued Circuits. J. Multiple Valued Log. Soft Comput. 12(5-6): 431-450 (2006) - [c29]D. Michael Miller, Mitchell A. Thornton, David Goodman:
A Decision Diagram Package for Reversible and Quantum Circuit Simulation. IEEE Congress on Evolutionary Computation 2006: 2428-2435 - [c28]D. Michael Miller, Mitchell A. Thornton:
QMDD: A Decision Diagram Structure for Reversible and Quantum Circuits. ISMVL 2006: 30 - 2005
- [j14]Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Toffoli network synthesis with templates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(6): 807-817 (2005) - [j13]Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Synthesis of Fredkin-Toffoli reversible networks. IEEE Trans. Very Large Scale Integr. Syst. 13(6): 765-769 (2005) - [c27]Dmitri Maslov, Christina Young, D. Michael Miller, Gerhard W. Dueck:
Quantum Circuit Simplification Using Templates. DATE 2005: 1208-1213 - 2004
- [j12]Mitchell A. Thornton, D. Michael Miller:
Computation of Discrete Function Chrestenson Spectrum Using Cayley Color Graphs. J. Multiple Valued Log. Soft Comput. 10(2): 189-202 (2004) - [c26]D. Michael Miller, Gerhard W. Dueck, Dmitri Maslov:
A Synthesis Method for MVL Reversible Logi. ISMVL 2004: 74-80 - [e1]Christine W. Chan, Witold Kinsner, Yingxu Wang, D. Michael Miller:
Proceedings of the 3rd IEEE International Conference on Cognitive Informatics (ICCI 2004), 16-17 August 2004, Victoria, Canada. IEEE Computer Society 2004, ISBN 0-7695-2190-8 [contents] - 2003
- [j11]Ali Sheikholeslami, D. Michael Miller:
Introduction: Special Issue in Recognition of Kenneth C. Smith. J. Multiple Valued Log. Soft Comput. 9(1): 1-3 (2003) - [c25]D. Michael Miller, Dmitri Maslov, Gerhard W. Dueck:
A transformation based algorithm for reversible logic synthesis. DAC 2003: 318-323 - [c24]Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Fredkin/Toffoli Templates for Reversible Logic Synthesis. ICCAD 2003: 256-261 - [c23]D. Michael Miller, Gerhard W. Dueck:
On the Size of Multiple-Valued Decision Diagrams. ISMVL 2003: 235-240 - [c22]D. Michael Miller, Rolf Drechsler:
Augmented Sifting of Multiple-Valued Decision Diagrams. ISMVL 2003: 375-382 - [c21]Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Simplification of Toffoli Networks via Templates. SBCCI 2003: 53- - 2002
- [c20]Whitney J. Townsend, Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller:
Computing walsh, arithmetic, and reed-muller spectral decision diagrams using graph transformations. ACM Great Lakes Symposium on VLSI 2002: 178-183 - [c19]Mitchell A. Thornton, D. Michael Miller, Whitney J. Townsend:
Chrestenson Spectrum Computation Using Cayley Color Graphs. ISMVL 2002: 123-129 - [c18]D. Michael Miller, Rolf Drechsler:
On the Construction of Multiple-Valued Decision Diagrams. ISMVL 2002: 245-253 - [c17]Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller:
Multi-Output Timed Shannon Circuits. ISVLSI 2002: 47-52 - 2001
- [b1]Mitchell Aaron Thornton, Rolf Drechsler, D. Michael Miller:
Spectral techniques in VLSI CAD. Kluwer 2001, ISBN 978-0-7923-7433-6, pp. I-XIII, 1-250 - 2000
- [c16]Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio:
TOP: An Algorithm for Three-Level Optimization of PLDs. DATE 2000: 751 - [c15]Yasunori Nagata, D. Michael Miller, Masao Mukaidono:
Logic Synthesis of Controllers for B-Ternary Asynchronous Systems. ISMVL 2000: 402-410
1990 – 1999
- 1999
- [c14]Yasunori Nagata, D. Michael Miller, Masao Mukaidono:
B-ternary Logic Based Asynchronous Micropipeline. ISMVL 1999: 214-219 - 1998
- [j10]D. Michael Miller:
An improved method for computing a generalized spectral coefficient. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(3): 233-238 (1998) - [c13]Yasunori Nagata, D. Michael Miller, Masao Mukaidono:
Minimal Test Set Generation for Fault Diagnosis in R-Valued PLAs. ISMVL 1998: 38-44 - [c12]D. Michael Miller, Rolf Drechsler:
Implementing a Multiple-Valued Decision Diagram Package. ISMVL 1998: 52-57 - 1996
- [j9]Shujian Zhang, D. Michael Miller, Jon C. Muzio:
Notes on "Complexity of the lookup-table minimization problem for FPGA technology mapping". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1588-1590 (1996) - [c11]D. Michael Miller:
A spectral method for Boolean function matching. ED&TC 1996: 602 - [c10]Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller:
A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs. ISMVL 1996: 92-97 - [c9]D. Michael Miller, Noriaki Muranaka:
Multiple-Valued Decision Diagrams with Symmetric Variable Nodes. ISMVL 1996: 242-247 - 1995
- [j8]Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller:
Quantitative analysis for linear hybrid cellular automata and LFSR as built-in self-test generators for sequential faults. J. Electron. Test. 7(3): 209-221 (1995) - 1994
- [c8]Shujian Zhang, Rod Byrne, Jon C. Muzio, D. Michael Miller:
Why Cellular Automata are better than LFSRs as Built-in Self-test Generators for Sequential-type Faults. ISCAS 1994: 69-72 - [c7]D. Michael Miller:
Spectral Transformation of Multiple-Valued Decision Diagrams. ISMVL 1994: 89-96 - 1993
- [c6]D. Michael Miller:
Multiple-Valued Logic Design Tools. ISMVL 1993: 2-11 - [c5]Noriaki Muranaka, Shigeru Imanishi, D. Michael Miller:
Decimal Addition and Subtraction Units Using the p-Valued Decimal Signed-Digit Number Representation. ISMVL 1993: 228-233 - 1992
- [j7]D. M. Marcynuk, D. Michael Miller:
The OR-k method for on-line checking of programmable logic arrays. J. Electron. Test. 3(1): 53-65 (1992) - [c4]Shujian Zhang, Rod Byrne, D. Michael Miller:
BIST Generators for Sequential Faults. ICCD 1992: 260-263 - [c3]Randal Tomczuk, D. Michael Miller:
Autocorrelation Techniques for Multi-Bit Decoder PLAs. ISMVL 1992: 355-364 - 1990
- [j6]Micaela Serra, Terry Slater, Jon C. Muzio, D. Michael Miller:
The analysis of one-dimensional linear cellular automata and their aliasing properties. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(7): 767-778 (1990) - [c2]D. Michael Miller, Shujian Zhang, Werner Pries, Robert D. McLeod:
Estimating aliasing in CA and LFSR based signature registers. ICCD 1990: 157-160 - [c1]Gerhard W. Dueck, D. Michael Miller:
RCM-MVL: A Recursive Consensus MVL Minimization Algorithm. ISMVL 1990: 136-143
1980 – 1989
- 1989
- [j5]Peter D. Hortensius, Robert D. McLeod, Werner Pries, D. Michael Miller, Howard C. Card:
Cellular automata-based pseudorandom number generators for built-in self-test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(8): 842-859 (1989) - 1984
- [j4]D. Michael Miller, Jon C. Muzio:
Spectral Fault Signatures for Single Stuck-At Faults in Combinational Networks. IEEE Trans. Computers 33(8): 765-769 (1984) - 1983
- [j3]D. Michael Miller, Jon C. Muzio:
Spectral Fault Signatures for Internally Unate Combinational Networks. IEEE Trans. Computers 32(11): 1058-1062 (1983) - 1980
- [j2]D. Michael Miller, Jon C. Muzio:
A class of two-place three-valued unary generators. Notre Dame J. Formal Log. 21(1): 148-154 (1980)
1970 – 1979
- 1976
- [j1]D. Michael Miller, Jon C. Muzio:
A ternary universal decision element. Notre Dame J. Formal Log. 17(4): 632-637 (1976)
Coauthor Index
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