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EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation

Published: 31 January 2023 Publication History

Abstract

In recent years, hardware systems have significantly grown in complexity. Due to the increasing complexity, there is a need to continuously improve the quality of the hardware design process. This leads designers to strive for more efficient data structures and algorithms operating on them to guarantee the correct behavior of such systems through verification techniques like model checking and meet time-to-market constraints. A Binary Decision Diagram (BDD) is a suitable data structure as it provides a canonical compact representation of Boolean functions, given variable ordering, and efficient algorithms for manipulating them. However, reduced ordered BDDs also have challenges: There is a large memory consumption for the BDD construction of some complex practical functions and the use of realizations in the form of BDD packages strongly depends on the application.
To address these issues, this paper presents a novel multi-core package called Engineer Decision Diagrams Yourself (EDDY) with dynamic memory management and reduced fragmentation. Experiments on BDD benchmarks of both combinational circuits and model checking show that using EDDY leads to a significantly performance boost compared to state-of-the-art packages.

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  • (2023)Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)10.1109/DDECS57882.2023.10139373(73-78)Online publication date: 3-May-2023

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cover image ACM Conferences
ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference
January 2023
807 pages
ISBN:9781450397834
DOI:10.1145/3566097
Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 31 January 2023

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Author Tags

  1. binary decision diagrams
  2. boolean functions
  3. memory management
  4. model checking
  5. parallel computing

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ASPDAC '23 Paper Acceptance Rate 102 of 328 submissions, 31%;
Overall Acceptance Rate 466 of 1,454 submissions, 32%

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  • (2023)Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)10.1109/DDECS57882.2023.10139373(73-78)Online publication date: 3-May-2023

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