research-article

EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation

Authors:

Rolf DrechslerAuthors Info & Claims

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

Pages 423 - 428

https://doi.org/10.1145/3566097.3567913

Published: 31 January 2023 Publication History

Abstract

In recent years, hardware systems have significantly grown in complexity. Due to the increasing complexity, there is a need to continuously improve the quality of the hardware design process. This leads designers to strive for more efficient data structures and algorithms operating on them to guarantee the correct behavior of such systems through verification techniques like model checking and meet time-to-market constraints. A Binary Decision Diagram (BDD) is a suitable data structure as it provides a canonical compact representation of Boolean functions, given variable ordering, and efficient algorithms for manipulating them. However, reduced ordered BDDs also have challenges: There is a large memory consumption for the BDD construction of some complex practical functions and the use of realizations in the form of BDD packages strongly depends on the application.

To address these issues, this paper presents a novel multi-core package called Engineer Decision Diagrams Yourself (EDDY) with dynamic memory management and reduced fragmentation. Experiments on BDD benchmarks of both combinational circuits and model checking show that using EDDY leads to a significantly performance boost compared to state-of-the-art packages.

References

[1]

T. Anderson. 1990. The Performance of Spin Lock Alternatives for Shared-Memory Multiprocessors. IEEE Transactions on Parallel and Distributed Systems 1, 1 (1990), 6--16.

Digital Library

[2]

C. Baier and J. Katoen. 2008. Principles of Model Checking. The MIT Press.

[3]

K. Brace, R. Rudell, and R. Bryant. 1991. Efficient Implementation of a BDD Package. In Proceedings of the 27th ACM/IEEE Design Automation Conference. ACM, New York, NY, USA, 40--45.

Digital Library

[4]

R. Bryant. 1986. Graph-Based Algorithms for Boolean Function Manipulation. IEEE Trans. Comput. 35, 8 (1986), 677--691.

Digital Library

[5]

R. Bryant. 1991. On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication. IEEE Trans. Comput. 40, 3 (1991), 205--213.

Digital Library

[6]

J. Burch, E. Clarke, D. Long, K. McMillan, and D. Dill. 1994. Symbolic model checking for sequential circuit verification. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 13, 4 (1994), 401--424.

Digital Library

[7]

J. Burch, E. Clarke, K. McMillan, D. Dill, and L. Hwang. 1992. Symbolic model checking: 10²⁰ States and beyond. Information and Computation 98, 2 (1992), 142--170.

Digital Library

[8]

S. Chaki and A. Gurfinkel. 2018. BDD-Based Symbolic Model Checking. Springer. 219--245 pages.

[9]

A. Cimatti, E. Clarke, F. Giunchiglia, and M. Roveri. 2000. NUSMV: a new symbolic model checker. International Journal on Software Tools for Technology Transfer 2, 4 (2000), 410--425.

[10]

E. Clarke, E. Emerson, and A. Sistla. 1986. Automatic Verification of Finite-State Concurrent Systems Using Temporal Logic Specifications. ACM Transactions on Programming Languages and Systems 8, 2 (1986), 244--263.

Digital Library

[11]

G. Cong and D. Bader. 2004. Lock-Free Parallel Algorithms: An Experimental Study. In Proceedings of the 11th International Conference on High Performance Computing. Springer, Berlin, Heidelberg, 516--527.

Digital Library

[12]

R. Drechsler and D. Sieling. 2001. Binary decision diagrams in theory and practice. International Journal on Software Tools for Technology Transfer 3, 2 (2001), 112--136.

[13]

G. Janssen. 2001. Design of a Pointerless BDD Package. In International Workshop on Logic and Synthesis. 310--315.

[14]

G. Janssen. 2003. A consumer report on BDD packages. In Proceedings of the 16th Symposium on Integrated Circuits and Systems Design. IEEE Computer Society, USA, 217--222.

[15]

T. Mailund. 2019. The Joys of Hashing. Springer. 21--47 pages.

[16]

K. McMillan. 1993. Symbolic Model Checking. Springer.

Digital Library

[17]

C. Meinel and T. Theobald. 2012. Algorithms and Data Structures in VLSI Design. Springer.

[18]

J. Nielsen. 1996. BuDDy: A BDD package. http://buddy.sourceforge.net/manual

[19]

R. Rajwar and J. Goodman. 2002. Transactional Lock-Free Execution of Lock-Based Programs. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems. ACM, New York, NY, USA, 5--17.

Digital Library

[20]

J. Seiffertt. 2017. Boolean Algebra. Springer. 11--24 pages.

[21]

C. Shannon. 1938. A symbolic analysis of relay and switching circuits. Transactions of the American Institute of Electrical Engineers 57, 12 (1938), 713--723.

[22]

F. Somenzi. 1995. CUDD: CU Decision Diagram Package. http://web.mit.edu/sage/export/tmp/y/usr/share/doc/polybori/cudd

[23]

F. Somenzi. 2001. Efficient manipulation of decision diagrams. International Journal on Software Tools for Technology Transfer 3, 2 (2001), 171--181.

[24]

T. Toda and K. Tsuda. 2015. BDD Construction for All Solutions SAT and Efficient Caching Mechanism. In Proceedings of the 30th Annual ACM Symposium on Applied Computing. ACM, New York, NY, USA, 1880--1886.

Digital Library

[25]

T. van Dijk, E. Hahn, D. Jansen, Y. Li, T. Neele, M. Stoelinga, A. Turrini, and L. Zhang. 2015. A Comparative Study of BDD Packages for Probabilistic Symbolic Model Checking. In Proceedings of the First International Symposium on Dependable Software Engineering. Springer, Berlin, Heidelberg, 35--51.

Digital Library

[26]

T. van Dijk and J. Pol. 2015. Sylvan: Multi-Core Decision Diagrams. In Tools and Algorithms for the Construction and Analysis of Systems. Springer, Berlin, Heidelberg, 677--691.

[27]

J. Wang and W. Tepfenhart. 2019. Propositional Logic. Taylor & Francis. 83--114 pages.

[28]

B. Yang, R. Bryant, D. O'Hallaron, A. Biere, O. Coudert, G. Janssen, R. Ranjan, and F. Somenzi. 1998. A Performance Study of BDD-Based Model Checking. In Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design. Springer, Berlin, Heidelberg, 255--289.

Cited By

Krauss RGoli MDrechsler R(2023)Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)10.1109/DDECS57882.2023.10139373(73-78)Online publication date: 3-May-2023
https://doi.org/10.1109/DDECS57882.2023.10139373

Index Terms

EDDY: A Multi-Core BDD Package with Dynamic Memory Management and Reduced Fragmentation

Recommendations

Chain Reduction for Binary and Zero-Suppressed Decision Diagrams
Abstract
Chain reduction enables reduced ordered binary decision diagrams (BDDs) and zero-suppressed binary decision diagrams (ZDDs) to each take advantage of the other’s ability to symbolically represent Boolean functions in compact form. For any Boolean ...
Using XBDDs and ZBDDs in points-to analysis

Binary decision diagrams (BDDs) have recently become widely accepted as a space-efficient method of representing relations in points-to or reference analyses. When BDDs are used to represent relations, each element of a domain is assigned a bit pattern ...
A Characterization of Binary Decision Diagrams

Binary decision diagrams (BDDs) are a representation of Boolean functions. Its use in the synthesis, simulation, and testing of Boolean circuits has been proposed by various researchers. In all these applications of BDDs solutions to some fundamental ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ASPDAC '23: Proceedings of the 28th Asia and South Pacific Design Automation Conference

January 2023

807 pages

ISBN:9781450397834

DOI:10.1145/3566097

General Chair:
Atsushi Takahashi
Tokyo Institute of Technology

Copyright © 2023 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

In-Cooperation

IPSJ
IEEE CAS
IEEE CEDA
IEICE

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 31 January 2023

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article

Conference

ASPDAC '23

Sponsor:

SIGDA

ASPDAC '23: 28th Asia and South Pacific Design Automation Conference

January 16 - 19, 2023

Tokyo, Japan

Acceptance Rates

ASPDAC '23 Paper Acceptance Rate 102 of 328 submissions, 31%;

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

1
Total Citations
View Citations
88
Total Downloads

Downloads (Last 12 months)32
Downloads (Last 6 weeks)1

Reflects downloads up to 23 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

Krauss RGoli MDrechsler R(2023)Efficient Binary Decision Diagram Manipulation by Reducing the Number of Intermediate Nodes2023 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS)10.1109/DDECS57882.2023.10139373(73-78)Online publication date: 3-May-2023
https://doi.org/10.1109/DDECS57882.2023.10139373

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents